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arch/arm:  Remove support for CONFIG_ARMV7M_CMNVECTOR.  It is now the only vector support available.  Also remove CONFIG_HAVE_CMNVECTOR.  That no longer signifies anything."
    arch/arm/src/stm32:  This commit removes support for the dedicated vector handling from the STM32 architecture support. Only common vectors are now supported.
This commit is contained in:
Gregory Nutt 2018-06-20 12:30:37 -06:00
parent 2ec450f185
commit 8bd9cfe038
247 changed files with 1540 additions and 4809 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
arch/arm/Kconfig
View File

@ -49,9 +49,7 @@ config ARCH_CHIP_DM320
config ARCH_CHIP_EFM32 config ARCH_CHIP_EFM32
bool "Energy Micro" bool "Energy Micro"
select ARCH_HAVE_CMNVECTOR
select ARCH_HAVE_SPI_BITORDER select ARCH_HAVE_SPI_BITORDER
select ARMV7M_CMNVECTOR
select ARCH_HAVE_FETCHADD select ARCH_HAVE_FETCHADD
---help--- ---help---
Energy Micro EFM32 microcontrollers (ARM Cortex-M). Energy Micro EFM32 microcontrollers (ARM Cortex-M).
@ -81,7 +79,6 @@ config ARCH_CHIP_IMX6
config ARCH_CHIP_IMXRT config ARCH_CHIP_IMXRT
bool "NXP/Freescale iMX.RT" bool "NXP/Freescale iMX.RT"
select ARCH_HAVE_CMNVECTOR
select ARCH_CORTEXM7 select ARCH_CORTEXM7
select ARCH_HAVE_MPU select ARCH_HAVE_MPU
select ARCH_HAVE_FETCHADD select ARCH_HAVE_FETCHADD
@ -90,7 +87,6 @@ config ARCH_CHIP_IMXRT
select ARCH_HAVE_I2CRESET select ARCH_HAVE_I2CRESET
select ARCH_HAVE_SPI_CS_CONTROL select ARCH_HAVE_SPI_CS_CONTROL
select ARM_HAVE_MPU_UNIFIED select ARM_HAVE_MPU_UNIFIED
select ARMV7M_CMNVECTOR
select ARMV7M_HAVE_STACKCHECK select ARMV7M_HAVE_STACKCHECK
---help--- ---help---
NXP i.MX RT (ARM Cortex-M7) architectures NXP i.MX RT (ARM Cortex-M7) architectures
@ -103,56 +99,46 @@ config ARCH_CHIP_KINETIS
select ARCH_HAVE_FPU select ARCH_HAVE_FPU
select ARCH_HAVE_FETCHADD select ARCH_HAVE_FETCHADD
select ARCH_HAVE_RAMFUNCS select ARCH_HAVE_RAMFUNCS
select ARCH_HAVE_CMNVECTOR
select ARCH_HAVE_I2CRESET select ARCH_HAVE_I2CRESET
select ARMV7M_CMNVECTOR
---help--- ---help---
Freescale Kinetis Architectures (ARM Cortex-M4) Freescale Kinetis Architectures (ARM Cortex-M4)
config ARCH_CHIP_KL config ARCH_CHIP_KL
bool "NXP/Freescale Kinetis L" bool "NXP/Freescale Kinetis L"
select ARCH_CORTEXM0 select ARCH_CORTEXM0
select ARCH_HAVE_CMNVECTOR
---help--- ---help---
Freescale Kinetis L Architectures (ARM Cortex-M0+) Freescale Kinetis L Architectures (ARM Cortex-M0+)
config ARCH_CHIP_LC823450 config ARCH_CHIP_LC823450
bool "ON Semiconductor LC823450" bool "ON Semiconductor LC823450"
select ARCH_CORTEXM3 select ARCH_CORTEXM3
select ARCH_HAVE_CMNVECTOR
select ARCH_HAVE_MPU select ARCH_HAVE_MPU
select ARCH_HAVE_HEAPCHECK select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_MULTICPU select ARCH_HAVE_MULTICPU
select ARCH_HAVE_I2CRESET select ARCH_HAVE_I2CRESET
select ARCH_GLOBAL_IRQDISABLE select ARCH_GLOBAL_IRQDISABLE
select ARMV7M_CMNVECTOR
---help--- ---help---
ON Semiconductor LC823450 architectures (ARM dual Cortex-M3) ON Semiconductor LC823450 architectures (ARM dual Cortex-M3)
config ARCH_CHIP_LM config ARCH_CHIP_LM
bool "TI/Luminary Stellaris" bool "TI/Luminary Stellaris"
select ARCH_HAVE_CMNVECTOR
select ARCH_HAVE_MPU select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED select ARM_HAVE_MPU_UNIFIED
select ARMV7M_CMNVECTOR
---help--- ---help---
TI/Luminary Stellaris LMS3 and LM4F architectures (ARM Cortex-M3/4) TI/Luminary Stellaris LMS3 and LM4F architectures (ARM Cortex-M3/4)
config ARCH_CHIP_LPC11XX config ARCH_CHIP_LPC11XX
bool "NXP LPC11xx" bool "NXP LPC11xx"
select ARCH_CORTEXM0 select ARCH_CORTEXM0
select ARCH_HAVE_CMNVECTOR
---help--- ---help---
NXP LPC11xx architectures (ARM Cortex-M0) NXP LPC11xx architectures (ARM Cortex-M0)
config ARCH_CHIP_LPC17XX config ARCH_CHIP_LPC17XX
bool "NXP LPC17xx" bool "NXP LPC17xx"
select ARCH_CORTEXM3 select ARCH_CORTEXM3
select ARCH_HAVE_CMNVECTOR
select ARCH_HAVE_MPU select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_FETCHADD select ARCH_HAVE_FETCHADD
select ARMV7M_CMNVECTOR
select ARMV7M_HAVE_STACKCHECK select ARMV7M_HAVE_STACKCHECK
---help--- ---help---
NXP LPC17xx architectures (ARM Cortex-M3) NXP LPC17xx architectures (ARM Cortex-M3)
@ -181,8 +167,6 @@ config ARCH_CHIP_LPC31XX
config ARCH_CHIP_LPC43XX config ARCH_CHIP_LPC43XX
bool "NXP LPC43XX" bool "NXP LPC43XX"
select ARCH_CORTEXM4 select ARCH_CORTEXM4
select ARCH_HAVE_CMNVECTOR
select ARMV7M_CMNVECTOR
select ARCH_HAVE_MPU select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_FPU select ARCH_HAVE_FPU
@ -193,8 +177,6 @@ config ARCH_CHIP_LPC43XX
config ARCH_CHIP_LPC54XX config ARCH_CHIP_LPC54XX
bool "NXP LPC54XX" bool "NXP LPC54XX"
select ARCH_CORTEXM4 select ARCH_CORTEXM4
select ARCH_HAVE_CMNVECTOR
select ARMV7M_CMNVECTOR
select ARCH_HAVE_MPU select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_FPU select ARCH_HAVE_FPU
@ -213,8 +195,6 @@ config ARCH_CHIP_MOXART
config ARCH_CHIP_NRF52 config ARCH_CHIP_NRF52
bool "Nordic NRF52" bool "Nordic NRF52"
select ARCH_CORTEXM4 select ARCH_CORTEXM4
select ARCH_HAVE_CMNVECTOR
select ARMV7M_CMNVECTOR
#select ARCH_HAVE_MPU #select ARCH_HAVE_MPU
#select ARM_HAVE_MPU_UNIFIED #select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_FPU select ARCH_HAVE_FPU
@ -224,7 +204,6 @@ config ARCH_CHIP_NRF52
config ARCH_CHIP_NUC1XX config ARCH_CHIP_NUC1XX
bool "Nuvoton NUC100/120" bool "Nuvoton NUC100/120"
select ARCH_CORTEXM0 select ARCH_CORTEXM0
select ARCH_HAVE_CMNVECTOR
---help--- ---help---
Nuvoton NUC100/120 architectures (ARM Cortex-M0). Nuvoton NUC100/120 architectures (ARM Cortex-M0).
@ -245,32 +224,27 @@ config ARCH_CHIP_SAMA5
config ARCH_CHIP_SAMD config ARCH_CHIP_SAMD
bool "Atmel SAMD" bool "Atmel SAMD"
select ARCH_CORTEXM0 select ARCH_CORTEXM0
select ARCH_HAVE_CMNVECTOR
---help--- ---help---
Atmel SAMD (ARM Cortex-M0+) Atmel SAMD (ARM Cortex-M0+)
config ARCH_CHIP_SAML config ARCH_CHIP_SAML
bool "Atmel SAML" bool "Atmel SAML"
select ARCH_CORTEXM0 select ARCH_CORTEXM0
select ARCH_HAVE_CMNVECTOR
---help--- ---help---
Atmel SAML (ARM Cortex-M0+) Atmel SAML (ARM Cortex-M0+)
config ARCH_CHIP_SAM34 config ARCH_CHIP_SAM34
bool "Atmel SAM3/SAM4" bool "Atmel SAM3/SAM4"
select ARCH_HAVE_CMNVECTOR
select ARCH_HAVE_MPU select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_FETCHADD select ARCH_HAVE_FETCHADD
select ARCH_HAVE_RAMFUNCS select ARCH_HAVE_RAMFUNCS
select ARMV7M_CMNVECTOR
select ARMV7M_HAVE_STACKCHECK select ARMV7M_HAVE_STACKCHECK
---help--- ---help---
Atmel SAM3 (ARM Cortex-M3) and SAM4 (ARM Cortex-M4) architectures Atmel SAM3 (ARM Cortex-M3) and SAM4 (ARM Cortex-M4) architectures
config ARCH_CHIP_SAMV7 config ARCH_CHIP_SAMV7
bool "Atmel SAMV7" bool "Atmel SAMV7"
select ARCH_HAVE_CMNVECTOR
select ARCH_CORTEXM7 select ARCH_CORTEXM7
select ARCH_HAVE_MPU select ARCH_HAVE_MPU
select ARCH_HAVE_FETCHADD select ARCH_HAVE_FETCHADD
@ -279,14 +253,12 @@ config ARCH_CHIP_SAMV7
select ARCH_HAVE_I2CRESET select ARCH_HAVE_I2CRESET
select ARCH_HAVE_SPI_CS_CONTROL select ARCH_HAVE_SPI_CS_CONTROL
select ARM_HAVE_MPU_UNIFIED select ARM_HAVE_MPU_UNIFIED
select ARMV7M_CMNVECTOR
select ARMV7M_HAVE_STACKCHECK select ARMV7M_HAVE_STACKCHECK
---help--- ---help---
Atmel SAMV7 (ARM Cortex-M7) architectures Atmel SAMV7 (ARM Cortex-M7) architectures
config ARCH_CHIP_STM32 config ARCH_CHIP_STM32
bool "STMicro STM32 F1/F2/F3/F4/L1" bool "STMicro STM32 F1/F2/F3/F4/L1"
select ARCH_HAVE_CMNVECTOR
select ARCH_HAVE_MPU select ARCH_HAVE_MPU
select ARCH_HAVE_FETCHADD select ARCH_HAVE_FETCHADD
select ARCH_HAVE_I2CRESET select ARCH_HAVE_I2CRESET
@ -303,13 +275,11 @@ config ARCH_CHIP_STM32
config ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F0
bool "STMicro STM32 F0" bool "STMicro STM32 F0"
select ARCH_CORTEXM0 select ARCH_CORTEXM0
select ARCH_HAVE_CMNVECTOR
---help--- ---help---
STMicro STM32 architectures (ARM Cortex-M0). STMicro STM32 architectures (ARM Cortex-M0).
config ARCH_CHIP_STM32F7 config ARCH_CHIP_STM32F7
bool "STMicro STM32 F7" bool "STMicro STM32 F7"
select ARCH_HAVE_CMNVECTOR
select ARCH_CORTEXM7 select ARCH_CORTEXM7
select ARCH_HAVE_MPU select ARCH_HAVE_MPU
select ARCH_HAVE_FETCHADD select ARCH_HAVE_FETCHADD
@ -317,21 +287,18 @@ config ARCH_CHIP_STM32F7
select ARCH_HAVE_HEAPCHECK select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_SPI_BITORDER select ARCH_HAVE_SPI_BITORDER
select ARM_HAVE_MPU_UNIFIED select ARM_HAVE_MPU_UNIFIED
select ARMV7M_CMNVECTOR
select ARMV7M_HAVE_STACKCHECK select ARMV7M_HAVE_STACKCHECK
---help--- ---help---
STMicro STM32 architectures (ARM Cortex-M7). STMicro STM32 architectures (ARM Cortex-M7).
config ARCH_CHIP_STM32H7 config ARCH_CHIP_STM32H7
bool "STMicro STM32 H7" bool "STMicro STM32 H7"
select ARCH_HAVE_CMNVECTOR
select ARCH_CORTEXM7 select ARCH_CORTEXM7
select ARCH_HAVE_MPU select ARCH_HAVE_MPU
# select ARCH_HAVE_I2CRESET # select ARCH_HAVE_I2CRESET
# select ARCH_HAVE_HEAPCHECK # select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_SPI_BITORDER select ARCH_HAVE_SPI_BITORDER
select ARM_HAVE_MPU_UNIFIED select ARM_HAVE_MPU_UNIFIED
select ARMV7M_CMNVECTOR
# select ARMV7M_HAVE_STACKCHECK # select ARMV7M_HAVE_STACKCHECK
depends on EXPERIMENTAL # Remove when the port is stable depends on EXPERIMENTAL # Remove when the port is stable
---help--- ---help---
@ -344,7 +311,6 @@ config ARCH_CHIP_STM32H7
config ARCH_CHIP_STM32L4 config ARCH_CHIP_STM32L4
bool "STMicro STM32 L4" bool "STMicro STM32 L4"
select ARCH_CORTEXM4 select ARCH_CORTEXM4
select ARCH_HAVE_CMNVECTOR
select ARCH_HAVE_MPU select ARCH_HAVE_MPU
select ARCH_HAVE_FETCHADD select ARCH_HAVE_FETCHADD
select ARCH_HAVE_I2CRESET select ARCH_HAVE_I2CRESET
@ -353,7 +319,6 @@ config ARCH_CHIP_STM32L4
select ARCH_HAVE_SPI_BITORDER select ARCH_HAVE_SPI_BITORDER
select ARCH_HAVE_TICKLESS select ARCH_HAVE_TICKLESS
select ARM_HAVE_MPU_UNIFIED select ARM_HAVE_MPU_UNIFIED
select ARMV7M_CMNVECTOR
select ARMV7M_HAVE_STACKCHECK select ARMV7M_HAVE_STACKCHECK
---help--- ---help---
STMicro STM32 architectures (ARM Cortex-M4). STMicro STM32 architectures (ARM Cortex-M4).
@ -378,25 +343,21 @@ config ARCH_CHIP_TMS570
config ARCH_CHIP_TIVA config ARCH_CHIP_TIVA
bool "TI Tiva" bool "TI Tiva"
select ARCH_HAVE_CMNVECTOR
select ARCH_HAVE_MPU select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_FPU select ARCH_HAVE_FPU
select ARCH_HAVE_FETCHADD select ARCH_HAVE_FETCHADD
select ARMV7M_CMNVECTOR
---help--- ---help---
TI Tiva TM4C architectures (ARM Cortex-M4) TI Tiva TM4C architectures (ARM Cortex-M4)
config ARCH_CHIP_XMC4 config ARCH_CHIP_XMC4
bool "Infineon XMC4xxx" bool "Infineon XMC4xxx"
select ARCH_HAVE_CMNVECTOR
select ARCH_CORTEXM4 select ARCH_CORTEXM4
select ARCH_HAVE_MPU select ARCH_HAVE_MPU
select ARCH_HAVE_FETCHADD select ARCH_HAVE_FETCHADD
select ARCH_HAVE_RAMFUNCS select ARCH_HAVE_RAMFUNCS
select ARCH_HAVE_I2CRESET select ARCH_HAVE_I2CRESET
select ARM_HAVE_MPU_UNIFIED select ARM_HAVE_MPU_UNIFIED
select ARMV7M_CMNVECTOR
select ARMV7M_HAVE_STACKCHECK select ARMV7M_HAVE_STACKCHECK
---help--- ---help---
Infineon XMC4xxx(ARM Cortex-M4) architectures Infineon XMC4xxx(ARM Cortex-M4) architectures
@ -491,6 +452,7 @@ config ARCH_CORTEXM3
default n default n
select ARCH_HAVE_IRQPRIO select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_RAMVECTORS select ARCH_HAVE_RAMVECTORS
select ARCH_HAVE_LAZYFPU
select ARCH_HAVE_HIPRI_INTERRUPT select ARCH_HAVE_HIPRI_INTERRUPT
select ARCH_HAVE_RESET select ARCH_HAVE_RESET
@ -503,6 +465,7 @@ config ARCH_CORTEXM4
default n default n
select ARCH_HAVE_IRQPRIO select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_RAMVECTORS select ARCH_HAVE_RAMVECTORS
select ARCH_HAVE_LAZYFPU
select ARCH_HAVE_HIPRI_INTERRUPT select ARCH_HAVE_HIPRI_INTERRUPT
select ARCH_HAVE_RESET select ARCH_HAVE_RESET
@ -512,6 +475,7 @@ config ARCH_CORTEXM7
select ARCH_HAVE_FPU select ARCH_HAVE_FPU
select ARCH_HAVE_IRQPRIO select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_RAMVECTORS select ARCH_HAVE_RAMVECTORS
select ARCH_HAVE_LAZYFPU
select ARCH_HAVE_HIPRI_INTERRUPT select ARCH_HAVE_HIPRI_INTERRUPT
select ARCH_HAVE_RESET select ARCH_HAVE_RESET
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
@ -634,23 +598,13 @@ config ARMV7M_USEBASEPRI
register, these hardfaults, will be avoided. For more details see register, these hardfaults, will be avoided. For more details see
http://www.nuttx.org/doku.php?id=wiki:nxinternal:svcall http://www.nuttx.org/doku.php?id=wiki:nxinternal:svcall
config ARCH_HAVE_CMNVECTOR config ARCH_HAVE_LAZYFPU
bool bool
config ARMV7M_CMNVECTOR
bool "Use common ARMv7-M vectors"
default n
depends on ARCH_HAVE_CMNVECTOR
---help---
Some architectures use their own, built-in vector logic. Some use only
the common vector logic. Some can use either their own built-in vector
logic or the common vector logic. This applies only to ARMv7-M
architectures.
config ARMV7M_LAZYFPU config ARMV7M_LAZYFPU
bool "Lazy FPU storage" bool "Lazy FPU storage"
default n default n
depends on ARCH_HAVE_CMNVECTOR depends on ARCH_HAVE_LAZYFPU
---help--- ---help---
There are two forms of the common vector logic. There are pros and There are two forms of the common vector logic. There are pros and
cons to each option: cons to each option:

2
arch/arm/include/armv7-m/irq.h
View File

@ -55,7 +55,7 @@
/* Included implementation-dependent register save structure layouts */ /* Included implementation-dependent register save structure layouts */
#if defined(CONFIG_ARMV7M_CMNVECTOR) && !defined(CONFIG_ARMV7M_LAZYFPU) #ifndef CONFIG_ARMV7M_LAZYFPU
# include <arch/armv7-m/irq_cmnvector.h> # include <arch/armv7-m/irq_cmnvector.h>
#else #else
# include <arch/armv7-m/irq_lazyfpu.h> # include <arch/armv7-m/irq_lazyfpu.h>

8
arch/arm/include/stm32/stm32f10xxx_irq.h
View File

@ -1,7 +1,7 @@
/************************************************************************************ /************************************************************************************
* arch/arm/include/stm32/stm32f10xxx_irq.h * arch/arm/include/stm32/stm32f10xxx_irq.h
* *
* Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved. * Copyright (C) 2009, 2012, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -129,7 +129,7 @@
# define STM32_IRQ_DMA2CH45 (75) /* 59: DMA2 Channel 4 and 5 global interrupt */ # define STM32_IRQ_DMA2CH45 (75) /* 59: DMA2 Channel 4 and 5 global interrupt */
# define STM32_IRQ_DMA2CH5 (76) /* 60: DMA2 Channel 5 global interrupt */ # define STM32_IRQ_DMA2CH5 (76) /* 60: DMA2 Channel 5 global interrupt */
# define NR_VECTORS (77) # define STM32_IRQ_NEXTINT (61)
# define NR_IRQS (77) # define NR_IRQS (77)
/* Connectivity Line Devices */ /* Connectivity Line Devices */
@ -204,7 +204,7 @@
# define STM32_IRQ_CAN2SCE (82) /* 66: CAN2 SCE interrupt */ # define STM32_IRQ_CAN2SCE (82) /* 66: CAN2 SCE interrupt */
# define STM32_IRQ_OTGFS (83) /* 67: USB On The Go FS global interrupt */ # define STM32_IRQ_OTGFS (83) /* 67: USB On The Go FS global interrupt */
# define NR_VECTORS (84) # define STM32_IRQ_NEXTINT (68)
# define NR_IRQS (84) # define NR_IRQS (84)
/* Medium and High Density Devices */ /* Medium and High Density Devices */
@ -271,7 +271,7 @@
# define STM32_IRQ_DMA2CH3 (74) /* 58: DMA2 Channel 3 global interrupt */ # define STM32_IRQ_DMA2CH3 (74) /* 58: DMA2 Channel 3 global interrupt */
# define STM32_IRQ_DMA2CH45 (75) /* 59: DMA2 Channel 4&5 global interrupt */ # define STM32_IRQ_DMA2CH45 (75) /* 59: DMA2 Channel 4&5 global interrupt */
# define NR_VECTORS (76) # define STM32_IRQ_NEXTINT (60)
# define NR_IRQS (76) # define NR_IRQS (76)
/* Convenience definitions for interrupts with multiple functions */ /* Convenience definitions for interrupts with multiple functions */

4
arch/arm/include/stm32/stm32f20xxx_irq.h
View File

@ -1,7 +1,7 @@
/**************************************************************************************************** /****************************************************************************************************
* arch/arm/include/stm32/stm32f20xxx_irq.h * arch/arm/include/stm32/stm32f20xxx_irq.h
* *
* Copyright (C) 2012 Gregory Nutt. All rights reserved. * Copyright (C) 2012, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -150,7 +150,7 @@
#define STM32_IRQ_HASH (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */ #define STM32_IRQ_HASH (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
#define STM32_IRQ_RNG (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */ #define STM32_IRQ_RNG (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
#define NR_VECTORS (STM32_IRQ_FIRST+81) #define STM32_IRQ_NEXTINT (81)
#define NR_IRQS (STM32_IRQ_FIRST+81) #define NR_IRQS (STM32_IRQ_FIRST+81)
/**************************************************************************************************** /****************************************************************************************************

4
arch/arm/include/stm32/stm32f30xxx_irq.h
View File

@ -1,7 +1,7 @@
/**************************************************************************************************** /****************************************************************************************************
* arch/arm/include/stm32/stm32f30xxx_irq.h * arch/arm/include/stm32/stm32f30xxx_irq.h
* *
* Copyright (C) 2012 Gregory Nutt. All rights reserved. * Copyright (C) 2012, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -161,7 +161,7 @@
#define STM32_IRQ_RESERVED80 (STM32_IRQ_FIRST+80) /* 80: Reserved */ #define STM32_IRQ_RESERVED80 (STM32_IRQ_FIRST+80) /* 80: Reserved */
#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */ #define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
#define NR_VECTORS (STM32_IRQ_FIRST+82) #define STM32_IRQ_NEXTINT (82)
#define NR_IRQS (STM32_IRQ_FIRST+82) #define NR_IRQS (STM32_IRQ_FIRST+82)
/**************************************************************************************************** /****************************************************************************************************

4
arch/arm/include/stm32/stm32f33xxx_irq.h
View File

@ -1,7 +1,7 @@
/**************************************************************************************************** /****************************************************************************************************
* arch/arm/include/stm32/stm32f33xxx_irq.h * arch/arm/include/stm32/stm32f33xxx_irq.h
* *
* Copyright (C) 2017 Gregory Nutt. All rights reserved. * Copyright (C) 2017, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* Modified for STM32F334 by Mateusz Szafoni <raiden00@railab.me> * Modified for STM32F334 by Mateusz Szafoni <raiden00@railab.me>
* *
@ -152,7 +152,7 @@
#define STM32_IRQ_RESERVED80 (STM32_IRQ_FIRST+80) /* 80: Reserved */ #define STM32_IRQ_RESERVED80 (STM32_IRQ_FIRST+80) /* 80: Reserved */
#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */ #define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
#define NR_VECTORS (STM32_IRQ_FIRST+82) #define STM32_IRQ_NEXTINT (82)
#define NR_IRQS (STM32_IRQ_FIRST+82) #define NR_IRQS (STM32_IRQ_FIRST+82)
/**************************************************************************************************** /****************************************************************************************************

4
arch/arm/include/stm32/stm32f37xxx_irq.h
View File

@ -1,7 +1,7 @@
/**************************************************************************************************** /****************************************************************************************************
* arch/arm/include/stm32/stm32f37xxx_irq.h * arch/arm/include/stm32/stm32f37xxx_irq.h
* *
* Copyright (C) 2012 Gregory Nutt. All rights reserved. * Copyright (C) 2012, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* Modified for STM32F373 by Marten Svanfeldt <marten@svanfeldt.com> * Modified for STM32F373 by Marten Svanfeldt <marten@svanfeldt.com>
* *
@ -147,7 +147,7 @@
#define STM32_IRQ_RESERVED80 (STM32_IRQ_FIRST+80) /* 80: Reserved */ #define STM32_IRQ_RESERVED80 (STM32_IRQ_FIRST+80) /* 80: Reserved */
#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */ #define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
#define NR_VECTORS (STM32_IRQ_FIRST+82) #define STM32_IRQ_NEXTINT (82)
#define NR_IRQS (STM32_IRQ_FIRST+82) #define NR_IRQS (STM32_IRQ_FIRST+82)
/**************************************************************************************************** /****************************************************************************************************

14
arch/arm/include/stm32/stm32f40xxx_irq.h
View File

@ -1,7 +1,7 @@
/**************************************************************************************************** /****************************************************************************************************
* arch/arm/include/stm32/stm32f40xxx_irq.h * arch/arm/include/stm32/stm32f40xxx_irq.h
* *
* Copyright (C) 2009, 2014-2015, 2017 Gregory Nutt. All rights reserved. * Copyright (C) 2009, 2014-2015, 2017-2018 Gregory Nutt. All rights reserved.
* Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved. * Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com> * David Sidrane <david_s5@nscdg.com>
@ -321,22 +321,22 @@
#if defined(CONFIG_STM32_STM32F401) || defined(CONFIG_STM32_STM32F411) || \ #if defined(CONFIG_STM32_STM32F401) || defined(CONFIG_STM32_STM32F411) || \
defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407) defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407)
# define NR_VECTORS (STM32_IRQ_FIRST+82) # define STM32_IRQ_NEXTINT (82)
# define NR_IRQS (STM32_IRQ_FIRST+82) # define NR_IRQS (STM32_IRQ_FIRST+82)
#elif defined(CONFIG_STM32_STM32F410) #elif defined(CONFIG_STM32_STM32F410)
# define NR_VECTORS (STM32_IRQ_FIRST+98) # define STM32_IRQ_NEXTINT (98)
# define NR_IRQS (STM32_IRQ_FIRST+98) # define NR_IRQS (STM32_IRQ_FIRST+98)
#elif defined(CONFIG_STM32_STM32F427) #elif defined(CONFIG_STM32_STM32F427)
# define NR_VECTORS (STM32_IRQ_FIRST+87) # define STM32_IRQ_NEXTINT (87)
# define NR_IRQS (STM32_IRQ_FIRST+87) # define NR_IRQS (STM32_IRQ_FIRST+87)
#elif defined(CONFIG_STM32_STM32F429) #elif defined(CONFIG_STM32_STM32F429)
# define NR_VECTORS (STM32_IRQ_FIRST+91) # define STM32_IRQ_NEXTINT (91)
# define NR_IRQS (STM32_IRQ_FIRST+91) # define NR_IRQS (STM32_IRQ_FIRST+91)
#elif defined(CONFIG_STM32_STM32F446) #elif defined(CONFIG_STM32_STM32F446)
# define NR_VECTORS (STM32_IRQ_FIRST+97) # define STM32_IRQ_NEXTINT (97)
# define NR_IRQS (STM32_IRQ_FIRST+97) # define NR_IRQS (STM32_IRQ_FIRST+97)
#elif defined(CONFIG_STM32_STM32F469) #elif defined(CONFIG_STM32_STM32F469)
# define NR_VECTORS (STM32_IRQ_FIRST+93) # define STM32_IRQ_NEXTINT (93)
# define NR_IRQS (STM32_IRQ_FIRST+93) # define NR_IRQS (STM32_IRQ_FIRST+93)
#endif #endif

8
arch/arm/include/stm32/stm32l15xxx_irq.h
View File

@ -2,7 +2,7 @@
* arch/arm/include/stm32/stm32l15xxx_irq.h * arch/arm/include/stm32/stm32l15xxx_irq.h
* For STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx advanced ARM-based 32-bit MCUs * For STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx advanced ARM-based 32-bit MCUs
* *
* Copyright (C) 2013 Gregory Nutt. All rights reserved. * Copyright (C) 2013, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -108,7 +108,7 @@
# define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+43) /* 43: TIM6 global interrupt */ # define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+43) /* 43: TIM6 global interrupt */
# define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+44) /* 44: TIM7 global interrupt */ # define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+44) /* 44: TIM7 global interrupt */
# define NR_VECTORS (STM32_IRQ_FIRST+45) # define STM32_IRQ_NEXTINT (45)
# define NR_IRQS (STM32_IRQ_FIRST+45) # define NR_IRQS (STM32_IRQ_FIRST+45)
/* External interrupts (vectors >= 16) medium+ density devices */ /* External interrupts (vectors >= 16) medium+ density devices */
@ -171,7 +171,7 @@
# define STM32_IRQ_AES (STM32_IRQ_FIRST+52) /* 52: AES global interrupt */ # define STM32_IRQ_AES (STM32_IRQ_FIRST+52) /* 52: AES global interrupt */
# define STM32_IRQ_COMPACQ (STM32_IRQ_FIRST+53) /* 53: Comparator Channel Acquisition Interrupt */ # define STM32_IRQ_COMPACQ (STM32_IRQ_FIRST+53) /* 53: Comparator Channel Acquisition Interrupt */
# define NR_VECTORS (STM32_IRQ_FIRST+54) # define STM32_IRQ_NEXTINT (54)
# define NR_IRQS (STM32_IRQ_FIRST+54) # define NR_IRQS (STM32_IRQ_FIRST+54)
/* External interrupts (vectors >= 16) high density devices */ /* External interrupts (vectors >= 16) high density devices */
@ -237,7 +237,7 @@
# define STM32_IRQ_AES (STM32_IRQ_FIRST+55) /* 55: AES global interrupt */ # define STM32_IRQ_AES (STM32_IRQ_FIRST+55) /* 55: AES global interrupt */
# define STM32_IRQ_COMPACQ (STM32_IRQ_FIRST+56) /* 56: Comparator Channel Acquisition Interrupt */ # define STM32_IRQ_COMPACQ (STM32_IRQ_FIRST+56) /* 56: Comparator Channel Acquisition Interrupt */
# define NR_VECTORS (STM32_IRQ_FIRST+57) # define STM32_IRQ_NEXTINT (57)
# define NR_IRQS (STM32_IRQ_FIRST+57) # define NR_IRQS (STM32_IRQ_FIRST+57)
#else #else
# error "Unknown STM32L density" # error "Unknown STM32L density"

2
arch/arm/src/Makefile
View File

@ -174,10 +174,8 @@ VPATH += common
VPATH += $(ARCH_SUBDIR) VPATH += $(ARCH_SUBDIR)
ifeq ($(CONFIG_ARCH_TOOLCHAIN_IAR),y) ifeq ($(CONFIG_ARCH_TOOLCHAIN_IAR),y)
VPATH += chip$(DELIM)iar
VPATH += $(ARCH_SUBDIR)$(DELIM)iar VPATH += $(ARCH_SUBDIR)$(DELIM)iar
else # ifeq ($(CONFIG_ARCH_TOOLCHAIN_GNU),y) else # ifeq ($(CONFIG_ARCH_TOOLCHAIN_GNU),y)
VPATH += chip$(DELIM)gnu
VPATH += $(ARCH_SUBDIR)$(DELIM)gnu VPATH += $(ARCH_SUBDIR)$(DELIM)gnu
endif endif

4
arch/arm/src/armv7-m/exc_return.h
View File

@ -93,7 +93,7 @@
* state from the main stack. Execution uses MSP after return. * state from the main stack. Execution uses MSP after return.
*/ */
#if defined(CONFIG_ARMV7M_CMNVECTOR) && !defined(CONFIG_ARMV7M_LAZYFPU) && defined(CONFIG_ARCH_FPU) #if !defined(CONFIG_ARMV7M_LAZYFPU) && defined(CONFIG_ARCH_FPU)
# define EXC_RETURN_PRIVTHR (EXC_RETURN_BASE | EXC_RETURN_THREAD_MODE) # define EXC_RETURN_PRIVTHR (EXC_RETURN_BASE | EXC_RETURN_THREAD_MODE)
#else #else
# define EXC_RETURN_PRIVTHR (EXC_RETURN_BASE | EXC_RETURN_STD_CONTEXT | \ # define EXC_RETURN_PRIVTHR (EXC_RETURN_BASE | EXC_RETURN_STD_CONTEXT | \
@ -104,7 +104,7 @@
* state from the process stack. Execution uses PSP after return. * state from the process stack. Execution uses PSP after return.
*/ */
#if defined(CONFIG_ARMV7M_CMNVECTOR) && !defined(CONFIG_ARMV7M_LAZYFPU) && defined(CONFIG_ARCH_FPU) #if !defined(CONFIG_ARMV7M_LAZYFPU) && defined(CONFIG_ARCH_FPU)
# define EXC_RETURN_UNPRIVTHR (EXC_RETURN_BASE | EXC_RETURN_THREAD_MODE | \ # define EXC_RETURN_UNPRIVTHR (EXC_RETURN_BASE | EXC_RETURN_THREAD_MODE | \
EXC_RETURN_PROCESS_STACK) EXC_RETURN_PROCESS_STACK)
#else #else

5
arch/arm/src/armv7-m/up_copyarmstate.c
View File

@ -45,8 +45,7 @@
#include "up_internal.h" #include "up_internal.h"
#if defined(CONFIG_ARCH_FPU) && \ #if defined(CONFIG_ARCH_FPU) && defined(CONFIG_ARMV7M_LAZYFPU)
(!defined(CONFIG_ARMV7M_CMNVECTOR) || defined(CONFIG_ARMV7M_LAZYFPU))
/**************************************************************************** /****************************************************************************
* Public Functions * Public Functions
@ -103,4 +102,4 @@ void up_copyarmstate(uint32_t *dest, uint32_t *src)
} }
} }
#endif /* CONFIG_ARCH_FPU && (!CONFIG_ARMV7M_CMNVECTOR || CONFIG_ARMV7M_LAZYFPU) */ #endif /* CONFIG_ARCH_FPU && CONFIG_ARMV7M_LAZYFPU */

10
arch/arm/src/armv7-m/up_initialstate.c
View File

@ -120,8 +120,7 @@ void up_initial_state(struct tcb_s *tcb)
#endif #endif
#endif /* CONFIG_PIC */ #endif /* CONFIG_PIC */
#if (defined(CONFIG_ARMV7M_CMNVECTOR) && !defined(CONFIG_ARMV7M_LAZYFPU)) || \ #if !defined(CONFIG_ARMV7M_LAZYFPU) || defined(CONFIG_BUILD_PROTECTED)
defined(CONFIG_BUILD_PROTECTED)
/* All tasks start via a stub function in kernel space. So all /* All tasks start via a stub function in kernel space. So all
* tasks must start in privileged thread mode. If CONFIG_BUILD_PROTECTED * tasks must start in privileged thread mode. If CONFIG_BUILD_PROTECTED
* is defined, then that stub function will switch to unprivileged * is defined, then that stub function will switch to unprivileged
@ -130,15 +129,14 @@ void up_initial_state(struct tcb_s *tcb)
xcp->regs[REG_EXC_RETURN] = EXC_RETURN_PRIVTHR; xcp->regs[REG_EXC_RETURN] = EXC_RETURN_PRIVTHR;
#endif /* (CONFIG_ARMV7M_CMNVECTOR && !CONFIG_ARMV7M_LAZYFPU) || CONFIG_BUILD_PROTECTED */ #endif /* !CONFIG_ARMV7M_LAZYFPU || CONFIG_BUILD_PROTECTED */
#if defined(CONFIG_ARMV7M_CMNVECTOR) && !defined(CONFIG_ARMV7M_LAZYFPU) && \ #if !defined(CONFIG_ARMV7M_LAZYFPU) && defined(CONFIG_ARCH_FPU)
defined(CONFIG_ARCH_FPU)
xcp->regs[REG_FPSCR] = 0; /* REVISIT: Initial FPSCR should be configurable */ xcp->regs[REG_FPSCR] = 0; /* REVISIT: Initial FPSCR should be configurable */
xcp->regs[REG_FPReserved] = 0; xcp->regs[REG_FPReserved] = 0;
#endif /* CONFIG_ARMV7M_CMNVECTOR && !CONFIG_ARMV7M_LAZYFPU && CONFIG_ARCH_FPU */ #endif /* !CONFIG_ARMV7M_LAZYFPU && CONFIG_ARCH_FPU */
/* Enable or disable interrupts, based on user configuration */ /* Enable or disable interrupts, based on user configuration */

6
arch/arm/src/armv7-m/up_svcall.c
View File

@ -179,8 +179,7 @@ int up_svcall(int irq, FAR void *context, FAR void *arg)
{ {
DEBUGASSERT(regs[REG_R1] != 0); DEBUGASSERT(regs[REG_R1] != 0);
memcpy((uint32_t *)regs[REG_R1], regs, XCPTCONTEXT_SIZE); memcpy((uint32_t *)regs[REG_R1], regs, XCPTCONTEXT_SIZE);
#if defined(CONFIG_ARCH_FPU) && \ #if defined(CONFIG_ARCH_FPU) && defined(CONFIG_ARMV7M_LAZYFPU)
(!defined(CONFIG_ARMV7M_CMNVECTOR) || defined(CONFIG_ARMV7M_LAZYFPU))
up_savefpu((uint32_t *)regs[REG_R1]); up_savefpu((uint32_t *)regs[REG_R1]);
#endif #endif
} }
@ -228,8 +227,7 @@ int up_svcall(int irq, FAR void *context, FAR void *arg)
{ {
DEBUGASSERT(regs[REG_R1] != 0 && regs[REG_R2] != 0); DEBUGASSERT(regs[REG_R1] != 0 && regs[REG_R2] != 0);
memcpy((uint32_t *)regs[REG_R1], regs, XCPTCONTEXT_SIZE); memcpy((uint32_t *)regs[REG_R1], regs, XCPTCONTEXT_SIZE);
#if defined(CONFIG_ARCH_FPU) && \ #if defined(CONFIG_ARCH_FPU) && defined(CONFIG_ARMV7M_LAZYFPU)
(!defined(CONFIG_ARMV7M_CMNVECTOR) || defined(CONFIG_ARMV7M_LAZYFPU))
up_savefpu((uint32_t *)regs[REG_R1]); up_savefpu((uint32_t *)regs[REG_R1]);
#endif #endif
CURRENT_REGS = (uint32_t *)regs[REG_R2]; CURRENT_REGS = (uint32_t *)regs[REG_R2];

4
arch/arm/src/common/up_internal.h
View File

@ -121,11 +121,9 @@
/* If the floating point unit is present and enabled, then save the /* If the floating point unit is present and enabled, then save the
* floating point registers as well as normal ARM registers. This only * floating point registers as well as normal ARM registers. This only
* applies if "lazy" floating point register save/restore is used * applies if "lazy" floating point register save/restore is used
* (i.e., not CONFIG_ARMV7M_CMNVECTOR=y with CONFIG_ARMV7M_LAZYFPU=n).
*/ */
# if defined(CONFIG_ARCH_FPU) && (!defined(CONFIG_ARMV7M_CMNVECTOR) || \ # if defined(CONFIG_ARCH_FPU) && defined(CONFIG_ARMV7M_LAZYFPU)
defined(CONFIG_ARMV7M_LAZYFPU))
# define up_savestate(regs) up_copyarmstate(regs, (uint32_t*)CURRENT_REGS) # define up_savestate(regs) up_copyarmstate(regs, (uint32_t*)CURRENT_REGS)
# else # else
# define up_savestate(regs) up_copyfullstate(regs, (uint32_t*)CURRENT_REGS) # define up_savestate(regs) up_copyfullstate(regs, (uint32_t*)CURRENT_REGS)

2
arch/arm/src/efm32/Make.defs
View File

@ -50,14 +50,12 @@ CMN_CSRCS += up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c
CMN_CSRCS += up_sigdeliver.c up_stackframe.c up_svcall.c up_systemreset.c CMN_CSRCS += up_sigdeliver.c up_stackframe.c up_svcall.c up_systemreset.c
CMN_CSRCS += up_udelay.c up_unblocktask.c up_usestack.c up_vfork.c CMN_CSRCS += up_udelay.c up_unblocktask.c up_usestack.c up_vfork.c
ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_ASRCS += up_lazyexception.S CMN_ASRCS += up_lazyexception.S
else else
CMN_ASRCS += up_exception.S CMN_ASRCS += up_exception.S
endif endif
CMN_CSRCS += up_vectors.c CMN_CSRCS += up_vectors.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y) ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c

4
arch/arm/src/imxrt/Make.defs
View File

@ -85,11 +85,7 @@ endif
ifeq ($(CONFIG_ARCH_FPU),y) ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S CMN_ASRCS += up_fpu.S
ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y)
CMN_CSRCS += up_copyarmstate.c CMN_CSRCS += up_copyarmstate.c
else ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_CSRCS += up_copyarmstate.c
endif
endif endif
# Required i.MX RT files # Required i.MX RT files

2
arch/arm/src/imxrt/imxrt_start.c
View File

@ -132,7 +132,7 @@ void __start(void) __attribute__ ((no_instrument_function));
****************************************************************************/ ****************************************************************************/
#ifdef CONFIG_ARCH_FPU #ifdef CONFIG_ARCH_FPU
#if defined(CONFIG_ARMV7M_CMNVECTOR) && !defined(CONFIG_ARMV7M_LAZYFPU) #ifndef CONFIG_ARMV7M_LAZYFPU
static inline void imxrt_fpuconfig(void) static inline void imxrt_fpuconfig(void)
{ {

2
arch/arm/src/kinetis/Make.defs
View File

@ -54,14 +54,12 @@ ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
CMN_CSRCS += up_stackcheck.c CMN_CSRCS += up_stackcheck.c
endif endif
ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_ASRCS += up_lazyexception.S CMN_ASRCS += up_lazyexception.S
else else
CMN_ASRCS += up_exception.S CMN_ASRCS += up_exception.S
endif endif
CMN_CSRCS += up_vectors.c CMN_CSRCS += up_vectors.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y) ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c

2
arch/arm/src/kinetis/kinetis_start.c
View File

@ -172,7 +172,7 @@ static inline void kinetis_fpuconfig(void)
setcontrol(regval); setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we * with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
* are going to turn on CONTROL.FPCA for all contexts. * are going to turn on CONTROL.FPCA for all contexts.
*/ */

2
arch/arm/src/lc823450/Make.defs
View File

@ -56,10 +56,8 @@ CMN_CSRCS += up_allocateheap.c
# CMN_CSRCS += up_dwt.c # CMN_CSRCS += up_dwt.c
CMN_CSRCS += up_stackframe.c CMN_CSRCS += up_stackframe.c
ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
CMN_ASRCS += up_exception.S CMN_ASRCS += up_exception.S
CMN_CSRCS += up_vectors.c CMN_CSRCS += up_vectors.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y) ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c

2
arch/arm/src/lpc17xx/Make.defs
View File

@ -57,14 +57,12 @@ ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
CMN_CSRCS += up_stackcheck.c CMN_CSRCS += up_stackcheck.c
endif endif
ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_ASRCS += up_lazyexception.S CMN_ASRCS += up_lazyexception.S
else else
CMN_ASRCS += up_exception.S CMN_ASRCS += up_exception.S
endif endif
CMN_CSRCS += up_vectors.c CMN_CSRCS += up_vectors.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y) ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c

6
arch/arm/src/lpc43xx/Make.defs
View File

@ -47,14 +47,12 @@ CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c up_stackframe.c
CMN_CSRCS += up_unblocktask.c up_usestack.c up_doirq.c up_hardfault.c CMN_CSRCS += up_unblocktask.c up_usestack.c up_doirq.c up_hardfault.c
CMN_CSRCS += up_svcall.c up_vfork.c CMN_CSRCS += up_svcall.c up_vfork.c
ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_ASRCS += up_lazyexception.S CMN_ASRCS += up_lazyexception.S
else else
CMN_ASRCS += up_exception.S CMN_ASRCS += up_exception.S
endif endif
CMN_CSRCS += up_vectors.c CMN_CSRCS += up_vectors.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y) ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c
@ -74,11 +72,7 @@ endif
ifeq ($(CONFIG_ARCH_FPU),y) ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S CMN_ASRCS += up_fpu.S
ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y)
CMN_CSRCS += up_copyarmstate.c CMN_CSRCS += up_copyarmstate.c
else ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_CSRCS += up_copyarmstate.c
endif
endif endif
CHIP_ASRCS = CHIP_ASRCS =

12
arch/arm/src/lpc43xx/lpc43_config.h
View File

@ -46,18 +46,6 @@
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ************************************************************************************/
/* Required configuration settings */
/* There are two version of the FPU support built into the most NuttX Cortex-M4 ports.
* The current LPC43xx port support only one of these options, the "Non-Lazy Floating
* Point Register Save". As a consequence, CONFIG_ARMV7M_CMNVECTOR must be defined
* in *all* LPC43xx configuration files.
*/
#ifndef CONFIG_ARMV7M_CMNVECTOR
# error "CONFIG_ARMV7M_CMNVECTOR must be defined for the LPC43xx"
#endif
/* Are any UARTs enabled? */ /* Are any UARTs enabled? */
#undef HAVE_UART #undef HAVE_UART

2
arch/arm/src/lpc43xx/lpc43_start.c
View File

@ -186,7 +186,7 @@ static inline void lpc43_enabuffering(void)
****************************************************************************/ ****************************************************************************/
#ifdef CONFIG_ARCH_FPU #ifdef CONFIG_ARCH_FPU
#if defined(CONFIG_ARMV7M_CMNVECTOR) && !defined(CONFIG_ARMV7M_LAZYFPU) #ifndef CONFIG_ARMV7M_LAZYFPU
static inline void lpc43_fpuconfig(void) static inline void lpc43_fpuconfig(void)
{ {

4
arch/arm/src/lpc54xx/Make.defs
View File

@ -72,11 +72,7 @@ endif
ifeq ($(CONFIG_ARCH_FPU),y) ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S CMN_ASRCS += up_fpu.S
ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y)
CMN_CSRCS += up_copyarmstate.c CMN_CSRCS += up_copyarmstate.c
else ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_CSRCS += up_copyarmstate.c
endif
endif endif
CHIP_ASRCS = CHIP_ASRCS =

2
arch/arm/src/lpc54xx/lpc54_start.c
View File

@ -120,7 +120,7 @@ static const struct pll_setup_s g_initial_pll_setup =
****************************************************************************/ ****************************************************************************/
#ifdef CONFIG_ARCH_FPU #ifdef CONFIG_ARCH_FPU
#if defined(CONFIG_ARMV7M_CMNVECTOR) && !defined(CONFIG_ARMV7M_LAZYFPU) #ifndef CONFIG_ARMV7M_LAZYFPU
static inline void lpc54_fpuconfig(void) static inline void lpc54_fpuconfig(void)
{ {
uint32_t regval; uint32_t regval;

4
arch/arm/src/nrf52/Make.defs
View File

@ -72,11 +72,7 @@ endif
ifeq ($(CONFIG_ARCH_FPU),y) ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S CMN_ASRCS += up_fpu.S
ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y)
CMN_CSRCS += up_copyarmstate.c CMN_CSRCS += up_copyarmstate.c
else ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_CSRCS += up_copyarmstate.c
endif
endif endif
CHIP_ASRCS = CHIP_ASRCS =

2
arch/arm/src/nrf52/nrf52_start.c
View File

@ -102,7 +102,7 @@
****************************************************************************/ ****************************************************************************/
#ifdef CONFIG_ARCH_FPU #ifdef CONFIG_ARCH_FPU
#if defined(CONFIG_ARMV7M_CMNVECTOR) && !defined(CONFIG_ARMV7M_LAZYFPU) #ifndef CONFIG_ARMV7M_LAZYFPU
static inline void nrf52_fpuconfig(void) static inline void nrf52_fpuconfig(void)
{ {
uint32_t regval; uint32_t regval;

2
arch/arm/src/sam34/Make.defs
View File

@ -62,14 +62,12 @@ endif
# Configuration-dependent common files # Configuration-dependent common files
ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_ASRCS += up_lazyexception.S CMN_ASRCS += up_lazyexception.S
else else
CMN_ASRCS += up_exception.S CMN_ASRCS += up_exception.S
endif endif
CMN_CSRCS += up_vectors.c CMN_CSRCS += up_vectors.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y) ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c

6
arch/arm/src/samv7/Make.defs
View File

@ -64,14 +64,12 @@ ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
CMN_CSRCS += up_stackcheck.c CMN_CSRCS += up_stackcheck.c
endif endif
ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_ASRCS += up_lazyexception.S CMN_ASRCS += up_lazyexception.S
else else
CMN_ASRCS += up_exception.S CMN_ASRCS += up_exception.S
endif endif
CMN_CSRCS += up_vectors.c CMN_CSRCS += up_vectors.c
endif
ifeq ($(CONFIG_ARMV7M_DCACHE),y) ifeq ($(CONFIG_ARMV7M_DCACHE),y)
CMN_CSRCS += arch_enable_dcache.c arch_disable_dcache.c CMN_CSRCS += arch_enable_dcache.c arch_disable_dcache.c
@ -84,11 +82,7 @@ endif
ifeq ($(CONFIG_ARCH_FPU),y) ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S CMN_ASRCS += up_fpu.S
ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y)
CMN_CSRCS += up_copyarmstate.c CMN_CSRCS += up_copyarmstate.c
else ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_CSRCS += up_copyarmstate.c
endif
endif endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y) ifeq ($(CONFIG_ARCH_RAMVECTORS),y)

2
arch/arm/src/samv7/sam_start.c
View File

@ -142,7 +142,7 @@ void __start(void) __attribute__ ((no_instrument_function));
****************************************************************************/ ****************************************************************************/
#ifdef CONFIG_ARCH_FPU #ifdef CONFIG_ARCH_FPU
#if defined(CONFIG_ARMV7M_CMNVECTOR) && !defined(CONFIG_ARMV7M_LAZYFPU) #ifndef CONFIG_ARMV7M_LAZYFPU
static inline void sam_fpuconfig(void) static inline void sam_fpuconfig(void)
{ {

16
arch/arm/src/stm32/Make.defs
View File

@ -1,7 +1,7 @@
############################################################################ ############################################################################
# arch/arm/src/stm32/Make.defs # arch/arm/src/stm32/Make.defs
# #
# Copyright (C) 2009, 2011-2016 Gregory Nutt. All rights reserved. # Copyright (C) 2009, 2011-2016, 2018 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org> # Author: Gregory Nutt <gnutt@nuttx.org>
# #
# Redistribution and use in source and binary forms, with or without # Redistribution and use in source and binary forms, with or without
@ -33,11 +33,7 @@
# #
############################################################################ ############################################################################
ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
HEAD_ASRC = HEAD_ASRC =
else
HEAD_ASRC = stm32_vectors.S
endif
CMN_UASRCS = CMN_UASRCS =
CMN_UCSRCS = CMN_UCSRCS =
@ -58,14 +54,12 @@ ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
CMN_CSRCS += up_stackcheck.c CMN_CSRCS += up_stackcheck.c
endif endif
ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_ASRCS += up_lazyexception.S CMN_ASRCS += up_lazyexception.S
else else
CMN_ASRCS += up_exception.S CMN_ASRCS += up_exception.S
endif endif
CMN_CSRCS += up_vectors.c CMN_CSRCS += up_vectors.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y) ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c
@ -85,11 +79,7 @@ endif
ifeq ($(CONFIG_ARCH_FPU),y) ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S CMN_ASRCS += up_fpu.S
ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y)
CMN_CSRCS += up_copyarmstate.c CMN_CSRCS += up_copyarmstate.c
else ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_CSRCS += up_copyarmstate.c
endif
endif endif
ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y) ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y)
@ -122,10 +112,6 @@ ifeq ($(CONFIG_STM32_FREERUN),y)
CHIP_CSRCS += stm32_freerun.c CHIP_CSRCS += stm32_freerun.c
endif endif
ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
CHIP_ASRCS += stm32_vectors.S
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y) ifeq ($(CONFIG_BUILD_PROTECTED),y)
CHIP_CSRCS += stm32_userspace.c stm32_mpuinit.c CHIP_CSRCS += stm32_userspace.c stm32_mpuinit.c
endif endif

37
arch/arm/src/stm32/chip.h
View File

@ -1,7 +1,7 @@
/************************************************************************************ /************************************************************************************
* arch/arm/src/stm32/chip.h * arch/arm/src/stm32/chip.h
* *
* Copyright (C) 2009, 2011-2014 Gregory Nutt. All rights reserved. * Copyright (C) 2009, 2011-2014, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -46,6 +46,10 @@
#include <arch/stm32/chip.h> #include <arch/stm32/chip.h>
/* Include the chip interrupt definition file */
#include <arch/stm32/irq.h>
/* Include the chip pin configuration file */ /* Include the chip pin configuration file */
/* STM32L EnergyLite Line ***********************************************************/ /* STM32L EnergyLite Line ***********************************************************/
@ -140,30 +144,6 @@
# error "No pinmap file for this STM32 chip" # error "No pinmap file for this STM32 chip"
#endif #endif
/* If the common ARMv7-M vector handling logic is used, then include the
* required vector definitions as well.
*/
#ifdef CONFIG_ARMV7M_CMNVECTOR
# if defined(CONFIG_STM32_STM32L15XX)
# include "chip/stm32l15xxx_vectors.h"
# elif defined(CONFIG_STM32_STM32F10XX)
# include "chip/stm32f10xxx_vectors.h"
# elif defined(CONFIG_STM32_STM32F20XX)
# include "chip/stm32f20xxx_vectors.h"
# elif defined(CONFIG_STM32_STM32F30XX)
# include "chip/stm32f30xxx_vectors.h"
# elif defined(CONFIG_STM32_STM32F33XX)
# include "chip/stm32f33xxx_vectors.h"
# elif defined(CONFIG_STM32_STM32F37XX)
# include "chip/stm32f37xxx_vectors.h"
# elif defined(CONFIG_STM32_STM32F4XXX)
# include "chip/stm32f40xxx_vectors.h"
# else
# error "No vector file for this STM32 family"
# endif
#endif
/* Include the chip memory map. */ /* Include the chip memory map. */
#include "chip/stm32_memorymap.h" #include "chip/stm32_memorymap.h"
@ -172,5 +152,12 @@
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ************************************************************************************/
/* Provide the required number of peripheral interrupt vector definitions as well.
* The definition STM32_IRQ_NEXTINT simply comes from the chip-specific IRQ header
* file included by arch/stm32/irq.h.
*/
#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINT
#endif /* __ARCH_ARM_SRC_STM32_CHIP_H */ #endif /* __ARCH_ARM_SRC_STM32_CHIP_H */

284
arch/arm/src/stm32/chip/stm32f10xxx_vectors.h
View File

@ -1,284 +0,0 @@
/************************************************************************************
* arch/arm/src/stm32/chip/stm32f10xxx_vectors.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Pre-processor definitions
************************************************************************************/
/* This file is included by stm32_vectors.S. It provides the macro VECTOR that
* supplies ach STM32F10xxx vector in terms of a (lower-case) ISR label and an
* (upper-case) IRQ number as defined in arch/arm/include/stm32/stm32f10xxx_irq.h.
* stm32_vectors.S will defined the VECTOR in different ways in order to generate
* the interrupt vectors and handlers in their final form.
*/
#if defined(CONFIG_STM32_VALUELINE)
/* If the common ARMv7-M vector handling is used, then all it needs is the following
* definition that provides the number of supported vectors.
*/
# ifdef CONFIG_ARMV7M_CMNVECTOR
/* Reserve 61 interrupt table entries for I/O interrupts. */
# define ARMV7M_PERIPHERAL_INTERRUPTS 61
#else
VECTOR(stm32_wwdg, STM32_IRQ_WWDG) /* Vector 16+0: Window Watchdog interrupt */
VECTOR(stm32_pvd, STM32_IRQ_PVD) /* Vector 16+1: PVD through EXTI Line detection interrupt */
VECTOR(stm32_tamper, STM32_IRQ_TAMPER) /* Vector 16+2: Tamper interrupt */
VECTOR(stm32_rtc, STM32_IRQ_RTC) /* Vector 16+3: RTC Wakeup through EXTI line interrupt */
VECTOR(stm32_flash, STM32_IRQ_FLASH) /* Vector 16+4: Flash global interrupt */
VECTOR(stm32_rcc, STM32_IRQ_RCC) /* Vector 16+5: RCC global interrupt */
VECTOR(stm32_exti0, STM32_IRQ_EXTI0) /* Vector 16+6: EXTI Line 0 interrupt */
VECTOR(stm32_exti1, STM32_IRQ_EXTI1) /* Vector 16+7: EXTI Line 1 interrupt */
VECTOR(stm32_exti2, STM32_IRQ_EXTI2) /* Vector 16+8: EXTI Line 2 interrupt */
VECTOR(stm32_exti3, STM32_IRQ_EXTI3) /* Vector 16+9: EXTI Line 3 interrupt */
VECTOR(stm32_exti4, STM32_IRQ_EXTI4) /* Vector 16+10: EXTI Line 4 interrupt */
VECTOR(stm32_dma1ch1, STM32_IRQ_DMA1CH1) /* Vector 16+11: DMA1 Channel 1 global interrupt */
VECTOR(stm32_dma1ch2, STM32_IRQ_DMA1CH2) /* Vector 16+12: DMA1 Channel 2 global interrupt */
VECTOR(stm32_dma1ch3, STM32_IRQ_DMA1CH3) /* Vector 16+13: DMA1 Channel 3 global interrupt */
VECTOR(stm32_dma1ch4, STM32_IRQ_DMA1CH4) /* Vector 16+14: DMA1 Channel 4 global interrupt */
VECTOR(stm32_dma1ch5, STM32_IRQ_DMA1CH5) /* Vector 16+15: DMA1 Channel 5 global interrupt */
VECTOR(stm32_dma1ch6, STM32_IRQ_DMA1CH6) /* Vector 16+16: DMA1 Channel 6 global interrupt */
VECTOR(stm32_dma1ch7, STM32_IRQ_DMA1CH7) /* Vector 16+17: DMA1 Channel 7 global interrupt */
VECTOR(stm32_adc1, STM32_IRQ_ADC1) /* Vector 16+18: ADC1 global interrupt */
UNUSED(STM32_IRQ_RESERVED0) /* Vector 16+19: Reserved 0 */
UNUSED(STM32_IRQ_RESERVED1) /* Vector 16+20: Reserved 1 */
UNUSED(STM32_IRQ_RESERVED2) /* Vector 16+21: Reserved 2 */
UNUSED(STM32_IRQ_RESERVED3) /* Vector 16+22: Reserved 3 */
VECTOR(stm32_exti95, STM32_IRQ_EXTI95) /* Vector 16+23: EXTI Line[9:5] interrupts */
VECTOR(stm32_tim1brk, STM32_IRQ_TIM1BRK) /* Vector 16+24: TIM1 Break interrupt; TIM15 global interrupt */
VECTOR(stm32_tim1up, STM32_IRQ_TIM1UP) /* Vector 16+25: TIM1 Update interrupt; TIM16 global interrupt */
VECTOR(stm32_tim1trgcom, STM32_IRQ_TIM1TRGCOM) /* Vector 16+26: TIM1 Trigger and Commutation interrupts; TIM17 global interrupt */
VECTOR(stm32_tim1cc, STM32_IRQ_TIM1CC) /* Vector 16+27: TIM1 Capture Compare interrupt */
VECTOR(stm32_tim2, STM32_IRQ_TIM2) /* Vector 16+28: TIM2 global interrupt */
VECTOR(stm32_tim3, STM32_IRQ_TIM3) /* Vector 16+29: TIM3 global interrupt */
VECTOR(stm32_tim4, STM32_IRQ_TIM4) /* Vector 16+30: TIM4 global interrupt */
VECTOR(stm32_i2c1ev, STM32_IRQ_I2C1EV) /* Vector 16+31: I2C1 event interrupt */
VECTOR(stm32_i2c1er, STM32_IRQ_I2C1ER) /* Vector 16+32: I2C1 error interrupt */
VECTOR(stm32_i2c2ev, STM32_IRQ_I2C2EV) /* Vector 16+33: I2C2 event interrupt */
VECTOR(stm32_i2c2er, STM32_IRQ_I2C2ER) /* Vector 16+34: I2C2 error interrupt */
VECTOR(stm32_spi1, STM32_IRQ_SPI1) /* Vector 16+35: SPI1 global interrupt */
VECTOR(stm32_spi2, STM32_IRQ_SPI2) /* Vector 16+36: SPI2 global interrupt */
VECTOR(stm32_usart1, STM32_IRQ_USART1) /* Vector 16+37: USART1 global interrupt */
VECTOR(stm32_usart2, STM32_IRQ_USART2) /* Vector 16+38: USART2 global interrupt */
VECTOR(stm32_usart3, STM32_IRQ_USART3) /* Vector 16+39: USART3 global interrupt */
VECTOR(stm32_exti1510, STM32_IRQ_EXTI1510) /* Vector 16+40: EXTI Line[15:10] interrupts */
VECTOR(stm32_rtcalr, STM32_IRQ_RTCALR) /* Vector 16+41: RTC alarms (A and B) through EXTI line interrupt */
VECTOR(stm32_cec, STM32_IRQ_CEC) /* Vector 16+42: CEC global interrupt */
VECTOR(stm32_tim12, STM32_IRQ_TIM12) /* Vector 16+43: TIM12 global interrupt */
VECTOR(stm32_tim13, STM32_IRQ_TIM13) /* Vector 16+44: TIM13 global interrupt */
VECTOR(stm32_tim14, STM32_IRQ_TIM14) /* Vector 16+45: TIM14 global interrupt */
UNUSED(STM32_IRQ_RESERVED4) /* Vector 16+46: Reserved 4 */
UNUSED(STM32_IRQ_RESERVED5) /* Vector 16+47: Reserved 5 */
VECTOR(stm32_fsmc, STM32_IRQ_FSMC) /* Vector 16+48: FSMC global interrupt */
UNUSED(STM32_IRQ_RESERVED6) /* Vector 16+49: Reserved 6 */
VECTOR(stm32_tim5, STM32_IRQ_TIM5) /* Vector 16+50: TIM5 global interrupt */
VECTOR(stm32_spi3, STM32_IRQ_SPI3) /* Vector 16+51: SPI3 global interrupt */
VECTOR(stm32_uart4, STM32_IRQ_UART4) /* Vector 16+52: USART2 global interrupt */
VECTOR(stm32_uart5, STM32_IRQ_UART5) /* Vector 16+53: UART5 global interrupt */
VECTOR(stm32_tim6, STM32_IRQ_TIM6) /* Vector 16+54: TIM6 global interrupt */
VECTOR(stm32_tim7, STM32_IRQ_TIM7) /* Vector 16+55: TIM7 global interrupt */
VECTOR(stm32_dma2ch1, STM32_IRQ_DMA2CH1) /* Vector 16+56: DMA2 Channel 1 global interrupt */
VECTOR(stm32_dma2ch2, STM32_IRQ_DMA2CH2) /* Vector 16+57: DMA2 Channel 2 global interrupt */
VECTOR(stm32_dma2ch3, STM32_IRQ_DMA2CH3) /* Vector 16+58: DMA2 Channel 3 global interrupt */
VECTOR(stm32_dma2ch45, STM32_IRQ_DMA2CH45) /* Vector 16+59: DMA2 Channel 4 and 5 global interrupt */
VECTOR(stm32_dma2ch5, STM32_IRQ_DMA2CH5) /* Vector 16+60: DMA2 Channel 5 global interrupt */
# endif /* CONFIG_ARMV7M_CMNVECTOR */
#elif defined(CONFIG_STM32_CONNECTIVITYLINE)
/* If the common ARMv7-M vector handling is used, then all it needs is the following
* definition that provides the number of supported vectors.
*/
#ifdef CONFIG_ARMV7M_CMNVECTOR
/* Reserve 68 interrupt table entries for I/O interrupts. */
# define ARMV7M_PERIPHERAL_INTERRUPTS 68
#else
VECTOR(stm32_wwdg, STM32_IRQ_WWDG) /* Vector 16+0: Window Watchdog interrupt */
VECTOR(stm32_pvd, STM32_IRQ_PVD) /* Vector 16+1: PVD through EXTI Line detection interrupt */
VECTOR(stm32_tamper, STM32_IRQ_TAMPER) /* Vector 16+2: Tamper interrupt */
VECTOR(stm32_rtc, STM32_IRQ_RTC) /* Vector 16+3: RTC global interrupt */
VECTOR(stm32_flash, STM32_IRQ_FLASH) /* Vector 16+4: Flash global interrupt */
VECTOR(stm32_rcc, STM32_IRQ_RCC) /* Vector 16+5: RCC global interrupt */
VECTOR(stm32_exti0, STM32_IRQ_EXTI0) /* Vector 16+6: EXTI Line 0 interrupt */
VECTOR(stm32_exti1, STM32_IRQ_EXTI1) /* Vector 16+7: EXTI Line 1 interrupt */
VECTOR(stm32_exti2, STM32_IRQ_EXTI2) /* Vector 16+8: EXTI Line 2 interrupt */
VECTOR(stm32_exti3, STM32_IRQ_EXTI3) /* Vector 16+9: EXTI Line 3 interrupt */
VECTOR(stm32_exti4, STM32_IRQ_EXTI4) /* Vector 16+10: EXTI Line 4 interrupt */
VECTOR(stm32_dma1ch1, STM32_IRQ_DMA1CH1) /* Vector 16+11: DMA1 Channel 1 global interrupt */
VECTOR(stm32_dma1ch2, STM32_IRQ_DMA1CH2) /* Vector 16+12: DMA1 Channel 2 global interrupt */
VECTOR(stm32_dma1ch3, STM32_IRQ_DMA1CH3) /* Vector 16+13: DMA1 Channel 3 global interrupt */
VECTOR(stm32_dma1ch4, STM32_IRQ_DMA1CH4) /* Vector 16+14: DMA1 Channel 4 global interrupt */
VECTOR(stm32_dma1ch5, STM32_IRQ_DMA1CH5) /* Vector 16+15: DMA1 Channel 5 global interrupt */
VECTOR(stm32_dma1ch6, STM32_IRQ_DMA1CH6) /* Vector 16+16: DMA1 Channel 6 global interrupt */
VECTOR(stm32_dma1ch7, STM32_IRQ_DMA1CH7) /* Vector 16+17: DMA1 Channel 7 global interrupt */
VECTOR(stm32_adc12, STM32_IRQ_ADC12) /* Vector 16+18: ADC1 and ADC2 global interrupt */
VECTOR(stm32_can1tx, STM32_IRQ_CAN1TX) /* Vector 16+19: CAN1 TX interrupts */
VECTOR(stm32_can1rx0, STM32_IRQ_CAN1RX0) /* Vector 16+20: CAN1 RX0 interrupts */
VECTOR(stm32_can1rx, STM32_IRQ_CAN1RX1) /* Vector 16+21: CAN1 RX1 interrupt */
VECTOR(stm32_can1sce, STM32_IRQ_CAN1SCE) /* Vector 16+22: CAN1 SCE interrupt */
VECTOR(stm32_exti95, STM32_IRQ_EXTI95) /* Vector 16+23: EXTI Line[9:5] interrupts */
VECTOR(stm32_tim1brk, STM32_IRQ_TIM1BRK) /* Vector 16+24: TIM1 Break interrupt */
VECTOR(stm32_tim1up, STM32_IRQ_TIM1UP) /* Vector 16+25: TIM1 Update interrupt */
VECTOR(stm32_tim1trgcom, STM32_IRQ_TIM1TRGCOM) /* Vector 16+26: TIM1 Trigger and Commutation interrupts */
VECTOR(stm32_tim1cc, STM32_IRQ_TIM1CC) /* Vector 16+27: TIM1 Capture Compare interrupt */
VECTOR(stm32_tim2, STM32_IRQ_TIM2) /* Vector 16+28: TIM2 global interrupt */
VECTOR(stm32_tim3, STM32_IRQ_TIM3) /* Vector 16+29: TIM3 global interrupt */
VECTOR(stm32_tim4, STM32_IRQ_TIM4) /* Vector 16+30: TIM4 global interrupt */
VECTOR(stm32_i2c1ev, STM32_IRQ_I2C1EV) /* Vector 16+31: I2C1 event interrupt */
VECTOR(stm32_i2c1er, STM32_IRQ_I2C1ER) /* Vector 16+32: I2C1 error interrupt */
VECTOR(stm32_i2c2ev, STM32_IRQ_I2C2EV) /* Vector 16+33: I2C2 event interrupt */
VECTOR(stm32_i2c2er, STM32_IRQ_I2C2ER) /* Vector 16+34: I2C2 error interrupt */
VECTOR(stm32_spi1, STM32_IRQ_SPI1) /* Vector 16+35: SPI1 global interrupt */
VECTOR(stm32_spi2, STM32_IRQ_SPI2) /* Vector 16+36: SPI2 global interrupt */
VECTOR(stm32_usart1, STM32_IRQ_USART1) /* Vector 16+37: USART1 global interrupt */
VECTOR(stm32_usart2, STM32_IRQ_USART2) /* Vector 16+38: USART2 global interrupt */
VECTOR(stm32_usart3, STM32_IRQ_USART3) /* Vector 16+39: USART3 global interrupt */
VECTOR(stm32_exti1510, STM32_IRQ_EXTI1510) /* Vector 16+40: EXTI Line[15:10] interrupts */
VECTOR(stm32_rtcalr, STM32_IRQ_RTCALRM) /* Vector 16+41: RTC alarm through EXTI line interrupt */
VECTOR(stm32_otgfswkup, STM32_IRQ_OTGFSWKUP) /* Vector 16+42: USB On-The-Go FS Wakeup through EXTI line interrupt */
UNUSED(STM32_IRQ_RESERVED0) /* Vector 16+43: Reserved 0 */
UNUSED(STM32_IRQ_RESERVED1) /* Vector 16+44: Reserved 1 */
UNUSED(STM32_IRQ_RESERVED2) /* Vector 16+55: Reserved 2 */
UNUSED(STM32_IRQ_RESERVED3) /* Vector 16+46: Reserved 3 */
UNUSED(STM32_IRQ_RESERVED4) /* Vector 16+47: Reserved 4 */
UNUSED(STM32_IRQ_RESERVED5) /* Vector 16+48: Reserved 5 */
UNUSED(STM32_IRQ_RESERVED6) /* Vector 16+49: Reserved 6 */
VECTOR(stm32_tim5, STM32_IRQ_TIM5) /* Vector 16+50: TIM5 global interrupt */
VECTOR(stm32_spi3, STM32_IRQ_SPI3 ) /* Vector 16+51: SPI3 global interrupt */
VECTOR(stm32_uart4 , STM32_IRQ_UART4) /* Vector 16+52: UART4 global interrupt */
VECTOR(stm32_uart5, STM32_IRQ_UART5) /* Vector 16+53: UART5 global interrupt */
VECTOR(stm32_tim6, STM32_IRQ_TIM6) /* Vector 16+54: TIM6 global interrupt */
VECTOR(stm32_tim7, STM32_IRQ_TIM7) /* Vector 16+55: TIM7 global interrupt */
VECTOR(stm32_dma2ch1, STM32_IRQ_DMA2CH1) /* Vector 16+56: DMA2 Channel 1 global interrupt */
VECTOR(stm32_dma2ch2, STM32_IRQ_DMA2CH2) /* Vector 16+57: DMA2 Channel 2 global interrupt */
VECTOR(stm32_dma2ch3, STM32_IRQ_DMA2CH3) /* Vector 16+58: DMA2 Channel 3 global interrupt */
VECTOR(stm32_dma2ch4, STM32_IRQ_DMA2CH4) /* Vector 16+59: DMA2 Channel 4 global interrupt */
VECTOR(stm32_dma2ch5, STM32_IRQ_DMA2CH5) /* Vector 16+60: DMA2 Channel 5 global interrupt */
VECTOR(stm32_eth, STM32_IRQ_ETH) /* Vector 16+61: Ethernet global interrupt */
VECTOR(stm32_ethwkup, STM32_IRQ_ETHWKUP) /* Vector 16+62: Ethernet Wakeup through EXTI line interrupt */
VECTOR(stm32_can2tx, STM32_IRQ_CAN2TX) /* Vector 16+63: CAN2 TX interrupts */
VECTOR(stm32_can2rx0, STM32_IRQ_CAN2RX0) /* Vector 16+64: CAN2 RX0 interrupts */
VECTOR(stm32_can2rx1, STM32_IRQ_CAN2RX1) /* Vector 16+65: CAN2 RX1 interrupt */
VECTOR(stm32_can2sce, STM32_IRQ_CAN2SCE) /* Vector 16+66: CAN2 SCE interrupt */
VECTOR(stm32_otgfs, STM32_IRQ_OTGFS) /* Vector 16+67: USB On The Go FS global interrupt */
#endif /* CONFIG_ARMV7M_CMNVECTOR */
#else /* CONFIG_STM32_CONNECTIVITYLINE */
/* If the common ARMv7-M vector handling is used, then all it needs is the following
* definition that provides the number of supported vectors.
*/
#ifdef CONFIG_ARMV7M_CMNVECTOR
/* Reserve 60 interrupt table entries for I/O interrupts. */
# define ARMV7M_PERIPHERAL_INTERRUPTS 60
#else
VECTOR(stm32_wwdg, STM32_IRQ_WWDG) /* Vector 16+0: Window Watchdog interrupt */
VECTOR(stm32_pvd, STM32_IRQ_PVD) /* Vector 16+1: PVD through EXTI Line detection interrupt */
VECTOR(stm32_tamper, STM32_IRQ_TAMPER) /* Vector 16+2: Tamper interrupt */
VECTOR(stm32_rtc, STM32_IRQ_RTC) /* Vector 16+3: RTC global interrupt */
VECTOR(stm32_flash, STM32_IRQ_FLASH) /* Vector 16+4: Flash global interrupt */
VECTOR(stm32_rcc, STM32_IRQ_RCC) /* Vector 16+5: RCC global interrupt */
VECTOR(stm32_exti0, STM32_IRQ_EXTI0) /* Vector 16+6: EXTI Line 0 interrupt */
VECTOR(stm32_exti1, STM32_IRQ_EXTI1) /* Vector 16+7: EXTI Line 1 interrupt */
VECTOR(stm32_exti2, STM32_IRQ_EXTI2) /* Vector 16+8: EXTI Line 2 interrupt */
VECTOR(stm32_exti3, STM32_IRQ_EXTI3) /* Vector 16+9: EXTI Line 3 interrupt */
VECTOR(stm32_exti4, STM32_IRQ_EXTI4) /* Vector 16+10: EXTI Line 4 interrupt */
VECTOR(stm32_dma1ch1, STM32_IRQ_DMA1CH1) /* Vector 16+11: DMA1 Channel 1 global interrupt */
VECTOR(stm32_dma1ch2, STM32_IRQ_DMA1CH2) /* Vector 16+12: DMA1 Channel 2 global interrupt */
VECTOR(stm32_dma1ch3, STM32_IRQ_DMA1CH3) /* Vector 16+13: DMA1 Channel 3 global interrupt */
VECTOR(stm32_dma1ch4, STM32_IRQ_DMA1CH4) /* Vector 16+14: DMA1 Channel 4 global interrupt */
VECTOR(stm32_dma1ch5, STM32_IRQ_DMA1CH5) /* Vector 16+15: DMA1 Channel 5 global interrupt */
VECTOR(stm32_dma1ch6, STM32_IRQ_DMA1CH6) /* Vector 16+16: DMA1 Channel 6 global interrupt */
VECTOR(stm32_dma1ch7, STM32_IRQ_DMA1CH7) /* Vector 16+17: DMA1 Channel 7 global interrupt */
VECTOR(stm32_adc12, STM32_IRQ_ADC12) /* Vector 16+18: ADC1 and ADC2 global interrupt */
VECTOR(stm32_usbhpcantx, STM32_IRQ_USBHPCANTX) /* Vector 16+19: USB High Priority or CAN TX interrupts*/
VECTOR(stm32_usblpcanrx0, STM32_IRQ_USBLPCANRX0) /* Vector 16+20: USB Low Priority or CAN RX0 interrupts*/
VECTOR(stm32_can1rx1, STM32_IRQ_CAN1RX1) /* Vector 16+21: CAN1 RX1 interrupt */
VECTOR(stm32_can1sce, STM32_IRQ_CAN1SCE) /* Vector 16+22: CAN1 SCE interrupt */
VECTOR(stm32_exti95, STM32_IRQ_EXTI95) /* Vector 16+23: EXTI Line[9:5] interrupts */
VECTOR(stm32_tim1brk, STM32_IRQ_TIM1BRK) /* Vector 16+24: TIM1 Break interrupt */
VECTOR(stm32_tim1up, STM32_IRQ_TIM1UP) /* Vector 16+25: TIM1 Update interrupt */
VECTOR(stm32_tim1rtgcom, STM32_IRQ_TIM1TRGCOM) /* Vector 16+26: TIM1 Trigger and Commutation interrupts */
VECTOR(stm32_tim1cc, STM32_IRQ_TIM1CC) /* Vector 16+27: TIM1 Capture Compare interrupt */
VECTOR(stm32_tim2, STM32_IRQ_TIM2) /* Vector 16+28: TIM2 global interrupt */
VECTOR(stm32_tim3, STM32_IRQ_TIM3) /* Vector 16+29: TIM3 global interrupt */
VECTOR(stm32_tim4, STM32_IRQ_TIM4) /* Vector 16+30: TIM4 global interrupt */
VECTOR(stm32_i2c1ev, STM32_IRQ_I2C1EV) /* Vector 16+31: I2C1 event interrupt */
VECTOR(stm32_i2c1er, STM32_IRQ_I2C1ER) /* Vector 16+32: I2C1 error interrupt */
VECTOR(stm32_i2c2ev, STM32_IRQ_I2C2EV) /* Vector 16+33: I2C2 event interrupt */
VECTOR(stm32_i2c2er, STM32_IRQ_I2C2ER) /* Vector 16+34: I2C2 error interrupt */
VECTOR(stm32_spi1, STM32_IRQ_SPI1) /* Vector 16+35: SPI1 global interrupt */
VECTOR(stm32_spi2, STM32_IRQ_SPI2) /* Vector 16+36: SPI2 global interrupt */
VECTOR(stm32_usart1, STM32_IRQ_USART1) /* Vector 16+37: USART1 global interrupt */
VECTOR(stm32_usart2, STM32_IRQ_USART2) /* Vector 16+38: USART2 global interrupt */
VECTOR(stm32_usart3, STM32_IRQ_USART3) /* Vector 16+39: USART3 global interrupt */
VECTOR(stm32_exti1510, STM32_IRQ_EXTI1510) /* Vector 16+40: EXTI Line[15:10] interrupts */
VECTOR(stm32_rtcalr, STM32_IRQ_RTCALRM) /* Vector 16+41: RTC alarm through EXTI line interrupt */
VECTOR(stm32_usbwkup, STM32_IRQ_USBWKUP) /* Vector 16+42: USB wakeup from suspend through EXTI line interrupt*/
VECTOR(stm32_tim8brk, STM32_IRQ_TIM8BRK) /* Vector 16+43: TIM8 Break interrupt */
VECTOR(stm32_tim8up, STM32_IRQ_TIM8UP) /* Vector 16+44: TIM8 Update interrupt */
VECTOR(stm32_tim8trgcom, STM32_IRQ_TIM8TRGCOM) /* Vector 16+45: TIM8 Trigger and Commutation interrupts */
VECTOR(stm32_tim8cc, STM32_IRQ_TIM8CC) /* Vector 16+46: TIM8 Capture Compare interrupt */
VECTOR(stm32_adc3, STM32_IRQ_ADC3) /* Vector 16+47: ADC3 global interrupt */
VECTOR(stm32_fsmc, STM32_IRQ_FSMC) /* Vector 16+48: FSMC global interrupt */
VECTOR(stm32_sdio, STM32_IRQ_SDIO) /* Vector 16+49: SDIO global interrupt */
VECTOR(stm32_tim5, STM32_IRQ_TIM5) /* Vector 16+50: TIM5 global interrupt */
VECTOR(stm32_spi3, STM32_IRQ_SPI3) /* Vector 16+51: SPI3 global interrupt */
VECTOR(stm32_uart4, STM32_IRQ_UART4) /* Vector 16+52: UART4 global interrupt */
VECTOR(stm32_uart5, STM32_IRQ_UART5) /* Vector 16+53: UART5 global interrupt */
VECTOR(stm32_tim6, STM32_IRQ_TIM6) /* Vector 16+54: TIM6 global interrupt */
VECTOR(stm32_tim7, STM32_IRQ_TIM7) /* Vector 16+55: TIM7 global interrupt */
VECTOR(stm32_dma2ch1, STM32_IRQ_DMA2CH1) /* Vector 16+56: DMA2 Channel 1 global interrupt */
VECTOR(stm32_dma2ch2, STM32_IRQ_DMA2CH2) /* Vector 16+57: DMA2 Channel 2 global interrupt */
VECTOR(stm32_dma2ch3, STM32_IRQ_DMA2CH3) /* Vector 16+58: DMA2 Channel 3 global interrupt */
VECTOR(stm32_dma2ch45, STM32_IRQ_DMA2CH45) /* Vector 16+59: DMA2 Channel 4&5 global interrupt */
#endif /* CONFIG_ARMV7M_CMNVECTOR */
#endif /* CONFIG_STM32_CONNECTIVITYLINE */

141
arch/arm/src/stm32/chip/stm32f20xxx_vectors.h
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@ -1,141 +0,0 @@
/************************************************************************************
* arch/arm/src/stm32/chip/stm32f20xxx_vectors.h
*
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Pre-processor definitions
************************************************************************************/
/* This file is included by stm32_vectors.S. It provides the macro VECTOR that
* supplies ach STM32F20xxx vector in terms of a (lower-case) ISR label and an
* (upper-case) IRQ number as defined in arch/arm/include/stm32/stm32f20xxx_irq.h.
* stm32_vectors.S will defined the VECTOR in different ways in order to generate
* the interrupt vectors and handlers in their final form.
*/
/* If the common ARMv7-M vector handling is used, then all it needs is the following
* definition that provides the number of supported vectors.
*/
#ifdef CONFIG_ARMV7M_CMNVECTOR
/* Reserve 82 interrupt table entries for I/O interrupts. */
# define ARMV7M_PERIPHERAL_INTERRUPTS 82
#else
VECTOR(stm32_wwdg, STM32_IRQ_WWDG) /* Vector 16+0: Window Watchdog interrupt */
VECTOR(stm32_pvd, STM32_IRQ_PVD) /* Vector 16+1: PVD through EXTI Line detection interrupt */
VECTOR(stm32_tamper, STM32_IRQ_TAMPER) /* Vector 16+2: Tamper and time stamp interrupts */
VECTOR(stm32_rtc_wkup, STM32_IRQ_RTC_WKUP) /* Vector 16+3: RTC global interrupt */
VECTOR(stm32_flash, STM32_IRQ_FLASH) /* Vector 16+4: Flash global interrupt */
VECTOR(stm32_rcc, STM32_IRQ_RCC) /* Vector 16+5: RCC global interrupt */
VECTOR(stm32_exti0, STM32_IRQ_EXTI0) /* Vector 16+6: EXTI Line 0 interrupt */
VECTOR(stm32_exti1, STM32_IRQ_EXTI1) /* Vector 16+7: EXTI Line 1 interrupt */
VECTOR(stm32_exti2, STM32_IRQ_EXTI2) /* Vector 16+8: EXTI Line 2 interrupt */
VECTOR(stm32_exti3, STM32_IRQ_EXTI3) /* Vector 16+9: EXTI Line 3 interrupt */
VECTOR(stm32_exti4, STM32_IRQ_EXTI4) /* Vector 16+10: EXTI Line 4 interrupt */
VECTOR(stm32_dma1s0, STM32_IRQ_DMA1S0) /* Vector 16+11: DMA1 Stream 0 global interrupt */
VECTOR(stm32_dma1s1, STM32_IRQ_DMA1S1) /* Vector 16+12: DMA1 Stream 1 global interrupt */
VECTOR(stm32_dma1s2, STM32_IRQ_DMA1S2) /* Vector 16+13: DMA1 Stream 2 global interrupt */
VECTOR(stm32_dma1s3, STM32_IRQ_DMA1S3) /* Vector 16+14: DMA1 Stream 3 global interrupt */
VECTOR(stm32_dma1s4, STM32_IRQ_DMA1S4) /* Vector 16+15: DMA1 Stream 4 global interrupt */
VECTOR(stm32_dma1s5, STM32_IRQ_DMA1S5) /* Vector 16+16: DMA1 Stream 5 global interrupt */
VECTOR(stm32_dma1s6, STM32_IRQ_DMA1S6) /* Vector 16+17: DMA1 Stream 6 global interrupt */
VECTOR(stm32_adc, STM32_IRQ_ADC) /* Vector 16+18: ADC1, ADC2, and ADC3 global interrupt */
VECTOR(stm32_can1tx, STM32_IRQ_CAN1TX) /* Vector 16+19: CAN1 TX interrupts */
VECTOR(stm32_can1rx0, STM32_IRQ_CAN1RX0) /* Vector 16+20: CAN1 RX0 interrupts */
VECTOR(stm32_can1rx1, STM32_IRQ_CAN1RX1) /* Vector 16+21: CAN1 RX1 interrupt */
VECTOR(stm32_can1sce, STM32_IRQ_CAN1SCE) /* Vector 16+22: CAN1 SCE interrupt */
VECTOR(stm32_exti95, STM32_IRQ_EXTI95) /* Vector 16+23: EXTI Line[9:5] interrupts */
VECTOR(stm32_tim1brk, STM32_IRQ_TIM1BRK) /* Vector 16+24: TIM1 Break interrupt/TIM9 global interrupt */
VECTOR(stm32_tim1up, STM32_IRQ_TIM1UP) /* Vector 16+25: TIM1 Update interrupt/TIM10 global interrupt */
VECTOR(stm32_tim1trgcom, STM32_IRQ_TIM1TRGCOM) /* Vector 16+26: TIM1 Trigger and Commutation interrupts/TIM11 global interrupt */
VECTOR(stm32_tim1cc, STM32_IRQ_TIM1CC) /* Vector 16+27: TIM1 Capture Compare interrupt */
VECTOR(stm32_tim2, STM32_IRQ_TIM2) /* Vector 16+28: TIM2 global interrupt */
VECTOR(stm32_tim3, STM32_IRQ_TIM3) /* Vector 16+29: TIM3 global interrupt */
VECTOR(stm32_tim4, STM32_IRQ_TIM4) /* Vector 16+30: TIM4 global interrupt */
VECTOR(stm32_i2c1ev, STM32_IRQ_I2C1EV) /* Vector 16+31: I2C1 event interrupt */
VECTOR(stm32_i2c1er, STM32_IRQ_I2C1ER) /* Vector 16+32: I2C1 error interrupt */
VECTOR(stm32_i2c2ev, STM32_IRQ_I2C2EV) /* Vector 16+33: I2C2 event interrupt */
VECTOR(stm32_i2c2er, STM32_IRQ_I2C2ER) /* Vector 16+34: I2C2 error interrupt */
VECTOR(stm32_spi1, STM32_IRQ_SPI1) /* Vector 16+35: SPI1 global interrupt */
VECTOR(stm32_spi2, STM32_IRQ_SPI2) /* Vector 16+36: SPI2 global interrupt */
VECTOR(stm32_usart1, STM32_IRQ_USART1) /* Vector 16+37: USART1 global interrupt */
VECTOR(stm32_usart2, STM32_IRQ_USART2) /* Vector 16+38: USART2 global interrupt */
VECTOR(stm32_usart3, STM32_IRQ_USART3) /* Vector 16+39: USART3 global interrupt */
VECTOR(stm32_exti1510, STM32_IRQ_EXTI1510) /* Vector 16+40: EXTI Line[15:10] interrupts */
VECTOR(stm32_rtcalrm, STM32_IRQ_RTCALRM) /* Vector 16+41: RTC alarm through EXTI line interrupt */
VECTOR(stm32_otgfswkup, STM32_IRQ_OTGFSWKUP) /* Vector 16+42: USB On-The-Go FS Wakeup through EXTI line interrupt */
VECTOR(stm32_tim8brk, STM32_IRQ_TIM8BRK) /* Vector 16+43: TIM8 Break interrupt/TIM12 global interrupt */
VECTOR(stm32_tim8up, STM32_IRQ_TIM8UP) /* Vector 16+44: TIM8 Update interrup/TIM13 global interrupt */
VECTOR(stm32_tim8trgcom, STM32_IRQ_TIM8TRGCOM) /* Vector 16+45: TIM8 Trigger and Commutation interrupts/TIM14 global interrupt */
VECTOR(stm32_tim8cc, STM32_IRQ_TIM8CC) /* Vector 16+46: TIM8 Capture Compare interrupt */
VECTOR(stm32_dma1s7, STM32_IRQ_DMA1S7) /* Vector 16+47: DMA1 Stream 7 global interrupt */
VECTOR(stm32_fsmc, STM32_IRQ_FSMC) /* Vector 16+48: FSMC global interrupt */
VECTOR(stm32_sdio, STM32_IRQ_SDIO) /* Vector 16+49: SDIO global interrupt */
VECTOR(stm32_tim5, STM32_IRQ_TIM5) /* Vector 16+50: TIM5 global interrupt */
VECTOR(stm32_spi3, STM32_IRQ_SPI3) /* Vector 16+51: SPI3 global interrupt */
VECTOR(stm32_uart4, STM32_IRQ_UART4) /* Vector 16+52: UART4 global interrupt */
VECTOR(stm32_uart5, STM32_IRQ_UART5) /* Vector 16+53: UART5 global interrupt */
VECTOR(stm32_tim6, STM32_IRQ_TIM6) /* Vector 16+54: TIM6 global interrupt/DAC1 and DAC2 underrun error interrupts */
VECTOR(stm32_tim7, STM32_IRQ_TIM7) /* Vector 16+55: TIM7 global interrupt */
VECTOR(stm32_dma2s0, STM32_IRQ_DMA2S0) /* Vector 16+56: DMA2 Stream 0 global interrupt */
VECTOR(stm32_dma2s1, STM32_IRQ_DMA2S1) /* Vector 16+57: DMA2 Stream 1 global interrupt */
VECTOR(stm32_dma2s2, STM32_IRQ_DMA2S2) /* Vector 16+58: DMA2 Stream 2 global interrupt */
VECTOR(stm32_dma2s3, STM32_IRQ_DMA2S3) /* Vector 16+59: DMA2 Stream 3 global interrupt */
VECTOR(stm32_dma2s4, STM32_IRQ_DMA2S4) /* Vector 16+60: DMA2 Stream 4 global interrupt */
VECTOR(stm32_eth, STM32_IRQ_ETH) /* Vector 16+61: Ethernet global interrupt */
VECTOR(stm32_ethwkup, STM32_IRQ_ETHWKUP) /* Vector 16+62: Ethernet Wakeup through EXTI line interrupt */
VECTOR(stm32_can2tx, STM32_IRQ_CAN2TX) /* Vector 16+63: CAN2 TX interrupts */
VECTOR(stm32_can2rx0, STM32_IRQ_CAN2RX0) /* Vector 16+64: CAN2 RX0 interrupts */
VECTOR(stm32_can2rx1, STM32_IRQ_CAN2RX1) /* Vector 16+65: CAN2 RX1 interrupt */
VECTOR(stm32_can2sce, STM32_IRQ_CAN2SCE) /* Vector 16+66: CAN2 SCE interrupt */
VECTOR(stm32_otgfs, STM32_IRQ_OTGFS) /* Vector 16+67: USB On The Go FS global interrupt */
VECTOR(stm32_dma2s5, STM32_IRQ_DMA2S5) /* Vector 16+68: DMA2 Stream 5 global interrupt */
VECTOR(stm32_dma2s6, STM32_IRQ_DMA2S6) /* Vector 16+69: DMA2 Stream 6 global interrupt */
VECTOR(stm32_dma2s7, STM32_IRQ_DMA2S7) /* Vector 16+70: DMA2 Stream 7 global interrupt */
VECTOR(stm32_usart6, STM32_IRQ_USART6) /* Vector 16+71: USART6 global interrupt */
VECTOR(stm32_i2c3ev, STM32_IRQ_I2C3EV) /* Vector 16+72: I2C3 event interrupt */
VECTOR(stm32_i2c3er, STM32_IRQ_I2C3ER) /* Vector 16+73: I2C3 error interrupt */
VECTOR(stm32_otghsep1out, STM32_IRQ_OTGHSEP1OUT) /* Vector 16+74: USB On The Go HS End Point 1 Out global interrupt */
VECTOR(stm32_otghsep1in, STM32_IRQ_OTGHSEP1IN) /* Vector 16+75: USB On The Go HS End Point 1 In global interrupt */
VECTOR(stm32_otghswkup, STM32_IRQ_OTGHSWKUP) /* Vector 16+76: USB On The Go HS Wakeup through EXTI interrupt */
VECTOR(stm32_otghs, STM32_IRQ_OTGHS) /* Vector 16+77: USB On The Go HS global interrupt */
VECTOR(stm32_dcmi, STM32_IRQ_DCMI) /* Vector 16+78: DCMI global interrupt */
VECTOR(stm32_cryp, STM32_IRQ_CRYP) /* Vector 16+79: CRYP crypto global interrupt */
VECTOR(stm32_hash, STM32_IRQ_HASH) /* Vector 16+80: Hash and Rng global interrupt */
#endif /* CONFIG_ARMV7M_CMNVECTOR */

149
arch/arm/src/stm32/chip/stm32f30xxx_vectors.h
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@ -1,149 +0,0 @@
/************************************************************************************
* arch/arm/src/stm32/chip/stm32f30xxx_vectors.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Pre-processor definitions
************************************************************************************/
/* This file is included by stm32_vectors.S. It provides the macro VECTOR that
* supplies each STM32F30xxx vector in terms of a (lower-case) ISR label and an
* (upper-case) IRQ number as defined in arch/arm/include/stm32/stm32f30xxx_irq.h.
* stm32_vectors.S will defined the VECTOR in different ways in order to generate
* the interrupt vectors and handlers in their final form.
*/
/* If the common ARMv7-M vector handling is used, then all it needs is the following
* definition that provides the number of supported vectors.
*/
#ifdef CONFIG_ARMV7M_CMNVECTOR
/* Reserve 82 interrupt table entries for I/O interrupts. */
# define ARMV7M_PERIPHERAL_INTERRUPTS 82
#else
VECTOR(stm32_wwdg, STM32_IRQ_WWDG) /* 0: Window Watchdog interrupt */
VECTOR(stm32_pvd, STM32_IRQ_PVD) /* 1: PVD through EXTI Line detection interrupt */
VECTOR(stm32_tamper, STM32_IRQ_TAMPER) /* 2: Tamper or Time stamp interrupt */
VECTOR(stm32_rtc_wkup, STM32_IRQ_RTC_WKUP) /* 3: RTC global interrupt */
VECTOR(stm32_flash, STM32_IRQ_FLASH) /* 4: Flash global interrupt */
VECTOR(stm32_rcc, STM32_IRQ_RCC) /* 5: RCC global interrupt */
VECTOR(stm32_exti0, STM32_IRQ_EXTI0) /* 6: EXTI Line 0 interrupt */
VECTOR(stm32_exti1, STM32_IRQ_EXTI1) /* 7: EXTI Line 1 interrupt */
VECTOR(stm32_exti2, STM32_IRQ_EXTI2) /* 8: EXTI Line 2 or TSC interrupt */
VECTOR(stm32_exti3, STM32_IRQ_EXTI3) /* 9: EXTI Line 3 interrupt */
VECTOR(stm32_exti4, STM32_IRQ_EXTI4) /* 10: EXTI Line 4 interrupt */
VECTOR(stm32_dma1ch1, STM32_IRQ_DMA1CH1) /* 11: DMA1 channel 1 global interrupt */
VECTOR(stm32_dma1ch2, STM32_IRQ_DMA1CH2) /* 12: DMA1 channel 2 global interrupt */
VECTOR(stm32_dma1ch3, STM32_IRQ_DMA1CH3) /* 13: DMA1 channel 3 global interrupt */
VECTOR(stm32_dma1ch4, STM32_IRQ_DMA1CH4) /* 14: DMA1 channel 4 global interrupt */
VECTOR(stm32_dma1ch5, STM32_IRQ_DMA1CH5) /* 15: DMA1 channel 5 global interrupt */
VECTOR(stm32_dma1ch6, STM32_IRQ_DMA1CH6) /* 16: DMA1 channel 6 global interrupt */
VECTOR(stm32_dma1ch7, STM32_IRQ_DMA1CH7) /* 17: DMA1 channel 7 global interrupt */
VECTOR(stm32_adc12, STM32_IRQ_ADC12) /* 18: ADC1/ADC2 global interrupt */
VECTOR(stm32_can1tx, STM32_IRQ_CAN1TX) /* 19: USB High Priority or CAN1 TX interrupts */
VECTOR(stm32_can1rx0, STM32_IRQ_CAN1RX0) /* 20: USB Low Priority or CAN1 RX0 interrupts*/
VECTOR(stm32_can1rx1, STM32_IRQ_CAN1RX1) /* 21: CAN1 RX1 interrupt */
VECTOR(stm32_can1sce, STM32_IRQ_CAN1SCE) /* 22: CAN1 SCE interrupt */
VECTOR(stm32_exti95, STM32_IRQ_EXTI95) /* 23: EXTI Line[9:5] interrupts */
VECTOR(stm32_tim1brk, STM32_IRQ_TIM1BRK) /* 24: TIM1 Break or TIM15 global interrupt */
VECTOR(stm32_tim1up, STM32_IRQ_TIM1UP) /* 25: TIM1 Update or TIM16 global interrupt */
VECTOR(stm32_tim1trgcom, STM32_IRQ_TIM1TRGCOM) /* 26: TIM1 Trigger or TIM17 global interrupt */
VECTOR(stm32_tim1cc, STM32_IRQ_TIM1CC) /* 27: TIM1 Capture Compare interrupt */
VECTOR(stm32_tim2, STM32_IRQ_TIM2) /* 28: TIM2 global interrupt */
VECTOR(stm32_tim3, STM32_IRQ_TIM3) /* 29: TIM3 global interrupt */
VECTOR(stm32_tim4, STM32_IRQ_TIM4) /* 30: TIM4 global interrupt */
VECTOR(stm32_i2c1ev, STM32_IRQ_I2C1EV) /* 31: I2C1 event or EXTI Line23 interrupt */
VECTOR(stm32_i2c1er, STM32_IRQ_I2C1ER) /* 32: I2C1 error interrupt */
VECTOR(stm32_i2c2ev, STM32_IRQ_I2C2EV) /* 33: I2C2 event or EXTI Line24 interrupt */
VECTOR(stm32_i2c2er, STM32_IRQ_I2C2ER) /* 34: I2C2 error interrupt */
VECTOR(stm32_spi1, STM32_IRQ_SPI1) /* 35: SPI1 global interrupt */
VECTOR(stm32_spi2, STM32_IRQ_SPI2) /* 36: SPI2 global interrupt */
VECTOR(stm32_usart1, STM32_IRQ_USART1) /* 37: USART1 global or EXTI Line 25 interrupt */
VECTOR(stm32_usart2, STM32_IRQ_USART2) /* 38: USART2 global or EXTI Line 26 interrupt */
VECTOR(stm32_usart3, STM32_IRQ_USART3) /* 39: USART3 global or EXTI Line 28 interrupt */
VECTOR(stm32_exti1510, STM32_IRQ_EXTI1510) /* 40: EXTI Line[15:10] interrupts */
VECTOR(stm32_rtcalrm, STM32_IRQ_RTCALRM) /* 41: RTC alarm through EXTI line interrupt */
VECTOR(stm32_ext18, STM32_IRQ_EXT18) /* 42: USB wakeup or EXTI Line 18 interrupt */
VECTOR(stm32_tim8brk, STM32_IRQ_TIM8BRK) /* 43: TIM8 Break interrupt */
VECTOR(stm32_tim8up, STM32_IRQ_TIM8UP) /* 44: TIM8 Update interrupt */
VECTOR(stm32_tim8trgcom, STM32_IRQ_TIM8TRGCOM) /* 45: TIM8 Trigger and Commutation interrupts */
VECTOR(stm32_tim8cc, STM32_IRQ_TIM8CC) /* 46: TIM8 Capture Compare interrupt */
VECTOR(stm32_adc3, STM32_IRQ_ADC3) /* 47: ADC3 global interrupt */
UNUSED(STM32_IRQ_RESERVED48) /* 48: Reserved */
UNUSED(STM32_IRQ_RESERVED49) /* 49: Reserved */
UNUSED(STM32_IRQ_RESERVED50) /* 50: Reserved */
VECTOR(stm32_spi3, STM32_IRQ_SPI3) /* 51: SPI3 global interrupt */
VECTOR(stm32_uart4, STM32_IRQ_UART4) /* 52: UART4 global or EXTI Line 34 interrupt */
VECTOR(stm32_uart5, STM32_IRQ_UART5) /* 53: UART5 global or EXTI Line 35 interrupt */
VECTOR(stm32_tim6, STM32_IRQ_TIM6) /* 54: TIM6 global or DAC1/2 underrun interrupts */
VECTOR(stm32_tim7, STM32_IRQ_TIM7) /* 55: TIM7 global interrupt */
VECTOR(stm32_dma2ch1, STM32_IRQ_DMA2CH1) /* 56: DMA2 channel 1 global interrupt */
VECTOR(stm32_dma2ch2, STM32_IRQ_DMA2CH2) /* 57: DMA2 channel 2 global interrupt */
VECTOR(stm32_dma2ch3, STM32_IRQ_DMA2CH3) /* 58: DMA2 channel 3 global interrupt */
VECTOR(stm32_dma2ch4, STM32_IRQ_DMA2CH4) /* 59: DMA2 channel 4 global interrupt */
VECTOR(stm32_dma2ch5, STM32_IRQ_DMA2CH5) /* 60: DMA2 channel 5 global interrupt */
VECTOR(stm32_adc4, STM32_IRQ_ADC4) /* 61: ADC4 global interrupt */
UNUSED(STM32_IRQ_RESERVED62) /* 62: Reserved */
UNUSED(STM32_IRQ_RESERVED63) /* 63: Reserved */
VECTOR(stm32_comp123, STM32_IRQ_COMP123) /* 64: COMP1-3 or EXTI Lines 21-2 and 29 interrupts */
VECTOR(stm32_comp456, STM32_IRQ_COMP456) /* 65: COMP4-6 or EXTI Lines 30-2 interrupts */
VECTOR(stm32_comp7, STM32_IRQ_COMP7) /* 66: COMP7 or EXTI Line 33 interrupt */
UNUSED(STM32_IRQ_RESERVED67) /* 67: Reserved */
UNUSED(STM32_IRQ_RESERVED68) /* 68: Reserved */
UNUSED(STM32_IRQ_RESERVED69) /* 69: Reserved */
UNUSED(STM32_IRQ_RESERVED70) /* 70: Reserved */
UNUSED(STM32_IRQ_RESERVED71) /* 71: Reserved */
UNUSED(STM32_IRQ_RESERVED72) /* 72: Reserved */
UNUSED(STM32_IRQ_RESERVED73) /* 73: Reserved */
VECTOR(stm32_usbhp, STM32_IRQ_USBHP_2) /* 74: USB High priority interrupt */
VECTOR(stm32_usblp, STM32_IRQ_USBLP_2) /* 75: USB Low priority interrupt */
VECTOR(stm32_usbwkup, STM32_IRQ_USBWKUP_2) /* 76: USB wakeup from suspend through EXTI line interrupt*/
UNUSED(STM32_IRQ_RESERVED77) /* 77: Reserved */
UNUSED(STM32_IRQ_RESERVED78) /* 78: Reserved */
UNUSED(STM32_IRQ_RESERVED79) /* 79: Reserved */
UNUSED(STM32_IRQ_RESERVED80) /* 80: Reserved */
VECTOR(stm32_fpu, STM32_IRQ_FPU) /* 81: FPU global interrupt */
#endif /* CONFIG_ARMV7M_CMNVECTOR */

151
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@ -1,151 +0,0 @@
/************************************************************************************
* arch/arm/src/stm32/chip/stm32f33xxx_vectors.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Modified for STM32F334 by Mateusz Szafoni <raiden00@railab.me>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Pre-processor definitions
************************************************************************************/
/* This file is included by stm32_vectors.S. It provides the macro VECTOR that
* supplies each STM32F33xxx vector in terms of a (lower-case) ISR label and an
* (upper-case) IRQ number as defined in arch/arm/include/stm32/stm32f33xxx_irq.h.
* stm32_vectors.S will defined the VECTOR in different ways in order to generate
* the interrupt vectors and handlers in their final form.
*/
/* If the common ARMv7-M vector handling is used, then all it needs is the following
* definition that provides the number of supported vectors.
*/
#ifdef CONFIG_ARMV7M_CMNVECTOR
/* Reserve 82 interrupt table entries for I/O interrupts. */
# define ARMV7M_PERIPHERAL_INTERRUPTS 82
#else
VECTOR(stm32_wwdg, STM32_IRQ_WWDG) /* 0: Window Watchdog interrupt */
VECTOR(stm32_pvd, STM32_IRQ_PVD) /* 1: PVD through EXTI Line detection interrupt */
VECTOR(stm32_tamper, STM32_IRQ_TAMPER) /* 2: Tamper or Time stamp interrupt */
VECTOR(stm32_rtc_wkup, STM32_IRQ_RTC_WKUP) /* 3: RTC global interrupt */
VECTOR(stm32_flash, STM32_IRQ_FLASH) /* 4: Flash global interrupt */
VECTOR(stm32_rcc, STM32_IRQ_RCC) /* 5: RCC global interrupt */
VECTOR(stm32_exti0, STM32_IRQ_EXTI0) /* 6: EXTI Line 0 interrupt */
VECTOR(stm32_exti1, STM32_IRQ_EXTI1) /* 7: EXTI Line 1 interrupt */
VECTOR(stm32_exti2, STM32_IRQ_EXTI2) /* 8: EXTI Line 2 or TSC interrupt */
VECTOR(stm32_exti3, STM32_IRQ_EXTI3) /* 9: EXTI Line 3 interrupt */
VECTOR(stm32_exti4, STM32_IRQ_EXTI4) /* 10: EXTI Line 4 interrupt */
VECTOR(stm32_dma1ch1, STM32_IRQ_DMA1CH1) /* 11: DMA1 channel 1 global interrupt */
VECTOR(stm32_dma1ch2, STM32_IRQ_DMA1CH2) /* 12: DMA1 channel 2 global interrupt */
VECTOR(stm32_dma1ch3, STM32_IRQ_DMA1CH3) /* 13: DMA1 channel 3 global interrupt */
VECTOR(stm32_dma1ch4, STM32_IRQ_DMA1CH4) /* 14: DMA1 channel 4 global interrupt */
VECTOR(stm32_dma1ch5, STM32_IRQ_DMA1CH5) /* 15: DMA1 channel 5 global interrupt */
VECTOR(stm32_dma1ch6, STM32_IRQ_DMA1CH6) /* 16: DMA1 channel 6 global interrupt */
VECTOR(stm32_dma1ch7, STM32_IRQ_DMA1CH7) /* 17: DMA1 channel 7 global interrupt */
VECTOR(stm32_adc12, STM32_IRQ_ADC12) /* 18: ADC1/ADC2 global interrupt */
VECTOR(stm32_can1tx, STM32_IRQ_CAN1TX) /* 19: USB High Priority or CAN1 TX interrupts */
VECTOR(stm32_can1rx0, STM32_IRQ_CAN1RX0) /* 20: USB Low Priority or CAN1 RX0 interrupts*/
VECTOR(stm32_can1rx1, STM32_IRQ_CAN1RX1) /* 21: CAN1 RX1 interrupt */
VECTOR(stm32_can1sce, STM32_IRQ_CAN1SCE) /* 22: CAN1 SCE interrupt */
VECTOR(stm32_exti95, STM32_IRQ_EXTI95) /* 23: EXTI Line[9:5] interrupts */
VECTOR(stm32_tim1brk, STM32_IRQ_TIM1BRK) /* 24: TIM1 Break or TIM15 global interrupt */
VECTOR(stm32_tim1up, STM32_IRQ_TIM1UP) /* 25: TIM1 Update or TIM16 global interrupt */
VECTOR(stm32_tim1trgcom, STM32_IRQ_TIM1TRGCOM) /* 26: TIM1 Trigger or TIM17 global interrupt */
VECTOR(stm32_tim1cc, STM32_IRQ_TIM1CC) /* 27: TIM1 Capture Compare interrupt */
VECTOR(stm32_tim2, STM32_IRQ_TIM2) /* 28: TIM2 global interrupt */
VECTOR(stm32_tim3, STM32_IRQ_TIM3) /* 29: TIM3 global interrupt */
UNUSED(STM32_IRQ_RESERVED30) /* 30: Reserved */
VECTOR(stm32_i2c1ev, STM32_IRQ_I2C1EV) /* 31: I2C1 event or EXTI Line23 interrupt */
VECTOR(stm32_i2c1er, STM32_IRQ_I2C1ER) /* 32: I2C1 error interrupt */
UNUSED(STM32_IRQ_RESERVED33) /* 33: Reserved */
UNUSED(STM32_IRQ_RESERVED34) /* 34: Reserved */
VECTOR(stm32_spi1, STM32_IRQ_SPI1) /* 35: SPI1 global interrupt */
UNUSED(STM32_IRQ_RESERVED36) /* 36: Reserved */
VECTOR(stm32_usart1, STM32_IRQ_USART1) /* 37: USART1 global or EXTI Line 25 interrupt */
VECTOR(stm32_usart2, STM32_IRQ_USART2) /* 38: USART2 global or EXTI Line 26 interrupt */
VECTOR(stm32_usart3, STM32_IRQ_USART3) /* 39: USART3 global or EXTI Line 28 interrupt */
VECTOR(stm32_exti1510, STM32_IRQ_EXTI1510) /* 40: EXTI Line[15:10] interrupts */
VECTOR(stm32_rtcalrm, STM32_IRQ_RTCALRM) /* 41: RTC alarm through EXTI line interrupt */
UNUSED(STM32_IRQ_RESERVED42) /* 42: Reserved */
UNUSED(STM32_IRQ_RESERVED43) /* 43: Reserved */
UNUSED(STM32_IRQ_RESERVED44) /* 44: Reserved */
UNUSED(STM32_IRQ_RESERVED45) /* 45: Reserved */
UNUSED(STM32_IRQ_RESERVED46) /* 46: Reserved */
UNUSED(STM32_IRQ_RESERVED47) /* 47: Reserved*/
UNUSED(STM32_IRQ_RESERVED48) /* 48: Reserved */
UNUSED(STM32_IRQ_RESERVED49) /* 49: Reserved */
UNUSED(STM32_IRQ_RESERVED50) /* 50: Reserved */
UNUSED(STM32_IRQ_RESERVED51) /* 51: Reserved */
UNUSED(STM32_IRQ_RESERVED51) /* 52: Reserved */
UNUSED(STM32_IRQ_RESERVED52) /* 53: Reserved */
VECTOR(stm32_dac1, STM32_IRQ_DAC1) /* 54: TIM6 global or DAC1 underrun interrupts */
VECTOR(stm32_dac2, STM32_IRQ_DAC2) /* 55: TIM7 global or DAC2 underrun interrupt */
UNUSED(STM32_IRQ_RESERVED56) /* 56: Reserved */
UNUSED(STM32_IRQ_RESERVED57) /* 57: Reserved */
UNUSED(STM32_IRQ_RESERVED58) /* 58: Reserved */
UNUSED(STM32_IRQ_RESERVED59) /* 59: Reserved */
UNUSED(STM32_IRQ_RESERVED60) /* 60: Reserved */
UNUSED(STM32_IRQ_RESERVED61) /* 61: Reserved */
UNUSED(STM32_IRQ_RESERVED62) /* 62: Reserved */
UNUSED(STM32_IRQ_RESERVED63) /* 63: Reserved */
VECTOR(stm32_comp2, STM32_IRQ_COMP2) /* 64: COMP2 or EXTI Lines 21-2 and 29 interrupts */
VECTOR(stm32_comp46, STM32_IRQ_COMP46) /* 65: COMP4/COMP6 or EXTI Lines 30-2 interrupts */
UNUSED(STM32_IRQ_RESERVED66) /* 66: Reserved */
VECTOR(stm32_hrtim_tm, STM32_IRQ_HRTIMTM) /* 67: HRTIM master timer interrutp */
VECTOR(stm32_hrtim_ta, STM32_IRQ_HRTIMTA) /* 68: HRTIM timer A interrutp */
VECTOR(stm32_hrtim_tb, STM32_IRQ_HRTIMTB) /* 69: HRTIM timer B interrutp */
VECTOR(stm32_hrtim_tc, STM32_IRQ_HRTIMTC) /* 70: HRTIM timer C interrutp */
VECTOR(stm32_hrtim_td, STM32_IRQ_HRTIMTD) /* 71: HRTIM timer D interrutp */
VECTOR(stm32_hrtim_te, STM32_IRQ_HRTIMTE) /* 72: HRTIM timer E interrutp */
VECTOR(stm32_hrtim_flt, STM32_IRQ_HRTIMFLT) /* 73: HRTIM fault interrutp */
UNUSED(STM32_IRQ_RESERVED73) /* 74: Reserved */
UNUSED(STM32_IRQ_RESERVED74) /* 75: Reserved */
UNUSED(STM32_IRQ_RESERVED75) /* 76: Reserved */
UNUSED(STM32_IRQ_RESERVED76) /* 77: Reserved */
UNUSED(STM32_IRQ_RESERVED77) /* 78: Reserved */
UNUSED(STM32_IRQ_RESERVED78) /* 79: Reserved */
UNUSED(STM32_IRQ_RESERVED79) /* 80: Reserved */
UNUSED(STM32_IRQ_RESERVED80) /* 81: Reserved */
VECTOR(stm32_fpu, STM32_IRQ_FPU) /* 82: FPU global interrupt */
#endif /* CONFIG_ARMV7M_CMNVECTOR */

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@ -1,150 +0,0 @@
/************************************************************************************
* arch/arm/src/stm32/chip/stm32f37xxx_vectors.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Modified for STM32F373 by Marten Svanfeldt <marten@svanfeldt.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Pre-processor definitions
************************************************************************************/
/* This file is included by stm32_vectors.S. It provides the macro VECTOR that
* supplies each STM32F37xxx vector in terms of a (lower-case) ISR label and an
* (upper-case) IRQ number as defined in arch/arm/include/stm32/stm32f37xxx_irq.h.
* stm32_vectors.S will defined the VECTOR in different ways in order to generate
* the interrupt vectors and handlers in their final form.
*/
/* If the common ARMv7-M vector handling is used, then all it needs is the following
* definition that provides the number of supported vectors.
*/
#ifdef CONFIG_ARMV7M_CMNVECTOR
/* Reserve 82 interrupt table entries for I/O interrupts. */
# define ARMV7M_PERIPHERAL_INTERRUPTS 82
#else
VECTOR(stm32_wwdg, STM32_IRQ_WWDG) /* 0: Window Watchdog interrupt */
VECTOR(stm32_pvd, STM32_IRQ_PVD) /* 1: PVD through EXTI Line detection interrupt */
VECTOR(stm32_tamper, STM32_IRQ_TAMPER) /* 2: Tamper or Time stamp interrupt */
VECTOR(stm32_rtc_wkup, STM32_IRQ_RTC_WKUP) /* 3: RTC global interrupt */
VECTOR(stm32_flash, STM32_IRQ_FLASH) /* 4: Flash global interrupt */
VECTOR(stm32_rcc, STM32_IRQ_RCC) /* 5: RCC global interrupt */
VECTOR(stm32_exti0, STM32_IRQ_EXTI0) /* 6: EXTI Line 0 interrupt */
VECTOR(stm32_exti1, STM32_IRQ_EXTI1) /* 7: EXTI Line 1 interrupt */
VECTOR(stm32_exti2, STM32_IRQ_EXTI2) /* 8: EXTI Line 2 or TSC interrupt */
VECTOR(stm32_exti3, STM32_IRQ_EXTI3) /* 9: EXTI Line 3 interrupt */
VECTOR(stm32_exti4, STM32_IRQ_EXTI4) /* 10: EXTI Line 4 interrupt */
VECTOR(stm32_dma1ch1, STM32_IRQ_DMA1CH1) /* 11: DMA1 channel 1 global interrupt */
VECTOR(stm32_dma1ch2, STM32_IRQ_DMA1CH2) /* 12: DMA1 channel 2 global interrupt */
VECTOR(stm32_dma1ch3, STM32_IRQ_DMA1CH3) /* 13: DMA1 channel 3 global interrupt */
VECTOR(stm32_dma1ch4, STM32_IRQ_DMA1CH4) /* 14: DMA1 channel 4 global interrupt */
VECTOR(stm32_dma1ch5, STM32_IRQ_DMA1CH5) /* 15: DMA1 channel 5 global interrupt */
VECTOR(stm32_dma1ch6, STM32_IRQ_DMA1CH6) /* 16: DMA1 channel 6 global interrupt */
VECTOR(stm32_dma1ch7, STM32_IRQ_DMA1CH7) /* 17: DMA1 channel 7 global interrupt */
VECTOR(stm32_adc1, STM32_IRQ_ADC1) /* 18: ADC1 global interrupt */
VECTOR(stm32_can1tx, STM32_IRQ_CAN1TX) /* 19: CAN1 TX interrupts */
VECTOR(stm32_can1rx0, STM32_IRQ_CAN1RX0) /* 20: CAN1 RX0 interrupts*/
VECTOR(stm32_can1rx1, STM32_IRQ_CAN1RX1) /* 21: CAN1 RX1 interrupt */
VECTOR(stm32_can1sce, STM32_IRQ_CAN1SCE) /* 22: CAN1 SCE interrupt */
VECTOR(stm32_exti95, STM32_IRQ_EXTI95) /* 23: EXTI Line[9:5] interrupts */
VECTOR(stm32_tim15, STM32_IRQ_TIM15) /* 24: TIM15 global interrupt */
VECTOR(stm32_tim16, STM32_IRQ_TIM16) /* 25: TIM16 global interrupt */
VECTOR(stm32_tim17, STM32_IRQ_TIM17) /* 26: TIM17 global interrupt */
VECTOR(stm32_tim18, STM32_IRQ_TIM18) /* 27: TIM18 global interrupt or DAC2 interrupt */
VECTOR(stm32_tim2, STM32_IRQ_TIM2) /* 28: TIM2 global interrupt */
VECTOR(stm32_tim3, STM32_IRQ_TIM3) /* 29: TIM3 global interrupt */
VECTOR(stm32_tim4, STM32_IRQ_TIM4) /* 30: TIM4 global interrupt */
VECTOR(stm32_i2c1ev, STM32_IRQ_I2C1EV) /* 31: I2C1 event or EXTI Line23 interrupt */
VECTOR(stm32_i2c1er, STM32_IRQ_I2C1ER) /* 32: I2C1 error interrupt */
VECTOR(stm32_i2c2ev, STM32_IRQ_I2C2EV) /* 33: I2C2 event or EXTI Line24 interrupt */
VECTOR(stm32_i2c2er, STM32_IRQ_I2C2ER) /* 34: I2C2 error interrupt */
VECTOR(stm32_spi1, STM32_IRQ_SPI1) /* 35: SPI1 global interrupt */
VECTOR(stm32_spi2, STM32_IRQ_SPI2) /* 36: SPI2 global interrupt */
VECTOR(stm32_usart1, STM32_IRQ_USART1) /* 37: USART1 global or EXTI Line 25 interrupt */
VECTOR(stm32_usart2, STM32_IRQ_USART2) /* 38: USART2 global or EXTI Line 26 interrupt */
VECTOR(stm32_usart3, STM32_IRQ_USART3) /* 39: USART3 global or EXTI Line 28 interrupt */
VECTOR(stm32_exti1510, STM32_IRQ_EXTI1510) /* 40: EXTI Line[15:10] interrupts */
VECTOR(stm32_rtcalrm, STM32_IRQ_RTCALRM) /* 41: RTC alarm through EXTI line interrupt */
VECTOR(stm32_cec, STM32_IRQ_CEC) /* 42: CEC global interrupt */
VECTOR(stm32_tim12, STM32_IRQ_TIM12) /* 43: TIM12 global interrupt */
VECTOR(stm32_tim13, STM32_IRQ_TIM13) /* 44: TIM13 global interrupt */
VECTOR(stm32_tim14, STM32_IRQ_TIM14) /* 45: TIM14 global interrupt */
UNUSED(STM32_IRQ_RESERVED46) /* 46: Reserved */
UNUSED(STM32_IRQ_RESERVED47) /* 47: Reserved */
UNUSED(STM32_IRQ_RESERVED48) /* 48: Reserved */
UNUSED(STM32_IRQ_RESERVED49) /* 49: Reserved */
UNUSED(STM32_IRQ_RESERVED50) /* 50: Reserved */
VECTOR(stm32_spi3, STM32_IRQ_SPI3) /* 51: SPI3 global interrupt */
UNUSED(STM32_IRQ_RESERVED52) /* 52: Reserved */
UNUSED(STM32_IRQ_RESERVED53) /* 53: Reserved */
VECTOR(stm32_tim6, STM32_IRQ_TIM6) /* 54: TIM6 global or DAC1 underrun interrupts */
VECTOR(stm32_tim7, STM32_IRQ_TIM7) /* 55: TIM7 global interrupt */
VECTOR(stm32_dma2ch1, STM32_IRQ_DMA2CH1) /* 56: DMA2 channel 1 global interrupt */
VECTOR(stm32_dma2ch2, STM32_IRQ_DMA2CH2) /* 57: DMA2 channel 2 global interrupt */
VECTOR(stm32_dma2ch3, STM32_IRQ_DMA2CH3) /* 58: DMA2 channel 3 global interrupt */
VECTOR(stm32_dma2ch4, STM32_IRQ_DMA2CH4) /* 59: DMA2 channel 4 global interrupt */
VECTOR(stm32_dma2ch5, STM32_IRQ_DMA2CH5) /* 60: DMA2 channel 5 global interrupt */
VECTOR(stm32_sdadc1, STM32_IRQ_SDADC1) /* 61: SDADC1 global interrupt */
VECTOR(stm32_sdadc2, STM32_IRQ_SDADC2) /* 62: SDADC2 global interrupt */
VECTOR(stm32_sdadc3, STM32_IRQ_SDADC3) /* 63: SDADC3 global interrupt */
VECTOR(stm32_comp12, STM32_IRQ_COMP12) /* 64: COMP1-2 */
UNUSED(STM32_IRQ_RESERVED65) /* 65: Reserved */
UNUSED(STM32_IRQ_RESERVED66) /* 66: Reserved */
UNUSED(STM32_IRQ_RESERVED67) /* 67: Reserved */
UNUSED(STM32_IRQ_RESERVED68) /* 68: Reserved */
UNUSED(STM32_IRQ_RESERVED69) /* 69: Reserved */
UNUSED(STM32_IRQ_RESERVED70) /* 70: Reserved */
UNUSED(STM32_IRQ_RESERVED71) /* 71: Reserved */
UNUSED(STM32_IRQ_RESERVED72) /* 72: Reserved */
UNUSED(STM32_IRQ_RESERVED73) /* 73: Reserved */
VECTOR(stm32_usbhp, STM32_IRQ_USBHP) /* 74: USB High priority interrupt */
VECTOR(stm32_usblp, STM32_IRQ_USBLP) /* 75: USB Low priority interrupt */
VECTOR(stm32_usbwkup, STM32_IRQ_USBWKUP) /* 76: USB wakeup from suspend through EXTI line interrupt*/
UNUSED(STM32_IRQ_RESERVED77) /* 77: Reserved */
UNUSED(STM32_IRQ_RESERVED78) /* 78: Reserved */
UNUSED(STM32_IRQ_RESERVED79) /* 79: Reserved */
UNUSED(STM32_IRQ_RESERVED80) /* 80: Reserved */
VECTOR(stm32_fpu, STM32_IRQ_FPU) /* 81: FPU global interrupt */
#endif /* CONFIG_ARMV7M_CMNVECTOR */

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@ -1,321 +0,0 @@
/************************************************************************************
* arch/arm/src/stm32/chip/stm32f40xxx_vectors.h
*
* Copyright (C) 2011-2012, 2014-2015, 2017 Gregory Nutt. All rights reserved.
* Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
* Paul Alexander Patience <paul-a.patience@polymtl.ca>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Pre-processor definitions
************************************************************************************/
/* This file is included by stm32_vectors.S. It provides the macro VECTOR that
* supplies each STM32F40xxx vector in terms of a (lower-case) ISR label and an
* (upper-case) IRQ number as defined in arch/arm/include/stm32/stm32f40xxx_irq.h.
* stm32_vectors.S will define the VECTOR macro in different ways in order to generate
* the interrupt vectors and handlers in their final form.
*/
/* If the common ARMv7-M vector handling is used, then all it needs is the following
* definition that provides the number of supported vectors.
*/
#ifdef CONFIG_ARMV7M_CMNVECTOR
/* Reserve interrupt table entries for I/O interrupts. */
# if defined(CONFIG_STM32_STM32F401) || defined(CONFIG_STM32_STM32F411) || \
defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407)
# define ARMV7M_PERIPHERAL_INTERRUPTS 82
# elif defined(CONFIG_STM32_STM32F410)
# define ARMV7M_PERIPHERAL_INTERRUPTS 98
# elif defined(CONFIG_STM32_STM32F427)
# define ARMV7M_PERIPHERAL_INTERRUPTS 87
# elif defined(CONFIG_STM32_STM32F429)
# define ARMV7M_PERIPHERAL_INTERRUPTS 91
# elif defined(CONFIG_STM32_STM32F446)
# define ARMV7M_PERIPHERAL_INTERRUPTS 97
# elif defined(CONFIG_STM32_STM32F469)
# define ARMV7M_PERIPHERAL_INTERRUPTS 93
# endif
#else
VECTOR(stm32_wwdg, STM32_IRQ_WWDG) /* Vector 16+0: Window Watchdog interrupt */
VECTOR(stm32_pvd, STM32_IRQ_PVD) /* Vector 16+1: PVD through EXTI Line detection interrupt */
VECTOR(stm32_tamper, STM32_IRQ_TAMPER) /* Vector 16+2: Tamper and time stamp interrupts */
VECTOR(stm32_rtc_wkup, STM32_IRQ_RTC_WKUP) /* Vector 16+3: RTC global interrupt */
VECTOR(stm32_flash, STM32_IRQ_FLASH) /* Vector 16+4: Flash global interrupt */
VECTOR(stm32_rcc, STM32_IRQ_RCC) /* Vector 16+5: RCC global interrupt */
VECTOR(stm32_exti0, STM32_IRQ_EXTI0) /* Vector 16+6: EXTI Line 0 interrupt */
VECTOR(stm32_exti1, STM32_IRQ_EXTI1) /* Vector 16+7: EXTI Line 1 interrupt */
VECTOR(stm32_exti2, STM32_IRQ_EXTI2) /* Vector 16+8: EXTI Line 2 interrupt */
VECTOR(stm32_exti3, STM32_IRQ_EXTI3) /* Vector 16+9: EXTI Line 3 interrupt */
VECTOR(stm32_exti4, STM32_IRQ_EXTI4) /* Vector 16+10: EXTI Line 4 interrupt */
VECTOR(stm32_dma1s0, STM32_IRQ_DMA1S0) /* Vector 16+11: DMA1 Stream 0 global interrupt */
VECTOR(stm32_dma1s1, STM32_IRQ_DMA1S1) /* Vector 16+12: DMA1 Stream 1 global interrupt */
VECTOR(stm32_dma1s2, STM32_IRQ_DMA1S2) /* Vector 16+13: DMA1 Stream 2 global interrupt */
VECTOR(stm32_dma1s3, STM32_IRQ_DMA1S3) /* Vector 16+14: DMA1 Stream 3 global interrupt */
VECTOR(stm32_dma1s4, STM32_IRQ_DMA1S4) /* Vector 16+15: DMA1 Stream 4 global interrupt */
VECTOR(stm32_dma1s5, STM32_IRQ_DMA1S5) /* Vector 16+16: DMA1 Stream 5 global interrupt */
VECTOR(stm32_dma1s6, STM32_IRQ_DMA1S6) /* Vector 16+17: DMA1 Stream 6 global interrupt */
VECTOR(stm32_adc, STM32_IRQ_ADC) /* Vector 16+18: ADC1, ADC2, and ADC3 global interrupt */
#if defined(CONFIG_STM32_STM32F410)
UNUSED(STM32_IRQ_RESERVED19) /* Vector 16+19: Reserved */
UNUSED(STM32_IRQ_RESERVED20) /* Vector 16+20: Reserved */
UNUSED(STM32_IRQ_RESERVED21) /* Vector 16+21: Reserved */
UNUSED(STM32_IRQ_RESERVED22) /* Vector 16+22: Reserved */
#else
VECTOR(stm32_can1tx, STM32_IRQ_CAN1TX) /* Vector 16+19: CAN1 TX interrupts */
VECTOR(stm32_can1rx0, STM32_IRQ_CAN1RX0) /* Vector 16+20: CAN1 RX0 interrupts */
VECTOR(stm32_can1rx1, STM32_IRQ_CAN1RX1) /* Vector 16+21: CAN1 RX1 interrupt */
VECTOR(stm32_can1sce, STM32_IRQ_CAN1SCE) /* Vector 16+22: CAN1 SCE interrupt */
#endif
VECTOR(stm32_exti95, STM32_IRQ_EXTI95) /* Vector 16+23: EXTI Line[9:5] interrupts */
VECTOR(stm32_tim1brk, STM32_IRQ_TIM1BRK) /* Vector 16+24: TIM1 Break interrupt/TIM9 global interrupt */
VECTOR(stm32_tim1up, STM32_IRQ_TIM1UP) /* Vector 16+25: TIM1 Update interrupt/TIM10 global interrupt */
VECTOR(stm32_tim1trgcom, STM32_IRQ_TIM1TRGCOM) /* Vector 16+26: TIM1 Trigger and Commutation interrupts/TIM11 global interrupt */
VECTOR(stm32_tim1cc, STM32_IRQ_TIM1CC) /* Vector 16+27: TIM1 Capture Compare interrupt */
#if defined(CONFIG_STM32_STM32F410)
UNUSED(STM32_IRQ_RESERVED28) /* Vector 16+28: Reserved */
UNUSED(STM32_IRQ_RESERVED29) /* Vector 16+29: Reserved */
UNUSED(STM32_IRQ_RESERVED30) /* Vector 16+30: Reserved */
#else
VECTOR(stm32_tim2, STM32_IRQ_TIM2) /* Vector 16+28: TIM2 global interrupt */
VECTOR(stm32_tim3, STM32_IRQ_TIM3) /* Vector 16+29: TIM3 global interrupt */
VECTOR(stm32_tim4, STM32_IRQ_TIM4) /* Vector 16+30: TIM4 global interrupt */
#endif
VECTOR(stm32_i2c1ev, STM32_IRQ_I2C1EV) /* Vector 16+31: I2C1 event interrupt */
VECTOR(stm32_i2c1er, STM32_IRQ_I2C1ER) /* Vector 16+32: I2C1 error interrupt */
VECTOR(stm32_i2c2ev, STM32_IRQ_I2C2EV) /* Vector 16+33: I2C2 event interrupt */
VECTOR(stm32_i2c2er, STM32_IRQ_I2C2ER) /* Vector 16+34: I2C2 error interrupt */
VECTOR(stm32_spi1, STM32_IRQ_SPI1) /* Vector 16+35: SPI1 global interrupt */
VECTOR(stm32_spi2, STM32_IRQ_SPI2) /* Vector 16+36: SPI2 global interrupt */
VECTOR(stm32_usart1, STM32_IRQ_USART1) /* Vector 16+37: USART1 global interrupt */
VECTOR(stm32_usart2, STM32_IRQ_USART2) /* Vector 16+38: USART2 global interrupt */
#if defined(CONFIG_STM32_STM32F410)
UNUSED(STM32_IRQ_RESERVED39) /* Vector 16+39: Reserved */
#else
VECTOR(stm32_usart3, STM32_IRQ_USART3) /* Vector 16+39: USART3 global interrupt */
#endif
VECTOR(stm32_exti1510, STM32_IRQ_EXTI1510) /* Vector 16+40: EXTI Line[15:10] interrupts */
VECTOR(stm32_rtcalrm, STM32_IRQ_RTCALRM) /* Vector 16+41: RTC alarm through EXTI line interrupt */
#if defined(CONFIG_STM32_STM32F410)
UNUSED(STM32_IRQ_RESERVED42) /* Vector 16+42: Reserved */
UNUSED(STM32_IRQ_RESERVED43) /* Vector 16+43: Reserved */
UNUSED(STM32_IRQ_RESERVED44) /* Vector 16+44: Reserved */
UNUSED(STM32_IRQ_RESERVED45) /* Vector 16+45: Reserved */
UNUSED(STM32_IRQ_RESERVED46) /* Vector 16+46: Reserved */
#else
VECTOR(stm32_otgfswkup, STM32_IRQ_OTGFSWKUP) /* Vector 16+42: USB On-The-Go FS Wakeup through EXTI line interrupt */
VECTOR(stm32_tim8brk, STM32_IRQ_TIM8BRK) /* Vector 16+43: TIM8 Break interrupt/TIM12 global interrupt */
VECTOR(stm32_tim8up, STM32_IRQ_TIM8UP) /* Vector 16+44: TIM8 Update interrupt/TIM13 global interrupt */
VECTOR(stm32_tim8trgcom, STM32_IRQ_TIM8TRGCOM) /* Vector 16+45: TIM8 Trigger and Commutation interrupts/TIM14 global interrupt */
VECTOR(stm32_tim8cc, STM32_IRQ_TIM8CC) /* Vector 16+46: TIM8 Capture Compare interrupt */
#endif
VECTOR(stm32_dma1s7, STM32_IRQ_DMA1S7) /* Vector 16+47: DMA1 Stream 7 global interrupt */
#if defined(CONFIG_STM32_STM32F410)
UNUSED(STM32_IRQ_RESERVED48) /* Vector 16+48: Reserved */
UNUSED(STM32_IRQ_RESERVED49) /* Vector 16+49: Reserved */
#else
VECTOR(stm32_fsmc, STM32_IRQ_FSMC) /* Vector 16+48: FSMC global interrupt */
VECTOR(stm32_sdio, STM32_IRQ_SDIO) /* Vector 16+49: SDIO global interrupt */
#endif
VECTOR(stm32_tim5, STM32_IRQ_TIM5) /* Vector 16+50: TIM5 global interrupt */
#if defined(CONFIG_STM32_STM32F410)
UNUSED(STM32_IRQ_RESERVED51) /* Vector 16+51: Reserved */
UNUSED(STM32_IRQ_RESERVED52) /* Vector 16+52: Reserved */
UNUSED(STM32_IRQ_RESERVED53) /* Vector 16+53: Reserved */
#else
VECTOR(stm32_spi3, STM32_IRQ_SPI3) /* Vector 16+51: SPI3 global interrupt */
VECTOR(stm32_uart4, STM32_IRQ_UART4) /* Vector 16+52: UART4 global interrupt */
VECTOR(stm32_uart5, STM32_IRQ_UART5) /* Vector 16+53: UART5 global interrupt */
#endif
VECTOR(stm32_tim6, STM32_IRQ_TIM6) /* Vector 16+54: TIM6 global interrupt/DAC1 and DAC2 underrun error interrupts */
#if defined(CONFIG_STM32_STM32F410)
UNUSED(STM32_IRQ_RESERVED55) /* Vector 16+55: Reserved */
#else
VECTOR(stm32_tim7, STM32_IRQ_TIM7) /* Vector 16+55: TIM7 global interrupt */
#endif
VECTOR(stm32_dma2s0, STM32_IRQ_DMA2S0) /* Vector 16+56: DMA2 Stream 0 global interrupt */
VECTOR(stm32_dma2s1, STM32_IRQ_DMA2S1) /* Vector 16+57: DMA2 Stream 1 global interrupt */
VECTOR(stm32_dma2s2, STM32_IRQ_DMA2S2) /* Vector 16+58: DMA2 Stream 2 global interrupt */
VECTOR(stm32_dma2s3, STM32_IRQ_DMA2S3) /* Vector 16+59: DMA2 Stream 3 global interrupt */
VECTOR(stm32_dma2s4, STM32_IRQ_DMA2S4) /* Vector 16+60: DMA2 Stream 4 global interrupt */
#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F410)
UNUSED(STM32_IRQ_RESERVED61) /* Vector 16+61: Reserved */
UNUSED(STM32_IRQ_RESERVED62) /* Vector 16+62: Reserved */
#else
VECTOR(stm32_eth, STM32_IRQ_ETH) /* Vector 16+61: Ethernet global interrupt */
VECTOR(stm32_ethwkup, STM32_IRQ_ETHWKUP) /* Vector 16+62: Ethernet Wakeup through EXTI line interrupt */
#endif
#if defined(CONFIG_STM32_STM32F410)
UNUSED(STM32_IRQ_RESERVED63) /* Vector 16+63: Reserved */
UNUSED(STM32_IRQ_RESERVED64) /* Vector 16+64: Reserved */
UNUSED(STM32_IRQ_RESERVED65) /* Vector 16+65: Reserved */
UNUSED(STM32_IRQ_RESERVED66) /* Vector 16+66: Reserved */
UNUSED(STM32_IRQ_RESERVED67) /* Vector 16+67: Reserved */
#else
VECTOR(stm32_can2tx, STM32_IRQ_CAN2TX) /* Vector 16+63: CAN2 TX interrupts */
VECTOR(stm32_can2rx0, STM32_IRQ_CAN2RX0) /* Vector 16+64: CAN2 RX0 interrupts */
VECTOR(stm32_can2rx1, STM32_IRQ_CAN2RX1) /* Vector 16+65: CAN2 RX1 interrupt */
VECTOR(stm32_can2sce, STM32_IRQ_CAN2SCE) /* Vector 16+66: CAN2 SCE interrupt */
VECTOR(stm32_otgfs, STM32_IRQ_OTGFS) /* Vector 16+67: USB On The Go FS global interrupt */
#endif
VECTOR(stm32_dma2s5, STM32_IRQ_DMA2S5) /* Vector 16+68: DMA2 Stream 5 global interrupt */
VECTOR(stm32_dma2s6, STM32_IRQ_DMA2S6) /* Vector 16+69: DMA2 Stream 6 global interrupt */
VECTOR(stm32_dma2s7, STM32_IRQ_DMA2S7) /* Vector 16+70: DMA2 Stream 7 global interrupt */
VECTOR(stm32_usart6, STM32_IRQ_USART6) /* Vector 16+71: USART6 global interrupt */
#if defined(CONFIG_STM32_STM32F410)
UNUSED(STM32_IRQ_RESERVED72) /* Vector 16+72: Reserved */
UNUSED(STM32_IRQ_RESERVED73) /* Vector 16+73: Reserved */
UNUSED(STM32_IRQ_RESERVED74) /* Vector 16+74: Reserved */
UNUSED(STM32_IRQ_RESERVED75) /* Vector 16+75: Reserved */
UNUSED(STM32_IRQ_RESERVED76) /* Vector 16+76: Reserved */
UNUSED(STM32_IRQ_RESERVED77) /* Vector 16+77: Reserved */
UNUSED(STM32_IRQ_RESERVED78) /* Vector 16+78: Reserved */
#else
VECTOR(stm32_i2c3ev, STM32_IRQ_I2C3EV) /* Vector 16+72: I2C3 event interrupt */
VECTOR(stm32_i2c3er, STM32_IRQ_I2C3ER) /* Vector 16+73: I2C3 error interrupt */
VECTOR(stm32_otghsep1out, STM32_IRQ_OTGHSEP1OUT) /* Vector 16+74: USB On The Go HS End Point 1 Out global interrupt */
VECTOR(stm32_otghsep1in, STM32_IRQ_OTGHSEP1IN) /* Vector 16+75: USB On The Go HS End Point 1 In global interrupt */
VECTOR(stm32_otghswkup, STM32_IRQ_OTGHSWKUP) /* Vector 16+76: USB On The Go HS Wakeup through EXTI interrupt */
VECTOR(stm32_otghs, STM32_IRQ_OTGHS) /* Vector 16+77: USB On The Go HS global interrupt */
VECTOR(stm32_dcmi, STM32_IRQ_DCMI) /* Vector 16+78: DCMI global interrupt */
#endif
#if defined(CONFIG_STM32_STM32F446)
UNUSED(STM32_IRQ_RESERVED79) /* Vector 16+79: Reserved */
UNUSED(STM32_IRQ_RESERVED80) /* Vector 16+80: Reserved */
#else
# if defined(CONFIG_STM32_STM32F410)
UNUSED(STM32_IRQ_RESERVED79) /* Vector 16+79: Reserved */
# else
VECTOR(stm32_cryp, STM32_IRQ_CRYP) /* Vector 16+79: CRYP crypto global interrupt */
# endif
VECTOR(stm32_hash, STM32_IRQ_HASH) /* Vector 16+80: Hash and Rng global interrupt */
#endif
VECTOR(stm32_fpu, STM32_IRQ_FPU) /* Vector 16+81: FPU global interrupt */
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
defined(CONFIG_STM32_STM32F469)
VECTOR(stm32_uart7, STM32_IRQ_UART7) /* Vector 16+82: UART7 interrupt */
VECTOR(stm32_uart8, STM32_IRQ_UART8) /* Vector 16+83: UART8 interrupt */
#elif defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F410)
UNUSED(STM32_IRQ_RESERVED82) /* Vector 16+82: Reserved */
UNUSED(STM32_IRQ_RESERVED83) /* Vector 16+83: Reserved */
#endif
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
VECTOR(stm32_spi4, STM32_IRQ_SPI4) /* Vector 16+84: SPI4 interrupt */
#elif defined(CONFIG_STM32_STM32F410)
UNUSED(STM32_IRQ_RESERVED84) /* Vector 16+84: Reserved */
#endif
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
defined(CONFIG_STM32_STM32F469)
VECTOR(stm32_spi5, STM32_IRQ_SPI5) /* Vector 16+85: SPI5 interrupt */
VECTOR(stm32_spi6, STM32_IRQ_SPI6) /* Vector 16+86: SPI6 interrupt */
#elif defined(CONFIG_STM32_STM32F446)
UNUSED(STM32_IRQ_RESERVED85) /* Vector 16+85: Reserved */
UNUSED(STM32_IRQ_RESERVED86) /* Vector 16+86: Reserved */
#elif defined(CONFIG_STM32_STM32F410)
VECTOR(stm32_spi5, STM32_IRQ_SPI5) /* Vector 16+85: SPI5 interrupt */
UNUSED(STM32_IRQ_RESERVED86) /* Vector 16+86: Reserved */
#endif
#if defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F446) || \
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
VECTOR(stm32_sai1, STM32_IRQ_SAI1) /* Vector 16+87: SAI1 interrupt */
#elif defined(CONFIG_STM32_STM32F410)
UNUSED(STM32_IRQ_RESERVED87) /* Vector 16+87: Reserved */
#endif
#if defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F469)
VECTOR(stm32_ltdcint, STM32_IRQ_LTDCINT) /* Vector 16+88: LTDC interrupt */
VECTOR(stm32_ltdcerrint, STM32_IRQ_LTDCERRINT) /* Vector 16+89: LTDC Error interrupt */
VECTOR(stm32_dma2d, STM32_IRQ_DMA2D) /* Vector 16+90: DMA2D interrupt */
#elif defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F410)
UNUSED(STM32_IRQ_RESERVED88) /* Vector 16+88: Reserved */
UNUSED(STM32_IRQ_RESERVED89) /* Vector 16+89: Reserved */
UNUSED(STM32_IRQ_RESERVED90) /* Vector 16+90: Reserved */
#endif
#if defined(CONFIG_STM32_STM32F410)
UNUSED(STM32_IRQ_RESERVED91) /* Vector 16+91: Reserved */
UNUSED(STM32_IRQ_RESERVED92) /* Vector 16+92: Reserved */
#elif defined(CONFIG_STM32_STM32F446)
VECTOR(stm32_sai2, STM32_IRQ_SAI2) /* Vector 16+91: SAI2 Global interrupt */
VECTOR(stm32_quadspi, STM32_IRQ_QUADSPI) /* Vector 16+92: QuadSPI Global interrupt */
#elif defined(CONFIG_STM32_STM32F469)
VECTOR(stm32_quadspi, STM32_IRQ_QUADSPI) /* Vector 16+91: QuadSPI Global interrupt */
VECTOR(stm32_dsi, STM32_IRQ_DSI) /* Vector 16+92: DSI Global interrupt */
#endif
#if defined(CONFIG_STM32_STM32F446)
VECTOR(stm32_hdmicec, STM32_IRQ_HDMICEC) /* Vector 16+93: HDMI-CEC Global interrupt */
VECTOR(stm32_spdifrx, STM32_IRQ_SPDIFRX) /* Vector 16+94: SPDIF-Rx Global interrupt */
VECTOR(stm32_fmpi2c1, STM32_IRQ_FMPI2C1) /* Vector 16+95: FMPI2C1 event interrupt */
VECTOR(stm32_fmpi2c1err, STM32_IRQ_FMPI2C1ERR) /* Vector 16+96: FMPI2C1 Error event interrupt */
#endif
#if defined(CONFIG_STM32_STM32F410)
UNUSED(STM32_IRQ_RESERVED93) /* Vector 16+93: Reserved */
UNUSED(STM32_IRQ_RESERVED94) /* Vector 16+94: Reserved */
UNUSED(STM32_IRQ_RESERVED95) /* Vector 16+95: Reserved */
UNUSED(STM32_IRQ_RESERVED96) /* Vector 16+96: Reserved */
UNUSED(STM32_IRQ_RESERVED97) /* Vector 16+97: Reserved */
#endif
#endif /* CONFIG_ARMV7M_CMNVECTOR */

258
arch/arm/src/stm32/chip/stm32l15xxx_vectors.h
View File

@ -1,258 +0,0 @@
/************************************************************************************
* arch/arm/src/stm32/chip/stm32l15xxx_vectors.h
* For STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx advanced ARM-based
* 32-bit MCUs
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Pre-processor definitions
************************************************************************************/
/* This file is included by stm32_vectors.S. It provides the macro VECTOR that
* supplies ach STM32F10xxx vector in terms of a (lower-case) ISR label and an
* (upper-case) IRQ number as defined in arch/arm/include/stm32/stm32f10xxx_irq.h.
* stm32_vectors.S will defined the VECTOR in different ways in order to generate
* the interrupt vectors and handlers in their final form.
*
*
* Vectors for low and medium density devices
*/
#if defined(CONFIG_STM32_LOWDENSITY) || defined(CONFIG_STM32_MEDIUMDENSITY)
/* If the common ARMv7-M vector handling is used, then all it needs is the following
* definition that provides the number of supported vectors.
*/
#ifdef CONFIG_ARMV7M_CMNVECTOR
/* Reserve 45 interrupt table entries for I/O interrupts. */
# define ARMV7M_PERIPHERAL_INTERRUPTS 45
#else
VECTOR(stm32_wwdg, STM32_IRQ_WWDG) /* 0: Window Watchdog interrupt */
VECTOR(stm32_pvd, STM32_IRQ_PVD) /* 1: PVD through EXTI Line detection interrupt */
VECTOR(stm32_tamper, STM32_IRQ_TAMPER) /* 2: Tamper through EXTI line interrupt */
VECTOR(stm32_rtc_wkup, STM32_IRQ_RTC_WKUP) /* 3: RTC Wakeup through EXTI line interrupt */
VECTOR(stm32_flash, STM32_IRQ_FLASH) /* 4: Flash global interrupt */
VECTOR(stm32_rcc, STM32_IRQ_RCC) /* 5: RCC global interrupt */
VECTOR(stm32_exti0, STM32_IRQ_EXTI0) /* 6: EXTI Line 0 interrupt */
VECTOR(stm32_exti1, STM32_IRQ_EXTI1) /* 7: EXTI Line 1 interrupt */
VECTOR(stm32_exti2, STM32_IRQ_EXTI2) /* 8: EXTI Line 2 interrupt */
VECTOR(stm32_exti3, STM32_IRQ_EXTI3) /* 9: EXTI Line 3 interrupt */
VECTOR(stm32_exti4, STM32_IRQ_EXTI4) /* 10: EXTI Line 4 interrupt */
VECTOR(stm32_dma1ch1, STM32_IRQ_DMA1CH1) /* 11: DMA1 channel 1 global interrupt */
VECTOR(stm32_dma1ch2, STM32_IRQ_DMA1CH2) /* 12: DMA1 channel 2 global interrupt */
VECTOR(stm32_dma1ch3, STM32_IRQ_DMA1CH3) /* 13: DMA1 channel 3 global interrupt */
VECTOR(stm32_dma1ch4, STM32_IRQ_DMA1CH4) /* 14: DMA1 channel 4 global interrupt */
VECTOR(stm32_dma1ch5, STM32_IRQ_DMA1CH5) /* 15: DMA1 channel 5 global interrupt */
VECTOR(stm32_dma1ch6, STM32_IRQ_DMA1CH6) /* 16: DMA1 channel 6 global interrupt */
VECTOR(stm32_dma1ch7, STM32_IRQ_DMA1CH7) /* 17: DMA1 channel 7 global interrupt */
VECTOR(stm32_adc1, STM32_IRQ_ADC1) /* 18: ADC1 global interrupt */
VECTOR(stm32_usbhp, STM32_IRQ_USBHP) /* 19: USB High Priority interrupts */
VECTOR(stm32_usblp, STM32_IRQ_USBLP) /* 20: USB Low Priority interrupt */
VECTOR(stm32_dac, STM32_IRQ_DAC) /* 21: DAC interrupt */
VECTOR(stm32_comp, STM32_IRQ_COMP) /* 22: Comparator wakeup through EXTI interrupt */
VECTOR(stm32_exti95, STM32_IRQ_EXTI95) /* 23: EXTI Line[9:5] interrupts */
VECTOR(stm32_ldc, STM32_IRQ_LDC) /* 24: LCD global interrupt */
VECTOR(stm32_tim9, STM32_IRQ_TIM9) /* 25: TIM9 global interrupt */
VECTOR(stm32_tim10, STM32_IRQ_TIM10) /* 26: TIM10 global interrupt */
VECTOR(stm32_tim11, STM32_IRQ_TIM11) /* 27: TIM11 global interrupt */
VECTOR(stm32_tim2, STM32_IRQ_TIM2) /* 28: TIM2 global interrupt */
VECTOR(stm32_tim3, STM32_IRQ_TIM3) /* 29: TIM3 global interrupt */
VECTOR(stm32_tim4, STM32_IRQ_TIM4) /* 30: TIM4 global interrupt */
VECTOR(stm32_i2c1ev, STM32_IRQ_I2C1EV) /* 31: I2C1 event interrupt */
VECTOR(stm32_i2c1er, STM32_IRQ_I2C1ER) /* 32: I2C1 error interrupt */
VECTOR(stm32_i2c2ev, STM32_IRQ_I2C2EV) /* 33: I2C2 event interrupt */
VECTOR(stm32_i2c2er, STM32_IRQ_I2C2ER) /* 34: I2C2 error interrupt */
VECTOR(stm32_spi1, STM32_IRQ_SPI1) /* 35: SPI1 global interrupt */
VECTOR(stm32_spi2, STM32_IRQ_SPI2) /* 36: SPI2 global interrupt */
VECTOR(stm32_usart1, STM32_IRQ_USART1) /* 37: USART1 global interrupt */
VECTOR(stm32_usart2, STM32_IRQ_USART2) /* 38: USART2 global interrupt */
VECTOR(stm32_usart3, STM32_IRQ_USART3) /* 39: USART3 global interrupt */
VECTOR(stm32_exti1510, STM32_IRQ_EXTI1510) /* 40: EXTI Line[15:10] interrupts */
VECTOR(stm32_rtcalrm, STM32_IRQ_RTCALRM) /* 41: RTC alarm through EXTI line interrupt */
VECTOR(stm32_usbwkup, STM32_IRQ_USBWKUP) /* 42: USB wakeup from suspend through EXTI line interrupt */
VECTOR(stm32_tim6, STM32_IRQ_TIM6) /* 43: TIM6 global interrupt */
VECTOR(stm32_TIM7, STM32_IRQ_TIM7) /* 44: TIM7 global interrupt */
#endif
/* Vectors for medium+ density devices */
#elif defined(CONFIG_STM32_MEDIUMPLUSDENSITY)
/* If the common ARMv7-M vector handling is used, then all it needs is the following
* definition that provides the number of supported vectors.
*/
#ifdef CONFIG_ARMV7M_CMNVECTOR
/* Reserve 61 interrupt table entries for I/O interrupts. */
# define ARMV7M_PERIPHERAL_INTERRUPTS 54
#else
VECTOR(stm32_wwdg, STM32_IRQ_WWDG) /* 0: Window Watchdog interrupt */
VECTOR(stm32_pvd, STM32_IRQ_PVD) /* 1: PVD through EXTI Line detection interrupt */
VECTOR(stm32_tamper, STM32_IRQ_TAMPER) /* 2: Tamper through EXTI line interrupt */
VECTOR(stm32_rtc_wkup, STM32_IRQ_RTC_WKUP) /* 3: RTC Wakeup through EXTI line interrupt */
VECTOR(stm32_flash, STM32_IRQ_FLASH) /* 4: Flash global interrupt */
VECTOR(stm32_rcc, STM32_IRQ_RCC) /* 5: RCC global interrupt */
VECTOR(stm32_exti0, STM32_IRQ_EXTI0) /* 6: EXTI Line 0 interrupt */
VECTOR(stm32_exti1, STM32_IRQ_EXTI1) /* 7: EXTI Line 1 interrupt */
VECTOR(stm32_exti2, STM32_IRQ_EXTI2) /* 8: EXTI Line 2 interrupt */
VECTOR(stm32_exti3, STM32_IRQ_EXTI3) /* 9: EXTI Line 3 interrupt */
VECTOR(stm32_exti4, STM32_IRQ_EXTI4) /* 10: EXTI Line 4 interrupt */
VECTOR(stm32_dma1ch1, STM32_IRQ_DMA1CH1) /* 11: DMA1 channel 1 global interrupt */
VECTOR(stm32_dma1ch2, STM32_IRQ_DMA1CH2) /* 12: DMA1 channel 2 global interrupt */
VECTOR(stm32_dma1ch3, STM32_IRQ_DMA1CH3) /* 13: DMA1 channel 3 global interrupt */
VECTOR(stm32_dma1ch4, STM32_IRQ_DMA1CH4) /* 14: DMA1 channel 4 global interrupt */
VECTOR(stm32_dma1ch5, STM32_IRQ_DMA1CH5) /* 15: DMA1 channel 5 global interrupt */
VECTOR(stm32_dma1ch6, STM32_IRQ_DMA1CH6) /* 16: DMA1 channel 6 global interrupt */
VECTOR(stm32_dma1ch7, STM32_IRQ_DMA1CH7) /* 17: DMA1 channel 7 global interrupt */
VECTOR(stm32_adc1, STM32_IRQ_ADC1) /* 18: ADC1 global interrupt */
VECTOR(stm32_usbhp, STM32_IRQ_USBHP) /* 19: USB High Priority interrupts */
VECTOR(stm32_usblp, STM32_IRQ_USBLP) /* 20: USB Low Priority interrupt */
VECTOR(stm32_dac, STM32_IRQ_DAC) /* 21: DAC interrupt */
VECTOR(stm32_comp, STM32_IRQ_COMP) /* 22: Comparator wakeup through EXTI interrupt */
VECTOR(stm32_exti95, STM32_IRQ_EXTI95) /* 23: EXTI Line[9:5] interrupts */
VECTOR(stm32_ldc, STM32_IRQ_LDC) /* 24: LCD global interrupt */
VECTOR(stm32_tim9, STM32_IRQ_TIM9) /* 25: TIM9 global interrupt */
VECTOR(stm32_tim10, STM32_IRQ_TIM10) /* 26: TIM10 global interrupt */
VECTOR(stm32_tim11, STM32_IRQ_TIM11) /* 27: TIM11 global interrupt */
VECTOR(stm32_tim2, STM32_IRQ_TIM2) /* 28: TIM2 global interrupt */
VECTOR(stm32_tim3, STM32_IRQ_TIM3) /* 29: TIM3 global interrupt */
VECTOR(stm32_tim4, STM32_IRQ_TIM4) /* 30: TIM4 global interrupt */
VECTOR(stm32_i2c1ev, STM32_IRQ_I2C1EV) /* 31: I2C1 event interrupt */
VECTOR(stm32_i2c1er, STM32_IRQ_I2C1ER) /* 32: I2C1 error interrupt */
VECTOR(stm32_i2c2ev, STM32_IRQ_I2C2EV) /* 33: I2C2 event interrupt */
VECTOR(stm32_i2c2er, STM32_IRQ_I2C2ER) /* 34: I2C2 error interrupt */
VECTOR(stm32_spi1, STM32_IRQ_SPI1) /* 35: SPI1 global interrupt */
VECTOR(stm32_spi2, STM32_IRQ_SPI2) /* 36: SPI2 global interrupt */
VECTOR(stm32_usart1, STM32_IRQ_USART1) /* 37: USART1 global interrupt */
VECTOR(stm32_usart2, STM32_IRQ_USART2) /* 38: USART2 global interrupt */
VECTOR(stm32_usart3, STM32_IRQ_USART3) /* 39: USART3 global interrupt */
VECTOR(stm32_exti1510, STM32_IRQ_EXTI1510) /* 40: EXTI Line[15:10] interrupts */
VECTOR(stm32_rtcalrm, STM32_IRQ_RTCALRM) /* 41: RTC alarm through EXTI line interrupt */
VECTOR(stm32_usbwkup, STM32_IRQ_USBWKUP) /* 42: USB wakeup from suspend through EXTI line interrupt */
VECTOR(stm32_tim6, STM32_IRQ_TIM6) /* 43: TIM6 global interrupt */
VECTOR(stm32_tim7, STM32_IRQ_TIM7) /* 44: TIM7 global interrupt */
VECTOR(stm32_tim5, STM32_IRQ_TIM5) /* 45: TIM5 global interrupt */
VECTOR(stm32_spi3, STM32_IRQ_SPI3) /* 46: SPI3 global interrupt */
VECTOR(stm32_dma2ch1, STM32_IRQ_DMA2CH1) /* 47: DMA2 channel 1 global interrupt */
VECTOR(stm32_dma2ch2, STM32_IRQ_DMA2CH2) /* 48: DMA2 channel 2 global interrupt */
VECTOR(stm32_dma2ch3, STM32_IRQ_DMA2CH3) /* 49: DMA2 channel 3 global interrupt */
VECTOR(stm32_dma2ch4, STM32_IRQ_DMA2CH4) /* 50: DMA2 channel 4 global interrupt */
VECTOR(stm32_dma2ch5, STM32_IRQ_DMA2CH5) /* 51: DMA2 channel 5 global interrupt */
VECTOR(stm32_aes, STM32_IRQ_AES) /* 52: AES global interrupt */
VECTOR(stm32_compacq, STM32_IRQ_COMPACQ) /* 53: Comparator Channel Acquisition Interrupt */
#endif
/* Vectors for high density devices */
#elif defined(CONFIG_STM32_HIGHDENSITY)
/* If the common ARMv7-M vector handling is used, then all it needs is the following
* definition that provides the number of supported vectors.
*/
#ifdef CONFIG_ARMV7M_CMNVECTOR
/* Reserve 61 interrupt table entries for I/O interrupts. */
# define ARMV7M_PERIPHERAL_INTERRUPTS 57
#else
VECTOR(stm32_wwdg, STM32_IRQ_WWDG) /* 0: Window Watchdog interrupt */
VECTOR(stm32_pvd, STM32_IRQ_PVD) /* 1: PVD through EXTI Line detection interrupt */
VECTOR(stm32_tamper, STM32_IRQ_TAMPER) /* 2: Tamper through EXTI line interrupt */
VECTOR(stm32_rtc_wkup, STM32_IRQ_RTC_WKUP) /* 3: RTC Wakeup through EXTI line interrupt */
VECTOR(stm32_flash, STM32_IRQ_FLASH) /* 4: Flash global interrupt */
VECTOR(stm32_rcc, STM32_IRQ_RCC) /* 5: RCC global interrupt */
VECTOR(stm32_exti0, STM32_IRQ_EXTI0) /* 6: EXTI Line 0 interrupt */
VECTOR(stm32_exti1, STM32_IRQ_EXTI1) /* 7: EXTI Line 1 interrupt */
VECTOR(stm32_exti2, STM32_IRQ_EXTI2) /* 8: EXTI Line 2 interrupt */
VECTOR(stm32_exti3, STM32_IRQ_EXTI3) /* 9: EXTI Line 3 interrupt */
VECTOR(stm32_exti4, STM32_IRQ_EXTI4) /* 10: EXTI Line 4 interrupt */
VECTOR(stm32_dma1ch1, STM32_IRQ_DMA1CH1) /* 11: DMA1 channel 1 global interrupt */
VECTOR(stm32_dma1ch2, STM32_IRQ_DMA1CH2) /* 12: DMA1 channel 2 global interrupt */
VECTOR(stm32_dma1ch3, STM32_IRQ_DMA1CH3) /* 13: DMA1 channel 3 global interrupt */
VECTOR(stm32_dma1ch4, STM32_IRQ_DMA1CH4) /* 14: DMA1 channel 4 global interrupt */
VECTOR(stm32_dma1ch5, STM32_IRQ_DMA1CH5) /* 15: DMA1 channel 5 global interrupt */
VECTOR(stm32_dma1ch6, STM32_IRQ_DMA1CH6) /* 16: DMA1 channel 6 global interrupt */
VECTOR(stm32_dma1ch7, STM32_IRQ_DMA1CH7) /* 17: DMA1 channel 7 global interrupt */
VECTOR(stm32_adc1, STM32_IRQ_ADC1) /* 18: ADC1 global interrupt */
VECTOR(stm32_usbhp, STM32_IRQ_USBHP) /* 19: USB High Priority interrupts */
VECTOR(stm32_usblp, STM32_IRQ_USBLP) /* 20: USB Low Priority interrupt */
VECTOR(stm32_dac, STM32_IRQ_DAC) /* 21: DAC interrupt */
VECTOR(stm32_comp, STM32_IRQ_COMP) /* 22: Comparator wakeup through EXTI interrupt */
VECTOR(stm32_exti95, STM32_IRQ_EXTI95) /* 23: EXTI Line[9:5] interrupts */
VECTOR(stm32_ldc, STM32_IRQ_LDC) /* 24: LCD global interrupt */
VECTOR(stm32_tim9, STM32_IRQ_TIM9) /* 25: TIM9 global interrupt */
VECTOR(stm32_tim10, STM32_IRQ_TIM10) /* 26: TIM10 global interrupt */
VECTOR(stm32_tim11, STM32_IRQ_TIM11) /* 27: TIM11 global interrupt */
VECTOR(stm32_tim2, STM32_IRQ_TIM2) /* 28: TIM2 global interrupt */
VECTOR(stm32_tim3, STM32_IRQ_TIM3) /* 29: TIM3 global interrupt */
VECTOR(stm32_tim4, STM32_IRQ_TIM4) /* 30: TIM4 global interrupt */
VECTOR(stm32_i2c1ev, STM32_IRQ_I2C1EV) /* 31: I2C1 event interrupt */
VECTOR(stm32_i2c1er, STM32_IRQ_I2C1ER) /* 32: I2C1 error interrupt */
VECTOR(stm32_i2c2ev, STM32_IRQ_I2C2EV) /* 33: I2C2 event interrupt */
VECTOR(stm32_i2c2er, STM32_IRQ_I2C2ER) /* 34: I2C2 error interrupt */
VECTOR(stm32_spi1, STM32_IRQ_SPI1) /* 35: SPI1 global interrupt */
VECTOR(stm32_spi2, STM32_IRQ_SPI2) /* 36: SPI2 global interrupt */
VECTOR(stm32_usart1, STM32_IRQ_USART1) /* 37: USART1 global interrupt */
VECTOR(stm32_usart2, STM32_IRQ_USART2) /* 38: USART2 global interrupt */
VECTOR(stm32_usart3, STM32_IRQ_USART3) /* 39: USART3 global interrupt */
VECTOR(stm32_exti1510, STM32_IRQ_EXTI1510) /* 40: EXTI Line[15:10] interrupts */
VECTOR(stm32_rtcalrm, STM32_IRQ_RTCALRM) /* 41: RTC alarm through EXTI line interrupt */
VECTOR(stm32_usbwkup, STM32_IRQ_USBWKUP) /* 42: USB wakeup from suspend through EXTI line interrupt */
VECTOR(stm32_tim6, STM32_IRQ_TIM6) /* 43: TIM6 global interrupt */
VECTOR(stm32_tim7, STM32_IRQ_TIM7) /* 44: TIM7 global interrupt */
VECTOR(stm32_sdio, STM32_IRQ_SDIO) /* 45: SDIO Global interrupt */
VECTOR(stm32_tim5, STM32_IRQ_TIM5) /* 46: TIM5 global interrupt */
VECTOR(stm32_spi3, STM32_IRQ_SPI3) /* 47: SPI3 global interrupt */
VECTOR(stm32_usart4, STM32_IRQ_UART4) /* 48: UART4 global interrupt */
VECTOR(stm32_usart5, STM32_IRQ_UART5) /* 49: UART5 global interrupt */
VECTOR(stm32_dma2ch1, STM32_IRQ_DMA2CH1) /* 50: DMA2 channel 1 global interrupt */
VECTOR(stm32_dma2ch2, STM32_IRQ_DMA2CH2) /* 51: DMA2 channel 2 global interrupt */
VECTOR(stm32_dma2ch3, STM32_IRQ_DMA2CH3) /* 52: DMA2 channel 3 global interrupt */
VECTOR(stm32_dma2ch4, STM32_IRQ_DMA2CH4) /* 53: DMA2 channel 4 global interrupt */
VECTOR(stm32_dma2ch5, STM32_IRQ_DMA2CH5) /* 54: DMA2 channel 5 global interrupt */
VECTOR(stm32_aes, STM32_IRQ_AES) /* 55: AES global interrupt */
VECTOR(stm32_compacq, STM32_IRQ_COMPACQ) /* 56: Comparator Channel Acquisition Interrupt */
#endif
#else
# error "Unknown STM32L density"
#endif

527
arch/arm/src/stm32/gnu/stm32_vectors.S
View File

@ -1,527 +0,0 @@
/************************************************************************************
* arch/arm/src/stm32/gnu/stm32_vectors.S
*
* Copyright (C) 2009-2013, 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <arch/irq.h>
#include "chip.h"
#include "exc_return.h"
/************************************************************************************
* Configuration
************************************************************************************/
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration ********************************************************************/
#ifdef CONFIG_ARCH_HIPRI_INTERRUPT
/* In kernel mode without an interrupt stack, this interrupt handler will set the
* MSP to the stack pointer of the interrupted thread. If the interrupted thread
* was a privileged thread, that will be the MSP otherwise it will be the PSP. If
* the PSP is used, then the value of the MSP will be invalid when the interrupt
* handler returns because it will be a pointer to an old position in the
* unprivileged stack. Then when the high priority interrupt occurs and uses this
* stale MSP, there will most likely be a system failure.
*
* If the interrupt stack is selected, on the other hand, then the interrupt
* handler will always set the MSP to the interrupt stack. So when the high
* priority interrupt occurs, it will either use the MSP of the last privileged
* thread to run or, in the case of the nested interrupt, the interrupt stack if
* no privileged task has run.
*/
# if defined(CONFIG_BUILD_PROTECTED) && CONFIG_ARCH_INTERRUPTSTACK < 4
# error Interrupt stack must be used with high priority interrupts in kernel mode
# endif
/* Use the BASEPRI to control interrupts is required if nested, high
* priority interrupts are supported.
*/
# ifndef CONFIG_ARMV7M_USEBASEPRI
# error CONFIG_ARMV7M_USEBASEPRI must be used with CONFIG_ARCH_HIPRI_INTERRUPT
# endif
#endif
/* Memory Map ***********************************************************************/
/*
* 0x0800:0000 - Beginning of FLASH. Address of vectors (if not using bootloader)
* Mapped to address 0x0000:0000 at boot time.
* 0x0800:3000 - Address of vectors if using bootloader
* 0x0803:ffff - End of flash
* 0x2000:0000 - Start of SRAM and start of .data (_sdata)
* - End of .data (_edata) abd start of .bss (_sbss)
* - End of .bss (_ebss) and bottom of idle stack
* - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack, start of heap
* 0x2000:ffff - End of SRAM and end of heap
*/
#define IDLE_STACK (_ebss+CONFIG_IDLETHREAD_STACKSIZE-4)
#define HEAP_BASE (_ebss+CONFIG_IDLETHREAD_STACKSIZE)
/************************************************************************************
* Public Symbols
************************************************************************************/
.syntax unified
.thumb
.file "stm32_vectors.S"
/* Check if common ARMv7 interrupt vectoring is used (see arch/arm/src/armv7-m/up_vectors.c) */
#ifndef CONFIG_ARMV7M_CMNVECTOR
.globl __start
/************************************************************************************
* Macros
************************************************************************************/
/* On entry into an IRQ, the hardware automatically saves the xPSR, PC, LR, R12, R0-R3
* registers on the stack, then branches to an instantantiation of the following
* macro. This macro simply loads the IRQ number into R0, then jumps to the common
* IRQ handling logic.
*/
.macro HANDLER, label, irqno
.thumb_func
\label:
mov r0, #\irqno
b exception_common
.endm
/************************************************************************************
* Vectors
************************************************************************************/
.section .vectors, "ax"
.code 16
.align 2
.globl _vectors
.type _vectors, function
_vectors:
/* Processor Exceptions */
.word IDLE_STACK /* Vector 0: Reset stack pointer */
.word __start /* Vector 1: Reset vector */
.word stm32_nmi /* Vector 2: Non-Maskable Interrupt (NMI) */
.word stm32_hardfault /* Vector 3: Hard fault */
.word stm32_mpu /* Vector 4: Memory management (MPU) */
.word stm32_busfault /* Vector 5: Bus fault */
.word stm32_usagefault /* Vector 6: Usage fault */
.word stm32_reserved /* Vector 7: Reserved */
.word stm32_reserved /* Vector 8: Reserved */
.word stm32_reserved /* Vector 9: Reserved */
.word stm32_reserved /* Vector 10: Reserved */
.word stm32_svcall /* Vector 11: SVC call */
.word stm32_dbgmonitor /* Vector 12: Debug monitor */
.word stm32_reserved /* Vector 13: Reserved */
.word stm32_pendsv /* Vector 14: Pendable system service request */
.word stm32_systick /* Vector 15: System tick */
/* External Interrupts */
#if !defined(CONFIG_STM32_NOEXT_VECTORS)
#undef VECTOR
#define VECTOR(l,i) .word l
#undef UNUSED
#define UNUSED(i) .word stm32_reserved
#if defined(CONFIG_STM32_STM32L15XX)
# include "chip/stm32l15xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F10XX)
# include "chip/stm32f10xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F20XX)
# include "chip/stm32f20xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F30XX)
# include "chip/stm32f30xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F33XX)
# include "chip/stm32f33xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F37XX)
# include "chip/stm32f37xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F4XXX)
# include "chip/stm32f40xxx_vectors.h"
#else
# error "No vectors for STM32 chip"
#endif
#endif /* CONFIG_STM32_NOEXT_VECTORS */
.size _vectors, .-_vectors
/************************************************************************************
* .text
************************************************************************************/
.text
.type handlers, function
.thumb_func
handlers:
HANDLER stm32_reserved, STM32_IRQ_RESERVED /* Unexpected/reserved vector */
HANDLER stm32_nmi, STM32_IRQ_NMI /* Vector 2: Non-Maskable Interrupt (NMI) */
HANDLER stm32_hardfault, STM32_IRQ_HARDFAULT /* Vector 3: Hard fault */
HANDLER stm32_mpu, STM32_IRQ_MEMFAULT /* Vector 4: Memory management (MPU) */
HANDLER stm32_busfault, STM32_IRQ_BUSFAULT /* Vector 5: Bus fault */
HANDLER stm32_usagefault, STM32_IRQ_USAGEFAULT /* Vector 6: Usage fault */
HANDLER stm32_svcall, STM32_IRQ_SVCALL /* Vector 11: SVC call */
HANDLER stm32_dbgmonitor, STM32_IRQ_DBGMONITOR /* Vector 12: Debug Monitor */
HANDLER stm32_pendsv, STM32_IRQ_PENDSV /* Vector 14: Penable system service request */
HANDLER stm32_systick, STM32_IRQ_SYSTICK /* Vector 15: System tick */
#if !defined(CONFIG_STM32_NOEXT_VECTORS)
#undef VECTOR
#define VECTOR(l,i) HANDLER l, i
#undef UNUSED
#define UNUSED(i)
#if defined(CONFIG_STM32_STM32L15XX)
# include "chip/stm32l15xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F10XX)
# include "chip/stm32f10xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F20XX)
# include "chip/stm32f20xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F30XX)
# include "chip/stm32f30xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F33XX)
# include "chip/stm32f33xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F37XX)
# include "chip/stm32f37xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F4XXX)
# include "chip/stm32f40xxx_vectors.h"
#else
# error "No handlers for STM32 chip"
#endif
#endif /* CONFIG_STM32_NOEXT_VECTORS */
/* Common IRQ handling logic. On entry here, the return stack is on either
* the PSP or the MSP and looks like the following:
*
* REG_XPSR
* REG_R15
* REG_R14
* REG_R12
* REG_R3
* REG_R2
* REG_R1
* MSP->REG_R0
*
* And
* R0 contains the IRQ number
* R14 Contains the EXC_RETURN value
* We are in handler mode and the current SP is the MSP
*/
.globl exception_common
.type exception_common, function
exception_common:
/* Complete the context save */
#ifdef CONFIG_BUILD_PROTECTED
/* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1
* (handler mode) if the stack is on the MSP. It can only be on the PSP if
* EXC_RETURN is 0xfffffffd (unprivileged thread)
*/
tst r14, #EXC_RETURN_PROCESS_STACK /* nonzero if context on process stack */
beq 1f /* Branch if context already on the MSP */
mrs r1, psp /* R1=The process stack pointer (PSP) */
mov sp, r1 /* Set the MSP to the PSP */
1:
#endif
/* r1 holds the value of the stack pointer AFTER the exception handling logic
* pushed the various registers onto the stack. Get r2 = the value of the
* stack pointer BEFORE the interrupt modified it.
*/
mov r2, sp /* R2=Copy of the main/process stack pointer */
add r2, #HW_XCPT_SIZE /* R2=MSP/PSP before the interrupt was taken */
#ifdef CONFIG_ARMV7M_USEBASEPRI
mrs r3, basepri /* R3=Current BASEPRI setting */
#else
mrs r3, primask /* R3=Current PRIMASK setting */
#endif
#ifdef CONFIG_ARCH_FPU
/* Skip over the block of memory reserved for floating pointer register save.
* Lazy FPU register saving is used. FPU registers will be saved in this
* block only if a context switch occurs (this means, of course, that the FPU
* cannot be used in interrupt processing).
*/
sub sp, #(4*SW_FPU_REGS)
#endif
/* Save the remaining registers on the stack after the registers pushed
* by the exception handling logic. r2=SP and r3=primask or basepri, r4-r11,
* r14=register values.
*/
#ifdef CONFIG_BUILD_PROTECTED
stmdb sp!, {r2-r11,r14} /* Save the remaining registers plus the SP value */
#else
stmdb sp!, {r2-r11} /* Save the remaining registers plus the SP value */
#endif
#ifndef CONFIG_ARCH_HIPRI_INTERRUPT
/* Disable interrupts, select the stack to use for interrupt handling
* and call up_doirq to handle the interrupt
*/
cpsid i /* Disable further interrupts */
#else
/* Set the BASEPRI register so that further normal interrupts will be
* masked. Nested, high priority may still occur, however.
*/
mov r2, #NVIC_SYSH_DISABLE_PRIORITY
msr basepri, r2 /* Set the BASEPRI */
#endif
/* There are two arguments to up_doirq:
*
* R0 = The IRQ number
* R1 = The top of the stack points to the saved state
*/
mov r1, sp
/* Also save the top of the stack in a preserved register */
mov r4, sp
#if CONFIG_ARCH_INTERRUPTSTACK > 7
/* If CONFIG_ARCH_INTERRUPTSTACK is defined, we will set the MSP to use
* a special special interrupt stack pointer. The way that this is done
* here prohibits nested interrupts without some additional logic!
*/
ldr sp, =g_intstackbase
#else
/* Otherwise, we will re-use the interrupted thread's stack. That may
* mean using either MSP or PSP stack for interrupt level processing (in
* kernel mode).
*/
bic r2, r4, #7 /* Get the stack pointer with 8-byte alignment */
mov sp, r2 /* Instantiate the aligned stack */
#endif
bl up_doirq /* R0=IRQ, R1=register save (msp) */
mov r1, r4 /* Recover R1=main stack pointer */
/* On return from up_doirq, R0 will hold a pointer to register context
* array to use for the interrupt return. If that return value is the same
* as current stack pointer, then things are relatively easy.
*/
cmp r0, r1 /* Context switch? */
beq 2f /* Branch if no context switch */
/* We are returning with a pending context switch.
*
* If the FPU is enabled, then we will need to restore FPU registers.
* This is not done in normal interrupt save/restore because the cost
* is prohibitive. This is only done when switching contexts. A
* consequence of this is that floating point operations may not be
* performed in interrupt handling logic.
*
* Here:
* r0 = Address of the register save area
*
* NOTE: It is a requirement that up_restorefpu() preserve the value of
* r0!
*/
#ifdef CONFIG_ARCH_FPU
bl up_restorefpu /* Restore the FPU registers */
#endif
/* We are returning with a pending context switch. This case is different
* because in this case, the register save structure does not lie in the
* stack but, rather, within a TCB structure. We'll have to copy some
* values to the stack.
*/
add r1, r0, #SW_XCPT_SIZE /* R1=Address of HW save area in reg array */
ldmia r1, {r4-r11} /* Fetch eight registers in HW save area */
ldr r1, [r0, #(4*REG_SP)] /* R1=Value of SP before interrupt */
stmdb r1!, {r4-r11} /* Store eight registers in HW save area */
#ifdef CONFIG_BUILD_PROTECTED
ldmia r0, {r2-r11,r14} /* Recover R4-R11, r14 + 2 temp values */
#else
ldmia r0, {r2-r11} /* Recover R4-R11 + 2 temp values */
#endif
b 3f /* Re-join common logic */
/* We are returning with no context switch. We simply need to "unwind"
* the same stack frame that we created
*
* Here:
* r1 = Address of the return stack (same as r0)
*/
2:
#ifdef CONFIG_BUILD_PROTECTED
ldmia r1!, {r2-r11,r14} /* Recover R4-R11, r14 + 2 temp values */
#else
ldmia r1!, {r2-r11} /* Recover R4-R11 + 2 temp values */
#endif
#ifdef CONFIG_ARCH_FPU
/* Skip over the block of memory reserved for floating pointer register
* save. Then R1 is the address of the HW save area
*/
add r1, #(4*SW_FPU_REGS)
#endif
/* Set up to return from the exception
*
* Here:
* r1 = Address on the target thread's stack position at the start of
* the registers saved by hardware
* r3 = primask or basepri
* r4-r11 = restored register values
*/
3:
#ifdef CONFIG_BUILD_PROTECTED
/* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1
* (handler mode) if the stack is on the MSP. It can only be on the PSP if
* EXC_RETURN is 0xfffffffd (unprivileged thread)
*/
mrs r2, control /* R2=Contents of the control register */
tst r14, #EXC_RETURN_PROCESS_STACK /* nonzero if context on process stack */
beq 4f /* Branch if privileged */
orr r2, r2, #1 /* Unprivileged mode */
msr psp, r1 /* R1=The process stack pointer */
b 5f
4:
bic r2, r2, #1 /* Privileged mode */
msr msp, r1 /* R1=The main stack pointer */
5:
msr control, r2 /* Save the updated control register */
#else
msr msp, r1 /* Recover the return MSP value */
/* Preload r14 with the special return value first (so that the return
* actually occurs with interrupts still disabled).
*/
ldr r14, =EXC_RETURN_PRIVTHR /* Load the special value */
#endif
/* Restore the interrupt state */
#ifdef CONFIG_ARMV7M_USEBASEPRI
msr basepri, r3 /* Restore interrupts priority masking */
#ifndef CONFIG_ARCH_HIPRI_INTERRUPT
cpsie i /* Re-enable interrupts */
#endif
#else
msr primask, r3 /* Restore interrupts */
#endif
/* Always return with R14 containing the special value that will: (1)
* return to thread mode, and (2) continue to use the MSP
*/
bx r14 /* And return */
.size handlers, .-handlers
/************************************************************************************
* Name: g_intstackalloc/g_intstackbase
*
* Description:
* Shouldn't happen
*
************************************************************************************/
#if CONFIG_ARCH_INTERRUPTSTACK > 7
.bss
.global g_intstackalloc
.global g_intstackbase
.align 8
g_intstackalloc:
.skip ((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
g_intstackbase:
.size g_intstackalloc, .-g_intstackalloc
#endif
#endif /* CONFIG_ARMV7M_CMNVECTOR */
/************************************************************************************
* .rodata
************************************************************************************/
.section .rodata, "a"
/* Variables: _sbss is the start of the BSS region (see ld.script) _ebss is the end
* of the BSS regsion (see ld.script). The idle task stack starts at the end of BSS
* and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE thread is the thread that
* the system boots on and, eventually, becomes the idle, do nothing task that runs
* only when there is nothing else to run. The heap continues from there until the
* end of memory. See g_idle_topstack below.
*/
.globl g_idle_topstack
.type g_idle_topstack, object
g_idle_topstack:
.word HEAP_BASE
.size g_idle_topstack, .-g_idle_topstack
.end

1084
arch/arm/src/stm32/iar/stm32_vectors.S
View File

File diff suppressed because it is too large Load Diff

12
arch/arm/src/stm32/stm32_rcc.h
View File

@ -1,7 +1,7 @@
/************************************************************************************ /************************************************************************************
* arch/arm/src/stm32/stm32_rcc.h * arch/arm/src/stm32/stm32_rcc.h
* *
* Copyright (C) 2009, 2011-2014 Gregory Nutt. All rights reserved. * Copyright (C) 2009, 2011-2014, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.orgr> * Author: Gregory Nutt <gnutt@nuttx.orgr>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -80,14 +80,20 @@ extern "C"
* Public Data * Public Data
************************************************************************************/ ************************************************************************************/
/* This symbol references the Cortex-M3 vector table (as positioned by the linker /* This symbol references the Cortex-M3/4 vector table (as positioned by the linker
* script, ld.script or ld.script.dfu. The standard location for the vector table is * script, ld.script or ld.script.dfu. The standard location for the vector table is
* at the beginning of FLASH at address 0x0800:0000. If we are using the STMicro DFU * at the beginning of FLASH at address 0x0800:0000. If we are using the STMicro DFU
* bootloader, then the vector table will be offset to a different location in FLASH * bootloader, then the vector table will be offset to a different location in FLASH
* and we will need to set the NVIC vector location to this alternative location. * and we will need to set the NVIC vector location to this alternative location.
*/ */
extern uint32_t _vectors[]; /* See stm32_vectors.S */ #if defined(__ICCARM__)
/* _vectors replaced on __vector_table for IAR C-SPY Simulator */
extern uint32_t __vector_table[];
#else
extern uint32_t _vectors[];
#endif
/************************************************************************************ /************************************************************************************
* Inline Functions * Inline Functions

34
arch/arm/src/stm32/stm32_start.c
View File

@ -1,7 +1,7 @@
/**************************************************************************** /****************************************************************************
* arch/arm/src/stm32/stm32_start.c * arch/arm/src/stm32/stm32_start.c
* *
* Copyright (C) 2009, 2011-2017 Gregory Nutt. All rights reserved. * Copyright (C) 2009, 2011-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -58,6 +58,36 @@
#include "stm32_start.h" #include "stm32_start.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* .data is positioned first in the primary RAM followed immediately by .bss.
* The IDLE thread stack lies just after .bss and has size give by
* CONFIG_IDLETHREAD_STACKSIZE; The heap then begins just after the IDLE.
* ARM EABI requires 64 bit stack alignment.
*/
#define IDLE_STACKSIZE (CONFIG_IDLETHREAD_STACKSIZE & ~7)
#define IDLE_STACK ((uintptr_t)&_ebss + IDLE_STACKSIZE)
#define HEAP_BASE ((uintptr_t)&_ebss + IDLE_STACKSIZE)
/****************************************************************************
* Public Data
****************************************************************************/
/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
* linker script. _ebss lies at the end of the BSS region. The idle task
* stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.
* The IDLE thread is the thread that the system boots on and, eventually,
* becomes the IDLE, do nothing task that runs only when there is nothing
* else to run. The heap continues from there until the end of memory.
* g_idle_topstack is a read-only variable the provides this computed
* address.
*/
const uintptr_t g_idle_topstack = HEAP_BASE;
/**************************************************************************** /****************************************************************************
* Private Function prototypes * Private Function prototypes
****************************************************************************/ ****************************************************************************/
@ -122,7 +152,7 @@ void __start(void) __attribute__ ((no_instrument_function));
****************************************************************************/ ****************************************************************************/
#ifdef CONFIG_ARCH_FPU #ifdef CONFIG_ARCH_FPU
#if defined(CONFIG_ARMV7M_CMNVECTOR) && !defined(CONFIG_ARMV7M_LAZYFPU) #ifndef CONFIG_ARMV7M_LAZYFPU
static inline void stm32_fpuconfig(void) static inline void stm32_fpuconfig(void)
{ {

18
arch/arm/src/stm32/stm32_start.h
View File

@ -1,7 +1,7 @@
/************************************************************************************ /************************************************************************************
* arch/arm/src/stm32/stm32_start.h * arch/arm/src/stm32/stm32_start.h
* *
* Copyright (C) 2017 Gregory Nutt. All rights reserved. * Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -42,6 +42,22 @@
#include <nuttx/config.h> #include <nuttx/config.h>
/************************************************************************************
* Public Data
************************************************************************************/
/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
* linker script. _ebss lies at the end of the BSS region. The idle task
* stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.
* The IDLE thread is the thread that the system boots on and, eventually,
* becomes the IDLE, do nothing task that runs only when there is nothing
* else to run. The heap continues from there until the end of memory.
* g_idle_topstack is a read-only variable the provides this computed
* address.
*/
extern const uintptr_t g_idle_topstack;
/************************************************************************************ /************************************************************************************
* Public Function Prototypes * Public Function Prototypes
************************************************************************************/ ************************************************************************************/

6
arch/arm/src/stm32f7/Make.defs
View File

@ -60,14 +60,12 @@ endif
# Configuration-dependent common files # Configuration-dependent common files
ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_ASRCS += up_lazyexception.S CMN_ASRCS += up_lazyexception.S
else else
CMN_ASRCS += up_exception.S CMN_ASRCS += up_exception.S
endif endif
CMN_CSRCS += up_vectors.c CMN_CSRCS += up_vectors.c
endif
ifeq ($(CONFIG_ARMV7M_DCACHE),y) ifeq ($(CONFIG_ARMV7M_DCACHE),y)
CMN_CSRCS += arch_enable_dcache.c arch_disable_dcache.c CMN_CSRCS += arch_enable_dcache.c arch_disable_dcache.c
@ -80,11 +78,7 @@ endif
ifeq ($(CONFIG_ARCH_FPU),y) ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S CMN_ASRCS += up_fpu.S
ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y)
CMN_CSRCS += up_copyarmstate.c CMN_CSRCS += up_copyarmstate.c
else ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_CSRCS += up_copyarmstate.c
endif
endif endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y) ifeq ($(CONFIG_ARCH_RAMVECTORS),y)

2
arch/arm/src/stm32f7/stm32_start.c
View File

@ -142,7 +142,7 @@ void __start(void) __attribute__ ((no_instrument_function));
****************************************************************************/ ****************************************************************************/
#ifdef CONFIG_ARCH_FPU #ifdef CONFIG_ARCH_FPU
#if defined(CONFIG_ARMV7M_CMNVECTOR) && !defined(CONFIG_ARMV7M_LAZYFPU) #ifndef CONFIG_ARMV7M_LAZYFPU
static inline void stm32_fpuconfig(void) static inline void stm32_fpuconfig(void)
{ {

6
arch/arm/src/stm32h7/Make.defs
View File

@ -57,14 +57,12 @@ CMN_CSRCS += up_hardfault.c up_svcall.c up_vfork.c
# Configuration-dependent common files # Configuration-dependent common files
ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_ASRCS += up_lazyexception.S CMN_ASRCS += up_lazyexception.S
else else
CMN_ASRCS += up_exception.S CMN_ASRCS += up_exception.S
endif endif
CMN_CSRCS += up_vectors.c CMN_CSRCS += up_vectors.c
endif
ifeq ($(CONFIG_ARMV7M_DCACHE),y) ifeq ($(CONFIG_ARMV7M_DCACHE),y)
CMN_CSRCS += arch_enable_dcache.c arch_disable_dcache.c CMN_CSRCS += arch_enable_dcache.c arch_disable_dcache.c
@ -77,11 +75,7 @@ endif
ifeq ($(CONFIG_ARCH_FPU),y) ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S CMN_ASRCS += up_fpu.S
ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y)
CMN_CSRCS += up_copyarmstate.c CMN_CSRCS += up_copyarmstate.c
else ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_CSRCS += up_copyarmstate.c
endif
endif endif
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)

2
arch/arm/src/stm32h7/stm32_start.c
View File

@ -143,7 +143,7 @@ void __start(void) __attribute__ ((no_instrument_function));
****************************************************************************/ ****************************************************************************/
#ifdef CONFIG_ARCH_FPU #ifdef CONFIG_ARCH_FPU
#if defined(CONFIG_ARMV7M_CMNVECTOR) && !defined(CONFIG_ARMV7M_LAZYFPU) #ifndef CONFIG_ARMV7M_LAZYFPU
static inline void stm32_fpuconfig(void) static inline void stm32_fpuconfig(void)
{ {

6
arch/arm/src/stm32l4/Make.defs
View File

@ -62,22 +62,16 @@ ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
CMN_CSRCS += up_stackcheck.c CMN_CSRCS += up_stackcheck.c
endif endif
ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_ASRCS += up_lazyexception.S CMN_ASRCS += up_lazyexception.S
else else
CMN_ASRCS += up_exception.S CMN_ASRCS += up_exception.S
endif endif
CMN_CSRCS += up_vectors.c CMN_CSRCS += up_vectors.c
endif
ifeq ($(CONFIG_ARCH_FPU),y) ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S CMN_ASRCS += up_fpu.S
ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y)
CMN_CSRCS += up_copyarmstate.c CMN_CSRCS += up_copyarmstate.c
else ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_CSRCS += up_copyarmstate.c
endif
endif endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y) ifeq ($(CONFIG_ARCH_RAMVECTORS),y)

2
arch/arm/src/stm32l4/stm32l4_start.c
View File

@ -160,7 +160,7 @@ void __start(void) __attribute__ ((no_instrument_function));
****************************************************************************/ ****************************************************************************/
#ifdef CONFIG_ARCH_FPU #ifdef CONFIG_ARCH_FPU
#if defined(CONFIG_ARMV7M_CMNVECTOR) && !defined(CONFIG_ARMV7M_LAZYFPU) #ifndef CONFIG_ARMV7M_LAZYFPU
static inline void stm32l4_fpuconfig(void) static inline void stm32l4_fpuconfig(void)
{ {

2
arch/arm/src/tiva/Make.defs
View File

@ -52,14 +52,12 @@ ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CMN_CSRCS += up_idle.c CMN_CSRCS += up_idle.c
endif endif
ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_ASRCS += up_lazyexception.S CMN_ASRCS += up_lazyexception.S
else else
CMN_ASRCS += up_exception.S CMN_ASRCS += up_exception.S
endif endif
CMN_CSRCS += up_vectors.c CMN_CSRCS += up_vectors.c
endif
ifeq ($(CONFIG_ARCH_FPU),y) ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S CMN_ASRCS += up_fpu.S

10
arch/arm/src/xmc4/Make.defs
View File

@ -33,11 +33,7 @@
# #
############################################################################ ############################################################################
ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
HEAD_ASRC = HEAD_ASRC =
else
HEAD_ASRC = xmc4_vectors.S
endif
CMN_UASRCS = CMN_UASRCS =
CMN_UCSRCS = CMN_UCSRCS =
@ -58,14 +54,12 @@ ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
CMN_CSRCS += up_stackcheck.c CMN_CSRCS += up_stackcheck.c
endif endif
ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_ASRCS += up_lazyexception.S CMN_ASRCS += up_lazyexception.S
else else
CMN_ASRCS += up_exception.S CMN_ASRCS += up_exception.S
endif endif
CMN_CSRCS += up_vectors.c CMN_CSRCS += up_vectors.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y) ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c
@ -95,11 +89,7 @@ endif
ifeq ($(CONFIG_ARCH_FPU),y) ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S CMN_ASRCS += up_fpu.S
ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y)
CMN_CSRCS += up_copyarmstate.c CMN_CSRCS += up_copyarmstate.c
else ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_CSRCS += up_copyarmstate.c
endif
endif endif
ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y) ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y)

5
arch/arm/src/xmc4/xmc4_start.c
View File

@ -108,9 +108,8 @@ static void go_os_start(void *pv, unsigned int nbytes)
* g_idle_topstack is a read-only variable the provides this computed * g_idle_topstack is a read-only variable the provides this computed
* address. * address.
*/ */
#if defined(CONFIG_ARMV7M_CMNVECTOR)
const uintptr_t g_idle_topstack = HEAP_BASE; const uintptr_t g_idle_topstack = HEAP_BASE;
#endif
/**************************************************************************** /****************************************************************************
* Private Data * Private Data
@ -155,7 +154,7 @@ void __start(void) __attribute__ ((no_instrument_function));
****************************************************************************/ ****************************************************************************/
#ifdef CONFIG_ARCH_FPU #ifdef CONFIG_ARCH_FPU
#if defined(CONFIG_ARMV7M_CMNVECTOR) && !defined(CONFIG_ARMV7M_LAZYFPU) #ifndef CONFIG_ARMV7M_LAZYFPU
static inline void xmc4_fpu_config(void) static inline void xmc4_fpu_config(void)
{ {

42
configs/bambino-200e/README.txt
View File

@ -85,39 +85,31 @@ FPU Configuration Options
------------------------- -------------------------
There are two version of the FPU support built into the most NuttX Cortex-M4 There are two version of the FPU support built into the most NuttX Cortex-M4
ports. The current LPC43xx port support only one of these options, the "Non- ports.
Lazy Floating Point Register Save". As a consequence, CONFIG_ARMV7M_CMNVECTOR
must be defined in *all* LPC43xx configuration files.
1. Lazy Floating Point Register Save. 1. Non-Lazy Floating Point Register Save
This is an untested implementation that saves and restores FPU registers In this configuration floating point register save and restore is
only on context switches. This means: (1) floating point registers are implemented on interrupt entry and return, respectively. In this
not stored on each context switch and, hence, possibly better interrupt case, you may use floating point operations for interrupt handling
logic if necessary. This FPU behavior logic is enabled by default
with:
CONFIG_ARCH_FPU=y
2. Lazy Floating Point Register Save.
An alternative mplementation only saves and restores FPU registers only
on context switches. This means: (1) floating point registers are not
stored on each context switch and, hence, possibly better interrupt
performance. But, (2) since floating point registers are not saved, performance. But, (2) since floating point registers are not saved,
you cannot use floating point operations within interrupt handlers. you cannot use floating point operations within interrupt handlers.
This logic can be enabled by simply adding the following to your .config This logic can be enabled by simply adding the following to your .config
file: file:
CONFIG_ARCH_FPU=y CONFIG_ARCH_FPU=y
CONFIG_ARMV7M_LAZYFPU=y
2. Non-Lazy Floating Point Register Save
Mike Smith has contributed an extensive re-write of the ARMv7-M exception
handling logic. This includes verified support for the FPU. These changes
have not yet been incorporated into the mainline and are still considered
experimental. These FPU logic can be enabled with:
CONFIG_ARCH_FPU=y
CONFIG_ARMV7M_CMNVECTOR=y
You will probably also changes to the ld.script in if this option is selected.
This should work:
-ENTRY(_stext)
+ENTRY(__start) /* Treat __start as the anchor for dead code stripping */
+EXTERN(_vectors) /* Force the vectors to be included in the output */
CFLAGS CFLAGS
------ ------

3
configs/bambino-200e/src/lpc43_ostest.c
View File

@ -60,8 +60,7 @@
#undef HAVE_FPU #undef HAVE_FPU
#if defined(CONFIG_ARCH_FPU) && defined(CONFIG_EXAMPLES_OSTEST_FPUSIZE) && \ #if defined(CONFIG_ARCH_FPU) && defined(CONFIG_EXAMPLES_OSTEST_FPUSIZE) && \
defined(CONFIG_SCHED_WAITPID) && !defined(CONFIG_DISABLE_SIGNALS) && \ defined(CONFIG_SCHED_WAITPID) && !defined(CONFIG_DISABLE_SIGNALS)
!defined(CONFIG_ARMV7M_CMNVECTOR)
# define HAVE_FPU 1 # define HAVE_FPU 1
#endif #endif

7
configs/clicker2-stm32/knsh/defconfig
View File

@ -1,19 +1,18 @@
# CONFIG_NSH_CMDOPT_DF_H is not set CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD_CLICKER2_STM32=y
CONFIG_ARCH_BOARD="clicker2-stm32" CONFIG_ARCH_BOARD="clicker2-stm32"
CONFIG_ARCH_BOARD_CLICKER2_STM32=y
CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F407VG=y
CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_IRQBUTTONS=y
CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm"
CONFIG_ARM_MPU=y CONFIG_ARM_MPU=y
CONFIG_BOARD_INITIALIZE=y CONFIG_BOARD_INITIALIZE=y
CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BOARD_LOOPSPERMSEC=16717
CONFIG_BUILD_PROTECTED=y CONFIG_BUILD_PROTECTED=y
CONFIG_DISABLE_POLL=y CONFIG_DISABLE_POLL=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_EXAMPLES_NSH=y CONFIG_EXAMPLES_NSH=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_FS_PROCFS=y CONFIG_FS_PROCFS=y
CONFIG_FS_WRITABLE=y CONFIG_FS_WRITABLE=y
CONFIG_HAVE_CXX=y CONFIG_HAVE_CXX=y

40
configs/clicker2-stm32/mrf24j40-6lowpan/defconfig
View File

@ -2,43 +2,43 @@
# CONFIG_NET_ETHERNET is not set # CONFIG_NET_ETHERNET is not set
# CONFIG_NET_IPv4 is not set # CONFIG_NET_IPv4 is not set
# CONFIG_NSH_DISABLE_TELNETD is not set # CONFIG_NSH_DISABLE_TELNETD is not set
CONFIG_ARCH_BOARD_CLICKER2_STM32=y CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="clicker2-stm32" CONFIG_ARCH_BOARD="clicker2-stm32"
CONFIG_ARCH_BOARD_CLICKER2_STM32=y
CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F407VG=y
CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_IRQBUTTONS=y
CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm" CONFIG_BOARDCTL_USBDEVCTRL=y
CONFIG_BOARD_INITIALIZE=y CONFIG_BOARD_INITIALIZE=y
CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BOARD_LOOPSPERMSEC=16717
CONFIG_BOARDCTL_USBDEVCTRL=y
CONFIG_BUILTIN=y CONFIG_BUILTIN=y
CONFIG_CDCACM=y
CONFIG_CDCACM_CONSOLE=y CONFIG_CDCACM_CONSOLE=y
CONFIG_CDCACM_RXBUFSIZE=256 CONFIG_CDCACM_RXBUFSIZE=256
CONFIG_CDCACM_TXBUFSIZE=256 CONFIG_CDCACM_TXBUFSIZE=256
CONFIG_CDCACM=y
CONFIG_DRIVERS_IEEE802154=y CONFIG_DRIVERS_IEEE802154=y
CONFIG_DRIVERS_WIRELESS=y CONFIG_DRIVERS_WIRELESS=y
CONFIG_EXAMPLES_NETTEST=y
CONFIG_EXAMPLES_NETTEST_DEVNAME="wpan0" CONFIG_EXAMPLES_NETTEST_DEVNAME="wpan0"
CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=61616
CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_1=0xfe80 CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_1=0xfe80
CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_6=0x00ff CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_6=0x00ff
CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_7=0xfe00 CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_7=0xfe00
CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_8=0x0800 CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_8=0x0800
CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=61616
CONFIG_EXAMPLES_NETTEST_TARGET2=y CONFIG_EXAMPLES_NETTEST_TARGET2=y
CONFIG_EXAMPLES_NETTEST=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_EXAMPLES_NSH=y CONFIG_EXAMPLES_NSH=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_EXAMPLES_UDP=y
CONFIG_EXAMPLES_UDP_CLIENT_PORTNO=61617 CONFIG_EXAMPLES_UDP_CLIENT_PORTNO=61617
CONFIG_EXAMPLES_UDP_DEVNAME="wpan0" CONFIG_EXAMPLES_UDP_DEVNAME="wpan0"
CONFIG_EXAMPLES_UDP_SERVER_PORTNO=61616
CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_1=0xfe80 CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_1=0xfe80
CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_6=0x00ff CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_6=0x00ff
CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_7=0xfe00 CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_7=0xfe00
CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_8=0x0d00 CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_8=0x0d00
CONFIG_EXAMPLES_UDP_SERVER_PORTNO=61616
CONFIG_EXAMPLES_UDP_TARGET2=y CONFIG_EXAMPLES_UDP_TARGET2=y
CONFIG_EXAMPLES_UDP=y
CONFIG_FAT_LCNAMES=y CONFIG_FAT_LCNAMES=y
CONFIG_FAT_LFN=y CONFIG_FAT_LFN=y
CONFIG_FS_FAT=y CONFIG_FS_FAT=y
@ -57,22 +57,22 @@ CONFIG_IOB_NCHAINS=16
CONFIG_MAC802154_NTXDESC=32 CONFIG_MAC802154_NTXDESC=32
CONFIG_MAX_TASKS=16 CONFIG_MAX_TASKS=16
CONFIG_MAX_WDOGPARMS=2 CONFIG_MAX_WDOGPARMS=2
CONFIG_NET=y
CONFIG_NETDEVICES=y
CONFIG_NETDEV_LATEINIT=y
CONFIG_NETDEV_STATISTICS=y
CONFIG_NETDEV_WIRELESS_IOCTL=y
CONFIG_NETUTILS_TELNETD=y
CONFIG_NET_6LOWPAN=y CONFIG_NET_6LOWPAN=y
CONFIG_NET_BROADCAST=y CONFIG_NET_BROADCAST=y
CONFIG_NET_HOSTNAME="MRF24J40" CONFIG_NET_HOSTNAME="MRF24J40"
CONFIG_NET_IPv6=y CONFIG_NET_IPv6=y
CONFIG_NET_SOCKOPTS=y CONFIG_NET_SOCKOPTS=y
CONFIG_NET_STATISTICS=y CONFIG_NET_STATISTICS=y
CONFIG_NET_TCP_WRITE_BUFFERS=y
CONFIG_NET_TCP=y CONFIG_NET_TCP=y
CONFIG_NET_TCPBACKLOG=y CONFIG_NET_TCPBACKLOG=y
CONFIG_NET_TCP_WRITE_BUFFERS=y
CONFIG_NET_UDP=y CONFIG_NET_UDP=y
CONFIG_NET=y
CONFIG_NETDEV_LATEINIT=y
CONFIG_NETDEV_STATISTICS=y
CONFIG_NETDEV_WIRELESS_IOCTL=y
CONFIG_NETDEVICES=y
CONFIG_NETUTILS_TELNETD=y
CONFIG_NFILE_DESCRIPTORS=8 CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8 CONFIG_NFILE_STREAMS=8
CONFIG_NSH_ARCHINIT=y CONFIG_NSH_ARCHINIT=y
@ -88,11 +88,11 @@ CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_MQ_MSGS=4 CONFIG_PREALLOC_MQ_MSGS=4
CONFIG_PREALLOC_TIMERS=4 CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=16 CONFIG_PREALLOC_WDOGS=16
CONFIG_RAM_SIZE=131072 CONFIG_RAMLOG=y
CONFIG_RAM_START=0x20000000
CONFIG_RAMLOG_BUFSIZE=8192 CONFIG_RAMLOG_BUFSIZE=8192
CONFIG_RAMLOG_SYSLOG=y CONFIG_RAMLOG_SYSLOG=y
CONFIG_RAMLOG=y CONFIG_RAM_SIZE=131072
CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200 CONFIG_RR_INTERVAL=200
CONFIG_SCHED_HPWORK=y CONFIG_SCHED_HPWORK=y
@ -113,5 +113,5 @@ CONFIG_SYSTEM_TELNET_CLIENT=y
CONFIG_TASK_NAME_SIZE=32 CONFIG_TASK_NAME_SIZE=32
CONFIG_USBDEV=y CONFIG_USBDEV=y
CONFIG_USER_ENTRYPOINT="nsh_main" CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_WIRELESS_IEEE802154=y
CONFIG_WIRELESS=y CONFIG_WIRELESS=y
CONFIG_WIRELESS_IEEE802154=y

32
configs/clicker2-stm32/mrf24j40-starhub/defconfig
View File

@ -2,26 +2,26 @@
# CONFIG_NET_ETHERNET is not set # CONFIG_NET_ETHERNET is not set
# CONFIG_NET_IPv4 is not set # CONFIG_NET_IPv4 is not set
# CONFIG_NSH_DISABLE_TELNETD is not set # CONFIG_NSH_DISABLE_TELNETD is not set
CONFIG_ARCH_BOARD_CLICKER2_STM32=y CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="clicker2-stm32" CONFIG_ARCH_BOARD="clicker2-stm32"
CONFIG_ARCH_BOARD_CLICKER2_STM32=y
CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F407VG=y
CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_IRQBUTTONS=y
CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm" CONFIG_BOARDCTL_USBDEVCTRL=y
CONFIG_BOARD_INITIALIZE=y CONFIG_BOARD_INITIALIZE=y
CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BOARD_LOOPSPERMSEC=16717
CONFIG_BOARDCTL_USBDEVCTRL=y
CONFIG_BUILTIN=y CONFIG_BUILTIN=y
CONFIG_CDCACM=y
CONFIG_CDCACM_CONSOLE=y CONFIG_CDCACM_CONSOLE=y
CONFIG_CDCACM_RXBUFSIZE=256 CONFIG_CDCACM_RXBUFSIZE=256
CONFIG_CDCACM_TXBUFSIZE=256 CONFIG_CDCACM_TXBUFSIZE=256
CONFIG_CDCACM=y
CONFIG_DRIVERS_IEEE802154=y CONFIG_DRIVERS_IEEE802154=y
CONFIG_DRIVERS_WIRELESS=y CONFIG_DRIVERS_WIRELESS=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_EXAMPLES_NSH=y CONFIG_EXAMPLES_NSH=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_FAT_LCNAMES=y CONFIG_FAT_LCNAMES=y
CONFIG_FAT_LFN=y CONFIG_FAT_LFN=y
CONFIG_FS_FAT=y CONFIG_FS_FAT=y
@ -40,6 +40,12 @@ CONFIG_IOB_NCHAINS=16
CONFIG_MAC802154_NTXDESC=32 CONFIG_MAC802154_NTXDESC=32
CONFIG_MAX_TASKS=16 CONFIG_MAX_TASKS=16
CONFIG_MAX_WDOGPARMS=2 CONFIG_MAX_WDOGPARMS=2
CONFIG_NET=y
CONFIG_NETDEVICES=y
CONFIG_NETDEV_LATEINIT=y
CONFIG_NETDEV_STATISTICS=y
CONFIG_NETDEV_TELNET=y
CONFIG_NETDEV_WIRELESS_IOCTL=y
CONFIG_NET_6LOWPAN=y CONFIG_NET_6LOWPAN=y
CONFIG_NET_BROADCAST=y CONFIG_NET_BROADCAST=y
CONFIG_NET_HOSTNAME="MRF24J40" CONFIG_NET_HOSTNAME="MRF24J40"
@ -48,16 +54,10 @@ CONFIG_NET_SOCKOPTS=y
CONFIG_NET_STAR=y CONFIG_NET_STAR=y
CONFIG_NET_STARHUB=y CONFIG_NET_STARHUB=y
CONFIG_NET_STATISTICS=y CONFIG_NET_STATISTICS=y
CONFIG_NET_TCP_WRITE_BUFFERS=y
CONFIG_NET_TCP=y CONFIG_NET_TCP=y
CONFIG_NET_TCPBACKLOG=y CONFIG_NET_TCPBACKLOG=y
CONFIG_NET_TCP_WRITE_BUFFERS=y
CONFIG_NET_UDP=y CONFIG_NET_UDP=y
CONFIG_NET=y
CONFIG_NETDEV_LATEINIT=y
CONFIG_NETDEV_STATISTICS=y
CONFIG_NETDEV_TELNET=y
CONFIG_NETDEV_WIRELESS_IOCTL=y
CONFIG_NETDEVICES=y
CONFIG_NFILE_DESCRIPTORS=8 CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8 CONFIG_NFILE_STREAMS=8
CONFIG_NSH_ARCHINIT=y CONFIG_NSH_ARCHINIT=y
@ -73,11 +73,11 @@ CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_MQ_MSGS=4 CONFIG_PREALLOC_MQ_MSGS=4
CONFIG_PREALLOC_TIMERS=4 CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=16 CONFIG_PREALLOC_WDOGS=16
CONFIG_RAM_SIZE=131072 CONFIG_RAMLOG=y
CONFIG_RAM_START=0x20000000
CONFIG_RAMLOG_BUFSIZE=8192 CONFIG_RAMLOG_BUFSIZE=8192
CONFIG_RAMLOG_SYSLOG=y CONFIG_RAMLOG_SYSLOG=y
CONFIG_RAMLOG=y CONFIG_RAM_SIZE=131072
CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200 CONFIG_RR_INTERVAL=200
CONFIG_SCHED_HPWORK=y CONFIG_SCHED_HPWORK=y
@ -98,5 +98,5 @@ CONFIG_SYSTEM_TELNET_CLIENT=y
CONFIG_TASK_NAME_SIZE=32 CONFIG_TASK_NAME_SIZE=32
CONFIG_USBDEV=y CONFIG_USBDEV=y
CONFIG_USER_ENTRYPOINT="nsh_main" CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_WIRELESS_IEEE802154=y
CONFIG_WIRELESS=y CONFIG_WIRELESS=y
CONFIG_WIRELESS_IEEE802154=y

42
configs/clicker2-stm32/mrf24j40-starpoint/defconfig
View File

@ -2,43 +2,43 @@
# CONFIG_NET_ETHERNET is not set # CONFIG_NET_ETHERNET is not set
# CONFIG_NET_IPv4 is not set # CONFIG_NET_IPv4 is not set
# CONFIG_NSH_DISABLE_TELNETD is not set # CONFIG_NSH_DISABLE_TELNETD is not set
CONFIG_ARCH_BOARD_CLICKER2_STM32=y CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="clicker2-stm32" CONFIG_ARCH_BOARD="clicker2-stm32"
CONFIG_ARCH_BOARD_CLICKER2_STM32=y
CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F407VG=y
CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_IRQBUTTONS=y
CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm" CONFIG_BOARDCTL_USBDEVCTRL=y
CONFIG_BOARD_INITIALIZE=y CONFIG_BOARD_INITIALIZE=y
CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BOARD_LOOPSPERMSEC=16717
CONFIG_BOARDCTL_USBDEVCTRL=y
CONFIG_BUILTIN=y CONFIG_BUILTIN=y
CONFIG_CDCACM=y
CONFIG_CDCACM_CONSOLE=y CONFIG_CDCACM_CONSOLE=y
CONFIG_CDCACM_RXBUFSIZE=256 CONFIG_CDCACM_RXBUFSIZE=256
CONFIG_CDCACM_TXBUFSIZE=256 CONFIG_CDCACM_TXBUFSIZE=256
CONFIG_CDCACM=y
CONFIG_DRIVERS_IEEE802154=y CONFIG_DRIVERS_IEEE802154=y
CONFIG_DRIVERS_WIRELESS=y CONFIG_DRIVERS_WIRELESS=y
CONFIG_EXAMPLES_NETTEST=y
CONFIG_EXAMPLES_NETTEST_DEVNAME="wpan0" CONFIG_EXAMPLES_NETTEST_DEVNAME="wpan0"
CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=61616
CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_1=0xfe80 CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_1=0xfe80
CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_6=0x00ff CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_6=0x00ff
CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_7=0xfe00 CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_7=0xfe00
CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_8=0x0800 CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_8=0x0800
CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=61616
CONFIG_EXAMPLES_NETTEST_TARGET2=y CONFIG_EXAMPLES_NETTEST_TARGET2=y
CONFIG_EXAMPLES_NETTEST=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_EXAMPLES_NSH=y CONFIG_EXAMPLES_NSH=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_EXAMPLES_UDP=y
CONFIG_EXAMPLES_UDP_CLIENT_PORTNO=61617 CONFIG_EXAMPLES_UDP_CLIENT_PORTNO=61617
CONFIG_EXAMPLES_UDP_DEVNAME="wpan0" CONFIG_EXAMPLES_UDP_DEVNAME="wpan0"
CONFIG_EXAMPLES_UDP_SERVER_PORTNO=61616
CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_1=0xfe80 CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_1=0xfe80
CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_6=0x00ff CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_6=0x00ff
CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_7=0xfe00 CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_7=0xfe00
CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_8=0x0d00 CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_8=0x0d00
CONFIG_EXAMPLES_UDP_SERVER_PORTNO=61616
CONFIG_EXAMPLES_UDP_TARGET2=y CONFIG_EXAMPLES_UDP_TARGET2=y
CONFIG_EXAMPLES_UDP=y
CONFIG_FAT_LCNAMES=y CONFIG_FAT_LCNAMES=y
CONFIG_FAT_LFN=y CONFIG_FAT_LFN=y
CONFIG_FS_FAT=y CONFIG_FS_FAT=y
@ -57,6 +57,13 @@ CONFIG_IOB_NCHAINS=16
CONFIG_MAC802154_NTXDESC=32 CONFIG_MAC802154_NTXDESC=32
CONFIG_MAX_TASKS=16 CONFIG_MAX_TASKS=16
CONFIG_MAX_WDOGPARMS=2 CONFIG_MAX_WDOGPARMS=2
CONFIG_NET=y
CONFIG_NETDEVICES=y
CONFIG_NETDEV_LATEINIT=y
CONFIG_NETDEV_STATISTICS=y
CONFIG_NETDEV_WIRELESS_IOCTL=y
CONFIG_NETUTILS_TELNETC=y
CONFIG_NETUTILS_TELNETD=y
CONFIG_NET_6LOWPAN=y CONFIG_NET_6LOWPAN=y
CONFIG_NET_BROADCAST=y CONFIG_NET_BROADCAST=y
CONFIG_NET_HOSTNAME="MRF24J40" CONFIG_NET_HOSTNAME="MRF24J40"
@ -64,17 +71,10 @@ CONFIG_NET_IPv6=y
CONFIG_NET_SOCKOPTS=y CONFIG_NET_SOCKOPTS=y
CONFIG_NET_STAR=y CONFIG_NET_STAR=y
CONFIG_NET_STATISTICS=y CONFIG_NET_STATISTICS=y
CONFIG_NET_TCP_WRITE_BUFFERS=y
CONFIG_NET_TCP=y CONFIG_NET_TCP=y
CONFIG_NET_TCPBACKLOG=y CONFIG_NET_TCPBACKLOG=y
CONFIG_NET_TCP_WRITE_BUFFERS=y
CONFIG_NET_UDP=y CONFIG_NET_UDP=y
CONFIG_NET=y
CONFIG_NETDEV_LATEINIT=y
CONFIG_NETDEV_STATISTICS=y
CONFIG_NETDEV_WIRELESS_IOCTL=y
CONFIG_NETDEVICES=y
CONFIG_NETUTILS_TELNETC=y
CONFIG_NETUTILS_TELNETD=y
CONFIG_NFILE_DESCRIPTORS=8 CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8 CONFIG_NFILE_STREAMS=8
CONFIG_NSH_ARCHINIT=y CONFIG_NSH_ARCHINIT=y
@ -90,11 +90,11 @@ CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_MQ_MSGS=4 CONFIG_PREALLOC_MQ_MSGS=4
CONFIG_PREALLOC_TIMERS=4 CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=16 CONFIG_PREALLOC_WDOGS=16
CONFIG_RAM_SIZE=131072 CONFIG_RAMLOG=y
CONFIG_RAM_START=0x20000000
CONFIG_RAMLOG_BUFSIZE=8192 CONFIG_RAMLOG_BUFSIZE=8192
CONFIG_RAMLOG_SYSLOG=y CONFIG_RAMLOG_SYSLOG=y
CONFIG_RAMLOG=y CONFIG_RAM_SIZE=131072
CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200 CONFIG_RR_INTERVAL=200
CONFIG_SCHED_HPWORK=y CONFIG_SCHED_HPWORK=y
@ -114,5 +114,5 @@ CONFIG_STM32_PWR=y
CONFIG_TASK_NAME_SIZE=32 CONFIG_TASK_NAME_SIZE=32
CONFIG_USBDEV=y CONFIG_USBDEV=y
CONFIG_USER_ENTRYPOINT="nsh_main" CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_WIRELESS_IEEE802154=y
CONFIG_WIRELESS=y CONFIG_WIRELESS=y
CONFIG_WIRELESS_IEEE802154=y

7
configs/clicker2-stm32/nsh/defconfig
View File

@ -1,18 +1,17 @@
# CONFIG_NSH_CMDOPT_DF_H is not set CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD_CLICKER2_STM32=y
CONFIG_ARCH_BOARD="clicker2-stm32" CONFIG_ARCH_BOARD="clicker2-stm32"
CONFIG_ARCH_BOARD_CLICKER2_STM32=y
CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F407VG=y
CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_IRQBUTTONS=y
CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm"
CONFIG_BOARD_INITIALIZE=y CONFIG_BOARD_INITIALIZE=y
CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BOARD_LOOPSPERMSEC=16717
CONFIG_BUILTIN=y CONFIG_BUILTIN=y
CONFIG_DISABLE_POLL=y CONFIG_DISABLE_POLL=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_EXAMPLES_NSH=y CONFIG_EXAMPLES_NSH=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_FS_PROCFS=y CONFIG_FS_PROCFS=y
CONFIG_FS_WRITABLE=y CONFIG_FS_WRITABLE=y
CONFIG_HAVE_CXX=y CONFIG_HAVE_CXX=y

1
configs/clicker2-stm32/scripts/flash.ld
View File

@ -52,6 +52,7 @@ MEMORY
} }
OUTPUT_ARCH(arm) OUTPUT_ARCH(arm)
EXTERN(_vectors)
ENTRY(_stext) ENTRY(_stext)
SECTIONS SECTIONS
{ {

1
configs/clicker2-stm32/scripts/kernel-space.ld
View File

@ -38,6 +38,7 @@
*/ */
OUTPUT_ARCH(arm) OUTPUT_ARCH(arm)
EXTERN(_vectors)
ENTRY(_stext) ENTRY(_stext)
SECTIONS SECTIONS
{ {

11
configs/clicker2-stm32/usbnsh/defconfig
View File

@ -1,24 +1,23 @@
# CONFIG_DEV_CONSOLE is not set # CONFIG_DEV_CONSOLE is not set
# CONFIG_NSH_CMDOPT_DF_H is not set CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD_CLICKER2_STM32=y
CONFIG_ARCH_BOARD="clicker2-stm32" CONFIG_ARCH_BOARD="clicker2-stm32"
CONFIG_ARCH_BOARD_CLICKER2_STM32=y
CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F407VG=y
CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_IRQBUTTONS=y
CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm" CONFIG_BOARDCTL_USBDEVCTRL=y
CONFIG_BOARD_INITIALIZE=y CONFIG_BOARD_INITIALIZE=y
CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BOARD_LOOPSPERMSEC=16717
CONFIG_BOARDCTL_USBDEVCTRL=y
CONFIG_BUILTIN=y CONFIG_BUILTIN=y
CONFIG_CDCACM=y
CONFIG_CDCACM_CONSOLE=y CONFIG_CDCACM_CONSOLE=y
CONFIG_CDCACM_RXBUFSIZE=256 CONFIG_CDCACM_RXBUFSIZE=256
CONFIG_CDCACM_TXBUFSIZE=256 CONFIG_CDCACM_TXBUFSIZE=256
CONFIG_CDCACM=y
CONFIG_DISABLE_POLL=y CONFIG_DISABLE_POLL=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_EXAMPLES_NSH=y CONFIG_EXAMPLES_NSH=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_FAT_LCNAMES=y CONFIG_FAT_LCNAMES=y
CONFIG_FAT_LFN=y CONFIG_FAT_LFN=y
CONFIG_FS_FAT=y CONFIG_FS_FAT=y

45
configs/clicker2-stm32/xbee-6lowpan/defconfig
View File

@ -1,23 +1,27 @@
# CONFIG_DEV_CONSOLE is not set
# CONFIG_NET_ETHERNET is not set
# CONFIG_NET_IPv4 is not set
# CONFIG_NSH_DISABLE_TELNETD is not set
CONFIG_ARCH="arm" CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="clicker2-stm32" CONFIG_ARCH_BOARD="clicker2-stm32"
CONFIG_ARCH_BOARD_CLICKER2_STM32=y CONFIG_ARCH_BOARD_CLICKER2_STM32=y
CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP_STM32F407VG=y
CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32F407VG=y
CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_IRQBUTTONS=y
CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_STACKDUMP=y
CONFIG_BOARDCTL_USBDEVCTRL=y CONFIG_BOARDCTL_USBDEVCTRL=y
CONFIG_BOARD_INITIALIZE=y CONFIG_BOARD_INITIALIZE=y
CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BOARD_LOOPSPERMSEC=16717
CONFIG_BUILTIN=y CONFIG_BUILTIN=y
CONFIG_CDCACM=y
CONFIG_CDCACM_CONSOLE=y CONFIG_CDCACM_CONSOLE=y
CONFIG_CDCACM_RXBUFSIZE=256 CONFIG_CDCACM_RXBUFSIZE=256
CONFIG_CDCACM_TXBUFSIZE=256 CONFIG_CDCACM_TXBUFSIZE=256
CONFIG_CDCACM=y
CONFIG_CLICKER2_STM32_MB1_XBEE=y CONFIG_CLICKER2_STM32_MB1_XBEE=y
# CONFIG_DEV_CONSOLE is not set
CONFIG_DRIVERS_IEEE802154=y CONFIG_DRIVERS_IEEE802154=y
CONFIG_DRIVERS_WIRELESS=y CONFIG_DRIVERS_WIRELESS=y
CONFIG_EXAMPLES_NETTEST=y
CONFIG_EXAMPLES_NETTEST_DEVNAME="wpan0" CONFIG_EXAMPLES_NETTEST_DEVNAME="wpan0"
CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_1=0xfe80 CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_1=0xfe80
CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_6=0x00ff CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_6=0x00ff
@ -25,9 +29,9 @@ CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_7=0xfe00
CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_8=0x0800 CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_8=0x0800
CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=61616 CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=61616
CONFIG_EXAMPLES_NETTEST_TARGET2=y CONFIG_EXAMPLES_NETTEST_TARGET2=y
CONFIG_EXAMPLES_NETTEST=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_EXAMPLES_NSH=y CONFIG_EXAMPLES_NSH=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_EXAMPLES_UDP=y
CONFIG_EXAMPLES_UDP_CLIENT_PORTNO=61617 CONFIG_EXAMPLES_UDP_CLIENT_PORTNO=61617
CONFIG_EXAMPLES_UDP_DEVNAME="wpan0" CONFIG_EXAMPLES_UDP_DEVNAME="wpan0"
CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_1=0xfe80 CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_1=0xfe80
@ -36,52 +40,41 @@ CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_7=0xfe00
CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_8=0x0d00 CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_8=0x0d00
CONFIG_EXAMPLES_UDP_SERVER_PORTNO=61616 CONFIG_EXAMPLES_UDP_SERVER_PORTNO=61616
CONFIG_EXAMPLES_UDP_TARGET2=y CONFIG_EXAMPLES_UDP_TARGET2=y
CONFIG_EXAMPLES_UDP=y
CONFIG_FAT_LCNAMES=y CONFIG_FAT_LCNAMES=y
CONFIG_FAT_LFN=y CONFIG_FAT_LFN=y
CONFIG_FS_FAT=y CONFIG_FS_FAT=y
CONFIG_FS_PROCFS=y CONFIG_FS_PROCFS=y
CONFIG_HAVE_CXXINITIALIZE=y
CONFIG_HAVE_CXX=y CONFIG_HAVE_CXX=y
CONFIG_HAVE_CXXINITIALIZE=y
CONFIG_IEEE802154_I8SAK=y CONFIG_IEEE802154_I8SAK=y
CONFIG_IEEE802154_IND_PREALLOC=32
CONFIG_IEEE802154_MACDEV=y
CONFIG_IEEE802154_NETDEV=y
CONFIG_IEEE802154_XBEE=y CONFIG_IEEE802154_XBEE=y
CONFIG_INTELHEX_BINARY=y CONFIG_INTELHEX_BINARY=y
CONFIG_IOB_BUFSIZE=128 CONFIG_IOB_BUFSIZE=128
CONFIG_IOB_NBUFFERS=32 CONFIG_IOB_NBUFFERS=32
CONFIG_IOB_NCHAINS=16 CONFIG_IOB_NCHAINS=16
CONFIG_MAC802154_NNOTIF=48
CONFIG_MAC802154_NTXDESC=32
CONFIG_MAX_TASKS=16 CONFIG_MAX_TASKS=16
CONFIG_MAX_WDOGPARMS=2 CONFIG_MAX_WDOGPARMS=2
CONFIG_NET_6LOWPAN=y CONFIG_NET=y
CONFIG_NET_BROADCAST=y
CONFIG_NETDEVICES=y CONFIG_NETDEVICES=y
CONFIG_NETDEV_LATEINIT=y CONFIG_NETDEV_LATEINIT=y
CONFIG_NETDEV_STATISTICS=y
CONFIG_NETDEV_WIRELESS_IOCTL=y CONFIG_NETDEV_WIRELESS_IOCTL=y
# CONFIG_NET_ETHERNET is not set CONFIG_NETUTILS_TELNETD=y
CONFIG_NET_6LOWPAN=y
CONFIG_NET_BROADCAST=y
CONFIG_NET_HOSTNAME="XBee" CONFIG_NET_HOSTNAME="XBee"
# CONFIG_NET_IPv4 is not set
CONFIG_NET_IPv6=y CONFIG_NET_IPv6=y
CONFIG_NET_SOCKOPTS=y CONFIG_NET_SOCKOPTS=y
CONFIG_NET_STATISTICS=y CONFIG_NET_STATISTICS=y
CONFIG_NET_TCP=y
CONFIG_NET_TCPBACKLOG=y CONFIG_NET_TCPBACKLOG=y
CONFIG_NET_TCP_WRITE_BUFFERS=y CONFIG_NET_TCP_WRITE_BUFFERS=y
CONFIG_NET_TCP=y
CONFIG_NET_UDP=y CONFIG_NET_UDP=y
CONFIG_NETUTILS_TELNETD=y
CONFIG_NET=y
CONFIG_NFILE_DESCRIPTORS=8 CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8 CONFIG_NFILE_STREAMS=8
CONFIG_NSH_ARCHINIT=y CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_BUILTIN_APPS=y
# CONFIG_NSH_CMDOPT_DF_H is not set
CONFIG_NSH_DISABLE_GET=y CONFIG_NSH_DISABLE_GET=y
CONFIG_NSH_DISABLE_PUT=y CONFIG_NSH_DISABLE_PUT=y
# CONFIG_NSH_DISABLE_TELNETD is not set
CONFIG_NSH_DISABLE_WGET=y CONFIG_NSH_DISABLE_WGET=y
CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64 CONFIG_NSH_LINELEN=64
@ -91,18 +84,18 @@ CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_MQ_MSGS=4 CONFIG_PREALLOC_MQ_MSGS=4
CONFIG_PREALLOC_TIMERS=4 CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=16 CONFIG_PREALLOC_WDOGS=16
CONFIG_RAMLOG=y
CONFIG_RAMLOG_BUFSIZE=8192 CONFIG_RAMLOG_BUFSIZE=8192
CONFIG_RAMLOG_SYSLOG=y CONFIG_RAMLOG_SYSLOG=y
CONFIG_RAMLOG=y
CONFIG_RAM_SIZE=131072 CONFIG_RAM_SIZE=131072
CONFIG_RAM_START=0x20000000 CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200 CONFIG_RR_INTERVAL=200
CONFIG_SCHED_HPWORK=y
CONFIG_SCHED_HPWORKPERIOD=50000 CONFIG_SCHED_HPWORKPERIOD=50000
CONFIG_SCHED_HPWORKPRIORITY=192 CONFIG_SCHED_HPWORKPRIORITY=192
CONFIG_SCHED_HPWORK=y
CONFIG_SCHED_LPWORKPRIORITY=160
CONFIG_SCHED_LPWORK=y CONFIG_SCHED_LPWORK=y
CONFIG_SCHED_LPWORKPRIORITY=160
CONFIG_SCHED_WAITPID=y CONFIG_SCHED_WAITPID=y
CONFIG_SDCLONE_DISABLE=y CONFIG_SDCLONE_DISABLE=y
CONFIG_STANDARD_SERIAL=y CONFIG_STANDARD_SERIAL=y
@ -116,5 +109,5 @@ CONFIG_SYSTEM_TELNET_CLIENT=y
CONFIG_TASK_NAME_SIZE=32 CONFIG_TASK_NAME_SIZE=32
CONFIG_USBDEV=y CONFIG_USBDEV=y
CONFIG_USER_ENTRYPOINT="nsh_main" CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_WIRELESS_IEEE802154=y
CONFIG_WIRELESS=y CONFIG_WIRELESS=y
CONFIG_WIRELESS_IEEE802154=y

32
configs/cloudctrl/nsh/defconfig
View File

@ -2,12 +2,12 @@
# CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set
# CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PS is not set
# CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_CALLBACK is not set
CONFIG_ARCH_BOARD_CLOUDCTRL=y CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="cloudctrl" CONFIG_ARCH_BOARD="cloudctrl"
CONFIG_ARCH_BOARD_CLOUDCTRL=y
CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32F107VC=y CONFIG_ARCH_CHIP_STM32F107VC=y
CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm"
CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y
CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BOARD_LOOPSPERMSEC=5483
CONFIG_BUILTIN=y CONFIG_BUILTIN=y
@ -21,24 +21,24 @@ CONFIG_HOST_WINDOWS=y
CONFIG_INTELHEX_BINARY=y CONFIG_INTELHEX_BINARY=y
CONFIG_MAX_TASKS=16 CONFIG_MAX_TASKS=16
CONFIG_MAX_WDOGPARMS=2 CONFIG_MAX_WDOGPARMS=2
CONFIG_MMCSD_SPICLOCK=12500000
CONFIG_MMCSD=y CONFIG_MMCSD=y
CONFIG_NET_ICMP_SOCKET=y CONFIG_MMCSD_SPICLOCK=12500000
CONFIG_NET_ICMP=y
CONFIG_NET_MAX_LISTENPORTS=40
CONFIG_NET_SOCKOPTS=y
CONFIG_NET_STATISTICS=y
CONFIG_NET_TCP_CONNS=40
CONFIG_NET_TCP=y
CONFIG_NET_TCPBACKLOG=y
CONFIG_NET_UDP_CHECKSUMS=y
CONFIG_NET_UDP=y
CONFIG_NET=y CONFIG_NET=y
CONFIG_NETDB_DNSCLIENT=y CONFIG_NETDB_DNSCLIENT=y
CONFIG_NETDB_DNSSERVER_NOADDR=y CONFIG_NETDB_DNSSERVER_NOADDR=y
CONFIG_NETUTILS_TELNETD=y CONFIG_NETUTILS_TELNETD=y
CONFIG_NETUTILS_TFTPC=y CONFIG_NETUTILS_TFTPC=y
CONFIG_NETUTILS_WEBCLIENT=y CONFIG_NETUTILS_WEBCLIENT=y
CONFIG_NET_ICMP=y
CONFIG_NET_ICMP_SOCKET=y
CONFIG_NET_MAX_LISTENPORTS=40
CONFIG_NET_SOCKOPTS=y
CONFIG_NET_STATISTICS=y
CONFIG_NET_TCP=y
CONFIG_NET_TCPBACKLOG=y
CONFIG_NET_TCP_CONNS=40
CONFIG_NET_UDP=y
CONFIG_NET_UDP_CHECKSUMS=y
CONFIG_NFILE_DESCRIPTORS=8 CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8 CONFIG_NFILE_STREAMS=8
CONFIG_NSH_ARCHINIT=y CONFIG_NSH_ARCHINIT=y
@ -60,22 +60,22 @@ CONFIG_SCHED_HPWORK=y
CONFIG_SCHED_WAITPID=y CONFIG_SCHED_WAITPID=y
CONFIG_SDCLONE_DISABLE=y CONFIG_SDCLONE_DISABLE=y
CONFIG_STM32_BKP=y CONFIG_STM32_BKP=y
CONFIG_STM32_ETH_REMAP=y
CONFIG_STM32_ETHMAC=y CONFIG_STM32_ETHMAC=y
CONFIG_STM32_ETH_REMAP=y
CONFIG_STM32_JTAG_FULL_ENABLE=y CONFIG_STM32_JTAG_FULL_ENABLE=y
CONFIG_STM32_PHYADDR=0 CONFIG_STM32_PHYADDR=0
CONFIG_STM32_PHYINIT=y CONFIG_STM32_PHYINIT=y
CONFIG_STM32_PHYSR=17
CONFIG_STM32_PHYSR_100FD=0x8000 CONFIG_STM32_PHYSR_100FD=0x8000
CONFIG_STM32_PHYSR_100HD=0x4000 CONFIG_STM32_PHYSR_100HD=0x4000
CONFIG_STM32_PHYSR_10FD=0x2000 CONFIG_STM32_PHYSR_10FD=0x2000
CONFIG_STM32_PHYSR_10HD=0x1000 CONFIG_STM32_PHYSR_10HD=0x1000
CONFIG_STM32_PHYSR_ALTCONFIG=y CONFIG_STM32_PHYSR_ALTCONFIG=y
CONFIG_STM32_PHYSR_ALTMODE=0xf000 CONFIG_STM32_PHYSR_ALTMODE=0xf000
CONFIG_STM32_PHYSR=17
CONFIG_STM32_PWR=y CONFIG_STM32_PWR=y
CONFIG_STM32_SPI1=y CONFIG_STM32_SPI1=y
CONFIG_STM32_USART2_REMAP=y
CONFIG_STM32_USART2=y CONFIG_STM32_USART2=y
CONFIG_STM32_USART2_REMAP=y
CONFIG_SYSTEM_PING=y CONFIG_SYSTEM_PING=y
CONFIG_TASK_NAME_SIZE=0 CONFIG_TASK_NAME_SIZE=0
CONFIG_USART2_RXBUFSIZE=128 CONFIG_USART2_RXBUFSIZE=128

1
configs/cloudctrl/scripts/cloudctrl-dfu.ld
View File

@ -46,6 +46,7 @@ MEMORY
} }
OUTPUT_ARCH(arm) OUTPUT_ARCH(arm)
EXTERN(_vectors)
ENTRY(_stext) ENTRY(_stext)
SECTIONS SECTIONS
{ {

1
configs/cloudctrl/scripts/cloudctrl.ld
View File

@ -44,6 +44,7 @@ MEMORY
} }
OUTPUT_ARCH(arm) OUTPUT_ARCH(arm)
EXTERN(_vectors)
ENTRY(_stext) ENTRY(_stext)
SECTIONS SECTIONS
{ {

30
configs/fire-stm32v2/nsh/defconfig
View File

@ -3,12 +3,12 @@
# CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set
# CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PS is not set
# CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_CALLBACK is not set
CONFIG_ARCH_BOARD_FIRE_STM32=y CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="fire-stm32v2" CONFIG_ARCH_BOARD="fire-stm32v2"
CONFIG_ARCH_BOARD_FIRE_STM32=y
CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32F103VE=y CONFIG_ARCH_CHIP_STM32F103VE=y
CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm"
CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y
CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BOARD_LOOPSPERMSEC=5483
CONFIG_BUILTIN=y CONFIG_BUILTIN=y
@ -18,26 +18,16 @@ CONFIG_FAT_LCNAMES=y
CONFIG_FAT_LFN=y CONFIG_FAT_LFN=y
CONFIG_FS_FAT=y CONFIG_FS_FAT=y
CONFIG_HOST_WINDOWS=y CONFIG_HOST_WINDOWS=y
CONFIG_I2C_POLLED=y
CONFIG_I2C=y CONFIG_I2C=y
CONFIG_I2CTOOL_DEFFREQ=100000 CONFIG_I2CTOOL_DEFFREQ=100000
CONFIG_I2CTOOL_MAXBUS=2 CONFIG_I2CTOOL_MAXBUS=2
CONFIG_I2CTOOL_MINBUS=1 CONFIG_I2CTOOL_MINBUS=1
CONFIG_I2C_POLLED=y
CONFIG_INTELHEX_BINARY=y CONFIG_INTELHEX_BINARY=y
CONFIG_MAX_TASKS=16 CONFIG_MAX_TASKS=16
CONFIG_MAX_WDOGPARMS=2 CONFIG_MAX_WDOGPARMS=2
CONFIG_MMCSD_SDIO=y
CONFIG_MMCSD=y CONFIG_MMCSD=y
CONFIG_NET_BROADCAST=y CONFIG_MMCSD_SDIO=y
CONFIG_NET_ICMP_SOCKET=y
CONFIG_NET_ICMP=y
CONFIG_NET_MAX_LISTENPORTS=16
CONFIG_NET_SOCKOPTS=y
CONFIG_NET_STATISTICS=y
CONFIG_NET_TCP_CONNS=16
CONFIG_NET_TCP=y
CONFIG_NET_UDP_CHECKSUMS=y
CONFIG_NET_UDP=y
CONFIG_NET=y CONFIG_NET=y
CONFIG_NETDB_DNSCLIENT=y CONFIG_NETDB_DNSCLIENT=y
CONFIG_NETDB_DNSSERVER_NOADDR=y CONFIG_NETDB_DNSSERVER_NOADDR=y
@ -45,6 +35,16 @@ CONFIG_NETDEVICES=y
CONFIG_NETUTILS_TELNETD=y CONFIG_NETUTILS_TELNETD=y
CONFIG_NETUTILS_TFTPC=y CONFIG_NETUTILS_TFTPC=y
CONFIG_NETUTILS_WEBCLIENT=y CONFIG_NETUTILS_WEBCLIENT=y
CONFIG_NET_BROADCAST=y
CONFIG_NET_ICMP=y
CONFIG_NET_ICMP_SOCKET=y
CONFIG_NET_MAX_LISTENPORTS=16
CONFIG_NET_SOCKOPTS=y
CONFIG_NET_STATISTICS=y
CONFIG_NET_TCP=y
CONFIG_NET_TCP_CONNS=16
CONFIG_NET_UDP=y
CONFIG_NET_UDP_CHECKSUMS=y
CONFIG_NFILE_DESCRIPTORS=8 CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8 CONFIG_NFILE_STREAMS=8
CONFIG_NSH_ARCHINIT=y CONFIG_NSH_ARCHINIT=y
@ -80,6 +80,7 @@ CONFIG_SYSTEM_PING=y
CONFIG_SYSTEM_USBMSC=y CONFIG_SYSTEM_USBMSC=y
CONFIG_TASK_NAME_SIZE=0 CONFIG_TASK_NAME_SIZE=0
CONFIG_USART1_SERIAL_CONSOLE=y CONFIG_USART1_SERIAL_CONSOLE=y
CONFIG_USBMSC=y
CONFIG_USBMSC_BULKINREQLEN=256 CONFIG_USBMSC_BULKINREQLEN=256
CONFIG_USBMSC_BULKOUTREQLEN=256 CONFIG_USBMSC_BULKOUTREQLEN=256
CONFIG_USBMSC_EPBULKIN=5 CONFIG_USBMSC_EPBULKIN=5
@ -88,6 +89,5 @@ CONFIG_USBMSC_NWRREQS=2
CONFIG_USBMSC_PRODUCTSTR="USBdev Storage" CONFIG_USBMSC_PRODUCTSTR="USBdev Storage"
CONFIG_USBMSC_REMOVABLE=y CONFIG_USBMSC_REMOVABLE=y
CONFIG_USBMSC_VERSIONNO=0x0399 CONFIG_USBMSC_VERSIONNO=0x0399
CONFIG_USBMSC=y
CONFIG_USER_ENTRYPOINT="nsh_main" CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_WDOG_INTRESERVE=2 CONFIG_WDOG_INTRESERVE=2

1
configs/fire-stm32v2/scripts/fire-stm32v2-dfu.ld
View File

@ -46,6 +46,7 @@ MEMORY
} }
OUTPUT_ARCH(arm) OUTPUT_ARCH(arm)
EXTERN(_vectors)
ENTRY(_stext) ENTRY(_stext)
SECTIONS SECTIONS
{ {

1
configs/fire-stm32v2/scripts/fire-stm32v2.ld
View File

@ -47,6 +47,7 @@ MEMORY
} }
OUTPUT_ARCH(arm) OUTPUT_ARCH(arm)
EXTERN(_vectors)
ENTRY(_stext) ENTRY(_stext)
SECTIONS SECTIONS
{ {

6
configs/hymini-stm32v/nsh/defconfig
View File

@ -1,13 +1,13 @@
# CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set
# CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PS is not set
CONFIG_ARCH_BOARD_HYMINI_STM32V=y CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="hymini-stm32v" CONFIG_ARCH_BOARD="hymini-stm32v"
CONFIG_ARCH_BOARD_HYMINI_STM32V=y
CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32F103VC=y CONFIG_ARCH_CHIP_STM32F103VC=y
CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_IRQBUTTONS=y
CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm"
CONFIG_BINFMT_DISABLE=y CONFIG_BINFMT_DISABLE=y
CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BOARD_LOOPSPERMSEC=5483
CONFIG_DISABLE_POLL=y CONFIG_DISABLE_POLL=y
@ -16,8 +16,8 @@ CONFIG_FAT_LCNAMES=y
CONFIG_FS_FAT=y CONFIG_FS_FAT=y
CONFIG_MAX_TASKS=16 CONFIG_MAX_TASKS=16
CONFIG_MAX_WDOGPARMS=2 CONFIG_MAX_WDOGPARMS=2
CONFIG_MMCSD_SDIO=y
CONFIG_MMCSD=y CONFIG_MMCSD=y
CONFIG_MMCSD_SDIO=y
CONFIG_NFILE_DESCRIPTORS=8 CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8 CONFIG_NFILE_STREAMS=8
CONFIG_NSH_ARCHINIT=y CONFIG_NSH_ARCHINIT=y

24
configs/hymini-stm32v/nsh2/defconfig
View File

@ -1,54 +1,54 @@
# CONFIG_MMCSD_MMCSUPPORT is not set # CONFIG_MMCSD_MMCSUPPORT is not set
# CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set
# CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PS is not set
# CONFIG_NXFONTS_DISABLE_16BPP is not set
# CONFIG_NX_DISABLE_16BPP is not set # CONFIG_NX_DISABLE_16BPP is not set
# CONFIG_NX_PACKEDMSFIRST is not set # CONFIG_NX_PACKEDMSFIRST is not set
# CONFIG_NXFONTS_DISABLE_16BPP is not set
# CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_CALLBACK is not set
CONFIG_ARCH_BOARD_HYMINI_STM32V=y CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="hymini-stm32v" CONFIG_ARCH_BOARD="hymini-stm32v"
CONFIG_ARCH_BOARD_HYMINI_STM32V=y
CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32F103VC=y CONFIG_ARCH_CHIP_STM32F103VC=y
CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_IRQBUTTONS=y
CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm"
CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BOARD_LOOPSPERMSEC=5483
CONFIG_BUILTIN=y CONFIG_BUILTIN=y
CONFIG_DISABLE_POLL=y CONFIG_DISABLE_POLL=y
CONFIG_EXAMPLES_NSH=y CONFIG_EXAMPLES_NSH=y
CONFIG_EXAMPLES_NX_BPP=16
CONFIG_EXAMPLES_NX=y CONFIG_EXAMPLES_NX=y
CONFIG_EXAMPLES_NXHELLO_BPP=16
CONFIG_EXAMPLES_NXHELLO=y CONFIG_EXAMPLES_NXHELLO=y
CONFIG_EXAMPLES_NXIMAGE_BPP=16 CONFIG_EXAMPLES_NXHELLO_BPP=16
CONFIG_EXAMPLES_NXIMAGE=y CONFIG_EXAMPLES_NXIMAGE=y
CONFIG_EXAMPLES_NXIMAGE_BPP=16
CONFIG_EXAMPLES_NX_BPP=16
CONFIG_EXAMPLES_TOUCHSCREEN=y CONFIG_EXAMPLES_TOUCHSCREEN=y
CONFIG_FAT_LCNAMES=y CONFIG_FAT_LCNAMES=y
CONFIG_FAT_LFN=y CONFIG_FAT_LFN=y
CONFIG_FS_FAT=y CONFIG_FS_FAT=y
CONFIG_FS_FATTIME=y CONFIG_FS_FATTIME=y
CONFIG_FS_ROMFS=y CONFIG_FS_ROMFS=y
CONFIG_INPUT_ADS7843E=y
CONFIG_INPUT=y CONFIG_INPUT=y
CONFIG_INPUT_ADS7843E=y
CONFIG_LCD=y
CONFIG_LCD_MAXCONTRAST=1 CONFIG_LCD_MAXCONTRAST=1
CONFIG_LCD_MAXPOWER=100 CONFIG_LCD_MAXPOWER=100
CONFIG_LCD_SSD1289=y CONFIG_LCD_SSD1289=y
CONFIG_LCD=y
CONFIG_MAX_TASKS=16 CONFIG_MAX_TASKS=16
CONFIG_MAX_WDOGPARMS=2 CONFIG_MAX_WDOGPARMS=2
CONFIG_MMCSD_SDIO=y
CONFIG_MMCSD=y CONFIG_MMCSD=y
CONFIG_MMCSD_SDIO=y
CONFIG_MQ_MAXMSGSIZE=64 CONFIG_MQ_MAXMSGSIZE=64
CONFIG_NFILE_DESCRIPTORS=8 CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8 CONFIG_NFILE_STREAMS=8
CONFIG_NSH_ARCHINIT=y CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_READLINE=y CONFIG_NSH_READLINE=y
CONFIG_NX_BLOCKING=y
CONFIG_NX=y CONFIG_NX=y
CONFIG_NXFONT_SANS23X27=y CONFIG_NXFONT_SANS23X27=y
CONFIG_NXFONT_SANS28X37B=y CONFIG_NXFONT_SANS28X37B=y
CONFIG_NX_BLOCKING=y
CONFIG_PREALLOC_MQ_MSGS=4 CONFIG_PREALLOC_MQ_MSGS=4
CONFIG_PREALLOC_TIMERS=4 CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=8 CONFIG_PREALLOC_WDOGS=8
@ -69,8 +69,8 @@ CONFIG_STM32_FSMC=y
CONFIG_STM32_PWR=y CONFIG_STM32_PWR=y
CONFIG_STM32_SDIO=y CONFIG_STM32_SDIO=y
CONFIG_STM32_SPI1=y CONFIG_STM32_SPI1=y
CONFIG_STM32_TIM3_PARTIAL_REMAP=y
CONFIG_STM32_TIM3=y CONFIG_STM32_TIM3=y
CONFIG_STM32_TIM3_PARTIAL_REMAP=y
CONFIG_STM32_USART1=y CONFIG_STM32_USART1=y
CONFIG_STM32_USB=y CONFIG_STM32_USB=y
CONFIG_SYMTAB_ORDEREDBYNAME=y CONFIG_SYMTAB_ORDEREDBYNAME=y
@ -78,6 +78,7 @@ CONFIG_SYSTEM_USBMSC=y
CONFIG_TASK_NAME_SIZE=0 CONFIG_TASK_NAME_SIZE=0
CONFIG_USART1_SERIAL_CONSOLE=y CONFIG_USART1_SERIAL_CONSOLE=y
CONFIG_USBDEV_TRACE=y CONFIG_USBDEV_TRACE=y
CONFIG_USBMSC=y
CONFIG_USBMSC_BULKINREQLEN=256 CONFIG_USBMSC_BULKINREQLEN=256
CONFIG_USBMSC_BULKOUTREQLEN=256 CONFIG_USBMSC_BULKOUTREQLEN=256
CONFIG_USBMSC_EPBULKIN=5 CONFIG_USBMSC_EPBULKIN=5
@ -86,6 +87,5 @@ CONFIG_USBMSC_NWRREQS=2
CONFIG_USBMSC_PRODUCTSTR="USBdev Storage" CONFIG_USBMSC_PRODUCTSTR="USBdev Storage"
CONFIG_USBMSC_REMOVABLE=y CONFIG_USBMSC_REMOVABLE=y
CONFIG_USBMSC_VERSIONNO=0x0399 CONFIG_USBMSC_VERSIONNO=0x0399
CONFIG_USBMSC=y
CONFIG_USER_ENTRYPOINT="nsh_main" CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_WDOG_INTRESERVE=1 CONFIG_WDOG_INTRESERVE=1

1
configs/hymini-stm32v/scripts/ld.script
View File

@ -48,6 +48,7 @@ MEMORY
} }
OUTPUT_ARCH(arm) OUTPUT_ARCH(arm)
EXTERN(_vectors)
ENTRY(_stext) ENTRY(_stext)
SECTIONS SECTIONS
{ {

8
configs/hymini-stm32v/usbmsc/defconfig
View File

@ -1,19 +1,19 @@
# CONFIG_MMCSD_HAVE_CARDDETECT is not set # CONFIG_MMCSD_HAVE_CARDDETECT is not set
# CONFIG_MMCSD_MMCSUPPORT is not set # CONFIG_MMCSD_MMCSUPPORT is not set
CONFIG_ARCH_BOARD_HYMINI_STM32V=y CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="hymini-stm32v" CONFIG_ARCH_BOARD="hymini-stm32v"
CONFIG_ARCH_BOARD_HYMINI_STM32V=y
CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32F103VC=y CONFIG_ARCH_CHIP_STM32F103VC=y
CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm"
CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y
CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BOARD_LOOPSPERMSEC=5483
CONFIG_DISABLE_POLL=y CONFIG_DISABLE_POLL=y
CONFIG_LIB_BOARDCTL=y CONFIG_LIB_BOARDCTL=y
CONFIG_MAX_TASKS=16 CONFIG_MAX_TASKS=16
CONFIG_MAX_WDOGPARMS=2 CONFIG_MAX_WDOGPARMS=2
CONFIG_MMCSD_SDIO=y
CONFIG_MMCSD=y CONFIG_MMCSD=y
CONFIG_MMCSD_SDIO=y
CONFIG_NFILE_DESCRIPTORS=8 CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8 CONFIG_NFILE_STREAMS=8
CONFIG_PREALLOC_MQ_MSGS=4 CONFIG_PREALLOC_MQ_MSGS=4
@ -40,6 +40,7 @@ CONFIG_SYMTAB_ORDEREDBYNAME=y
CONFIG_SYSTEM_USBMSC=y CONFIG_SYSTEM_USBMSC=y
CONFIG_TASK_NAME_SIZE=0 CONFIG_TASK_NAME_SIZE=0
CONFIG_USART1_SERIAL_CONSOLE=y CONFIG_USART1_SERIAL_CONSOLE=y
CONFIG_USBMSC=y
CONFIG_USBMSC_BULKINREQLEN=256 CONFIG_USBMSC_BULKINREQLEN=256
CONFIG_USBMSC_BULKOUTREQLEN=256 CONFIG_USBMSC_BULKOUTREQLEN=256
CONFIG_USBMSC_EPBULKIN=5 CONFIG_USBMSC_EPBULKIN=5
@ -48,6 +49,5 @@ CONFIG_USBMSC_NWRREQS=2
CONFIG_USBMSC_PRODUCTSTR="USBdev Storage" CONFIG_USBMSC_PRODUCTSTR="USBdev Storage"
CONFIG_USBMSC_REMOVABLE=y CONFIG_USBMSC_REMOVABLE=y
CONFIG_USBMSC_VERSIONNO=0x0399 CONFIG_USBMSC_VERSIONNO=0x0399
CONFIG_USBMSC=y
CONFIG_USER_ENTRYPOINT="msconn_main" CONFIG_USER_ENTRYPOINT="msconn_main"
CONFIG_WDOG_INTRESERVE=1 CONFIG_WDOG_INTRESERVE=1

8
configs/hymini-stm32v/usbnsh/defconfig
View File

@ -1,20 +1,20 @@
# CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set
# CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PS is not set
CONFIG_ARCH_BOARD_HYMINI_STM32V=y CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="hymini-stm32v" CONFIG_ARCH_BOARD="hymini-stm32v"
CONFIG_ARCH_BOARD_HYMINI_STM32V=y
CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32F103VC=y CONFIG_ARCH_CHIP_STM32F103VC=y
CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_IRQBUTTONS=y
CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm"
CONFIG_BINFMT_DISABLE=y CONFIG_BINFMT_DISABLE=y
CONFIG_BOARD_LOOPSPERMSEC=5483
CONFIG_BOARDCTL_USBDEVCTRL=y CONFIG_BOARDCTL_USBDEVCTRL=y
CONFIG_BOARD_LOOPSPERMSEC=5483
CONFIG_CDCACM=y
CONFIG_CDCACM_CONSOLE=y CONFIG_CDCACM_CONSOLE=y
CONFIG_CDCACM_RXBUFSIZE=256 CONFIG_CDCACM_RXBUFSIZE=256
CONFIG_CDCACM_TXBUFSIZE=256 CONFIG_CDCACM_TXBUFSIZE=256
CONFIG_CDCACM=y
CONFIG_DISABLE_POLL=y CONFIG_DISABLE_POLL=y
CONFIG_EXAMPLES_NSH=y CONFIG_EXAMPLES_NSH=y
CONFIG_LIB_BOARDCTL=y CONFIG_LIB_BOARDCTL=y

6
configs/hymini-stm32v/usbserial/defconfig
View File

@ -1,9 +1,9 @@
CONFIG_ARCH_BOARD_HYMINI_STM32V=y CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="hymini-stm32v" CONFIG_ARCH_BOARD="hymini-stm32v"
CONFIG_ARCH_BOARD_HYMINI_STM32V=y
CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32F103VC=y CONFIG_ARCH_CHIP_STM32F103VC=y
CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm"
CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y
CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BOARD_LOOPSPERMSEC=5483
CONFIG_DISABLE_MOUNTPOINT=y CONFIG_DISABLE_MOUNTPOINT=y
@ -14,11 +14,11 @@ CONFIG_MAX_TASKS=16
CONFIG_MAX_WDOGPARMS=2 CONFIG_MAX_WDOGPARMS=2
CONFIG_NFILE_DESCRIPTORS=8 CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8 CONFIG_NFILE_STREAMS=8
CONFIG_PL2303=y
CONFIG_PL2303_PRODUCTSTR="USBdev Serial" CONFIG_PL2303_PRODUCTSTR="USBdev Serial"
CONFIG_PL2303_RXBUFSIZE=512 CONFIG_PL2303_RXBUFSIZE=512
CONFIG_PL2303_TXBUFSIZE=512 CONFIG_PL2303_TXBUFSIZE=512
CONFIG_PL2303_VENDORSTR="Nuttx" CONFIG_PL2303_VENDORSTR="Nuttx"
CONFIG_PL2303=y
CONFIG_PREALLOC_MQ_MSGS=4 CONFIG_PREALLOC_MQ_MSGS=4
CONFIG_PREALLOC_TIMERS=4 CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=8 CONFIG_PREALLOC_WDOGS=8

42
configs/lpc4330-xplorer/README.txt
View File

@ -337,39 +337,31 @@ FPU Configuration Options
------------------------- -------------------------
There are two version of the FPU support built into the most NuttX Cortex-M4 There are two version of the FPU support built into the most NuttX Cortex-M4
ports. The current LPC43xx port support only one of these options, the "Non- ports.
Lazy Floating Point Register Save". As a consequence, CONFIG_ARMV7M_CMNVECTOR
must be defined in *all* LPC43xx configuration files.
1. Lazy Floating Point Register Save. 1. Non-Lazy Floating Point Register Save
This is an untested implementation that saves and restores FPU registers In this configuration floating point register save and restore is
only on context switches. This means: (1) floating point registers are implemented on interrupt entry and return, respectively. In this
not stored on each context switch and, hence, possibly better interrupt case, you may use floating point operations for interrupt handling
logic if necessary. This FPU behavior logic is enabled by default
with:
CONFIG_ARCH_FPU=y
2. Lazy Floating Point Register Save.
An alternative mplementation only saves and restores FPU registers only
on context switches. This means: (1) floating point registers are not
stored on each context switch and, hence, possibly better interrupt
performance. But, (2) since floating point registers are not saved, performance. But, (2) since floating point registers are not saved,
you cannot use floating point operations within interrupt handlers. you cannot use floating point operations within interrupt handlers.
This logic can be enabled by simply adding the following to your .config This logic can be enabled by simply adding the following to your .config
file: file:
CONFIG_ARCH_FPU=y CONFIG_ARCH_FPU=y
CONFIG_ARMV7M_LAZYFPU=y
2. Non-Lazy Floating Point Register Save
Mike Smith has contributed an extensive re-write of the ARMv7-M exception
handling logic. This includes verified support for the FPU. These changes
have not yet been incorporated into the mainline and are still considered
experimental. These FPU logic can be enabled with:
CONFIG_ARCH_FPU=y
CONFIG_ARMV7M_CMNVECTOR=y
You will probably also changes to the ld.script in if this option is selected.
This should work:
-ENTRY(_stext)
+ENTRY(__start) /* Treat __start as the anchor for dead code stripping */
+EXTERN(_vectors) /* Force the vectors to be included in the output */
CFLAGS CFLAGS
------ ------

3
configs/lpc4330-xplorer/src/lpc43_ostest.c
View File

@ -58,8 +58,7 @@
#undef HAVE_FPU #undef HAVE_FPU
#if defined(CONFIG_ARCH_FPU) && defined(CONFIG_EXAMPLES_OSTEST_FPUSIZE) && \ #if defined(CONFIG_ARCH_FPU) && defined(CONFIG_EXAMPLES_OSTEST_FPUSIZE) && \
defined(CONFIG_SCHED_WAITPID) && !defined(CONFIG_DISABLE_SIGNALS) && \ defined(CONFIG_SCHED_WAITPID) && !defined(CONFIG_DISABLE_SIGNALS)
!defined(CONFIG_ARMV7M_CMNVECTOR)
# define HAVE_FPU 1 # define HAVE_FPU 1
#endif #endif

42
configs/lpc4337-ws/README.txt
View File

@ -376,39 +376,31 @@ FPU Configuration Options
------------------------- -------------------------
There are two version of the FPU support built into the most NuttX Cortex-M4 There are two version of the FPU support built into the most NuttX Cortex-M4
ports. The current LPC43xx port support only one of these options, the "Non- ports.
Lazy Floating Point Register Save". As a consequence, CONFIG_ARMV7M_CMNVECTOR
must be defined in *all* LPC43xx configuration files.
1. Lazy Floating Point Register Save. 1. Non-Lazy Floating Point Register Save
This is an untested implementation that saves and restores FPU registers In this configuration floating point register save and restore is
only on context switches. This means: (1) floating point registers are implemented on interrupt entry and return, respectively. In this
not stored on each context switch and, hence, possibly better interrupt case, you may use floating point operations for interrupt handling
logic if necessary. This FPU behavior logic is enabled by default
with:
CONFIG_ARCH_FPU=y
2. Lazy Floating Point Register Save.
An alternative mplementation only saves and restores FPU registers only
on context switches. This means: (1) floating point registers are not
stored on each context switch and, hence, possibly better interrupt
performance. But, (2) since floating point registers are not saved, performance. But, (2) since floating point registers are not saved,
you cannot use floating point operations within interrupt handlers. you cannot use floating point operations within interrupt handlers.
This logic can be enabled by simply adding the following to your .config This logic can be enabled by simply adding the following to your .config
file: file:
CONFIG_ARCH_FPU=y CONFIG_ARCH_FPU=y
CONFIG_ARMV7M_LAZYFPU=y
2. Non-Lazy Floating Point Register Save
Mike Smith has contributed an extensive re-write of the ARMv7-M exception
handling logic. This includes verified support for the FPU. These changes
have not yet been incorporated into the mainline and are still considered
experimental. These FPU logic can be enabled with:
CONFIG_ARCH_FPU=y
CONFIG_ARMV7M_CMNVECTOR=y
You will probably also changes to the ld.script in if this option is selected.
This should work:
-ENTRY(_stext)
+ENTRY(__start) /* Treat __start as the anchor for dead code stripping */
+EXTERN(_vectors) /* Force the vectors to be included in the output */
CFLAGS CFLAGS
------ ------

42
configs/lpc4357-evb/README.txt
View File

@ -373,39 +373,31 @@ FPU Configuration Options
------------------------- -------------------------
There are two version of the FPU support built into the most NuttX Cortex-M4 There are two version of the FPU support built into the most NuttX Cortex-M4
ports. The current LPC43xx port support only one of these options, the "Non- ports.
Lazy Floating Point Register Save". As a consequence, CONFIG_ARMV7M_CMNVECTOR
must be defined in *all* LPC43xx configuration files.
1. Lazy Floating Point Register Save. 1. Non-Lazy Floating Point Register Save
This is an untested implementation that saves and restores FPU registers In this configuration floating point register save and restore is
only on context switches. This means: (1) floating point registers are implemented on interrupt entry and return, respectively. In this
not stored on each context switch and, hence, possibly better interrupt case, you may use floating point operations for interrupt handling
logic if necessary. This FPU behavior logic is enabled by default
with:
CONFIG_ARCH_FPU=y
2. Lazy Floating Point Register Save.
An alternative mplementation only saves and restores FPU registers only
on context switches. This means: (1) floating point registers are not
stored on each context switch and, hence, possibly better interrupt
performance. But, (2) since floating point registers are not saved, performance. But, (2) since floating point registers are not saved,
you cannot use floating point operations within interrupt handlers. you cannot use floating point operations within interrupt handlers.
This logic can be enabled by simply adding the following to your .config This logic can be enabled by simply adding the following to your .config
file: file:
CONFIG_ARCH_FPU=y CONFIG_ARCH_FPU=y
CONFIG_ARMV7M_LAZYFPU=y
2. Non-Lazy Floating Point Register Save
Mike Smith has contributed an extensive re-write of the ARMv7-M exception
handling logic. This includes verified support for the FPU. These changes
have not yet been incorporated into the mainline and are still considered
experimental. These FPU logic can be enabled with:
CONFIG_ARCH_FPU=y
CONFIG_ARMV7M_CMNVECTOR=y
You will probably also changes to the ld.script in if this option is selected.
This should work:
-ENTRY(_stext)
+ENTRY(__start) /* Treat __start as the anchor for dead code stripping */
+EXTERN(_vectors) /* Force the vectors to be included in the output */
CFLAGS CFLAGS
------ ------

3
configs/lpc4357-evb/src/lpc43_ostest.c
View File

@ -58,8 +58,7 @@
#undef HAVE_FPU #undef HAVE_FPU
#if defined(CONFIG_ARCH_FPU) && defined(CONFIG_EXAMPLES_OSTEST_FPUSIZE) && \ #if defined(CONFIG_ARCH_FPU) && defined(CONFIG_EXAMPLES_OSTEST_FPUSIZE) && \
defined(CONFIG_SCHED_WAITPID) && !defined(CONFIG_DISABLE_SIGNALS) && \ defined(CONFIG_SCHED_WAITPID) && !defined(CONFIG_DISABLE_SIGNALS)
!defined(CONFIG_ARMV7M_CMNVECTOR)
# define HAVE_FPU 1 # define HAVE_FPU 1
#endif #endif

42
configs/lpc4370-link2/README.txt
View File

@ -376,39 +376,31 @@ FPU Configuration Options
------------------------- -------------------------
There are two version of the FPU support built into the most NuttX Cortex-M4 There are two version of the FPU support built into the most NuttX Cortex-M4
ports. The current LPC43xx port support only one of these options, the "Non- ports.
Lazy Floating Point Register Save". As a consequence, CONFIG_ARMV7M_CMNVECTOR
must be defined in *all* LPC43xx configuration files.
1. Lazy Floating Point Register Save. 1. Non-Lazy Floating Point Register Save
This is an untested implementation that saves and restores FPU registers In this configuration floating point register save and restore is
only on context switches. This means: (1) floating point registers are implemented on interrupt entry and return, respectively. In this
not stored on each context switch and, hence, possibly better interrupt case, you may use floating point operations for interrupt handling
logic if necessary. This FPU behavior logic is enabled by default
with:
CONFIG_ARCH_FPU=y
2. Lazy Floating Point Register Save.
An alternative mplementation only saves and restores FPU registers only
on context switches. This means: (1) floating point registers are not
stored on each context switch and, hence, possibly better interrupt
performance. But, (2) since floating point registers are not saved, performance. But, (2) since floating point registers are not saved,
you cannot use floating point operations within interrupt handlers. you cannot use floating point operations within interrupt handlers.
This logic can be enabled by simply adding the following to your .config This logic can be enabled by simply adding the following to your .config
file: file:
CONFIG_ARCH_FPU=y CONFIG_ARCH_FPU=y
CONFIG_ARMV7M_LAZYFPU=y
2. Non-Lazy Floating Point Register Save
Mike Smith has contributed an extensive re-write of the ARMv7-M exception
handling logic. This includes verified support for the FPU. These changes
have not yet been incorporated into the mainline and are still considered
experimental. These FPU logic can be enabled with:
CONFIG_ARCH_FPU=y
CONFIG_ARMV7M_CMNVECTOR=y
You will probably also changes to the ld.script in if this option is selected.
This should work:
-ENTRY(_stext)
+ENTRY(__start) /* Treat __start as the anchor for dead code stripping */
+EXTERN(_vectors) /* Force the vectors to be included in the output */
CFLAGS CFLAGS
------ ------

3
configs/lpc4370-link2/src/lpc43_ostest.c
View File

@ -58,8 +58,7 @@
#undef HAVE_FPU #undef HAVE_FPU
#if defined(CONFIG_ARCH_FPU) && defined(CONFIG_EXAMPLES_OSTEST_FPUSIZE) && \ #if defined(CONFIG_ARCH_FPU) && defined(CONFIG_EXAMPLES_OSTEST_FPUSIZE) && \
defined(CONFIG_SCHED_WAITPID) && !defined(CONFIG_DISABLE_SIGNALS) && \ defined(CONFIG_SCHED_WAITPID) && !defined(CONFIG_DISABLE_SIGNALS)
!defined(CONFIG_ARMV7M_CMNVECTOR)
# define HAVE_FPU 1 # define HAVE_FPU 1
#endif #endif

12
configs/maple/nsh/defconfig
View File

@ -1,8 +1,8 @@
# CONFIG_DISABLE_OS_API is not set # CONFIG_DISABLE_OS_API is not set
# CONFIG_NSH_DISABLE_ADDROUTE is not set # CONFIG_NSH_DISABLEBG is not set
# CONFIG_NSH_DISABLESCRIPT is not set
# CONFIG_NSH_DISABLE_CMP is not set # CONFIG_NSH_DISABLE_CMP is not set
# CONFIG_NSH_DISABLE_DD is not set # CONFIG_NSH_DISABLE_DD is not set
# CONFIG_NSH_DISABLE_DELROUTE is not set
# CONFIG_NSH_DISABLE_EXEC is not set # CONFIG_NSH_DISABLE_EXEC is not set
# CONFIG_NSH_DISABLE_EXIT is not set # CONFIG_NSH_DISABLE_EXIT is not set
# CONFIG_NSH_DISABLE_GET is not set # CONFIG_NSH_DISABLE_GET is not set
@ -14,14 +14,12 @@
# CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PUT is not set
# CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_WGET is not set
# CONFIG_NSH_DISABLE_XD is not set # CONFIG_NSH_DISABLE_XD is not set
# CONFIG_NSH_DISABLEBG is not set CONFIG_ARCH="arm"
# CONFIG_NSH_DISABLESCRIPT is not set
CONFIG_ARCH_BOARD_MAPLE=y
CONFIG_ARCH_BOARD="maple" CONFIG_ARCH_BOARD="maple"
CONFIG_ARCH_BOARD_MAPLE=y
CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32F103CB=y CONFIG_ARCH_CHIP_STM32F103CB=y
CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm"
CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BOARD_LOOPSPERMSEC=5483
CONFIG_BUILTIN=y CONFIG_BUILTIN=y
CONFIG_DEFAULT_SMALL=y CONFIG_DEFAULT_SMALL=y
@ -53,7 +51,7 @@ CONFIG_STM32_USB=y
CONFIG_SYMTAB_ORDEREDBYNAME=y CONFIG_SYMTAB_ORDEREDBYNAME=y
CONFIG_TASK_NAME_SIZE=0 CONFIG_TASK_NAME_SIZE=0
CONFIG_USART1_SERIAL_CONSOLE=y CONFIG_USART1_SERIAL_CONSOLE=y
CONFIG_USBDEV_TRACE_NRECORDS=32
CONFIG_USBDEV_TRACE=y CONFIG_USBDEV_TRACE=y
CONFIG_USBDEV_TRACE_NRECORDS=32
CONFIG_USER_ENTRYPOINT="nsh_main" CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_WDOG_INTRESERVE=0 CONFIG_WDOG_INTRESERVE=0

20
configs/maple/nx/defconfig
View File

@ -1,5 +1,7 @@
# CONFIG_DEV_CONSOLE is not set # CONFIG_DEV_CONSOLE is not set
# CONFIG_DISABLE_OS_API is not set # CONFIG_DISABLE_OS_API is not set
# CONFIG_NSH_DISABLEBG is not set
# CONFIG_NSH_DISABLESCRIPT is not set
# CONFIG_NSH_DISABLE_CMP is not set # CONFIG_NSH_DISABLE_CMP is not set
# CONFIG_NSH_DISABLE_DD is not set # CONFIG_NSH_DISABLE_DD is not set
# CONFIG_NSH_DISABLE_EXEC is not set # CONFIG_NSH_DISABLE_EXEC is not set
@ -13,31 +15,29 @@
# CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PUT is not set
# CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_WGET is not set
# CONFIG_NSH_DISABLE_XD is not set # CONFIG_NSH_DISABLE_XD is not set
# CONFIG_NSH_DISABLEBG is not set
# CONFIG_NSH_DISABLESCRIPT is not set
# CONFIG_NX_DISABLE_1BPP is not set # CONFIG_NX_DISABLE_1BPP is not set
CONFIG_ARCH_BOARD_MAPLE=y CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="maple" CONFIG_ARCH_BOARD="maple"
CONFIG_ARCH_BOARD_MAPLE=y
CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32F103CB=y CONFIG_ARCH_CHIP_STM32F103CB=y
CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm"
CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BOARD_LOOPSPERMSEC=5483
CONFIG_BUILTIN=y CONFIG_BUILTIN=y
CONFIG_CDCACM=y
CONFIG_CDCACM_CONSOLE=y CONFIG_CDCACM_CONSOLE=y
CONFIG_CDCACM_RXBUFSIZE=256 CONFIG_CDCACM_RXBUFSIZE=256
CONFIG_CDCACM_TXBUFSIZE=256 CONFIG_CDCACM_TXBUFSIZE=256
CONFIG_CDCACM=y
CONFIG_DEFAULT_SMALL=y CONFIG_DEFAULT_SMALL=y
CONFIG_DISABLE_POLL=y CONFIG_DISABLE_POLL=y
CONFIG_EXAMPLES_NSH=y CONFIG_EXAMPLES_NSH=y
CONFIG_EXAMPLES_NX_BPP=1
CONFIG_EXAMPLES_NX=y CONFIG_EXAMPLES_NX=y
CONFIG_EXAMPLES_NXHELLO_BPP=1
CONFIG_EXAMPLES_NXHELLO=y CONFIG_EXAMPLES_NXHELLO=y
CONFIG_EXAMPLES_NXHELLO_BPP=1
CONFIG_EXAMPLES_NX_BPP=1
CONFIG_I2C=y CONFIG_I2C=y
CONFIG_LCD_SHARP_MEMLCD=y
CONFIG_LCD=y CONFIG_LCD=y
CONFIG_LCD_SHARP_MEMLCD=y
CONFIG_LIB_RAND_ORDER=2 CONFIG_LIB_RAND_ORDER=2
CONFIG_MAX_TASKS=16 CONFIG_MAX_TASKS=16
CONFIG_MAX_WDOGPARMS=2 CONFIG_MAX_WDOGPARMS=2
@ -48,9 +48,9 @@ CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_FILEIOSIZE=1024 CONFIG_NSH_FILEIOSIZE=1024
CONFIG_NSH_LINELEN=80 CONFIG_NSH_LINELEN=80
CONFIG_NSH_USBCONSOLE=y CONFIG_NSH_USBCONSOLE=y
CONFIG_NX_BLOCKING=y
CONFIG_NX=y CONFIG_NX=y
CONFIG_NXFONT_MONO5X8=y CONFIG_NXFONT_MONO5X8=y
CONFIG_NX_BLOCKING=y
CONFIG_PREALLOC_MQ_MSGS=4 CONFIG_PREALLOC_MQ_MSGS=4
CONFIG_PREALLOC_TIMERS=4 CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=6 CONFIG_PREALLOC_WDOGS=6
@ -75,7 +75,7 @@ CONFIG_STM32_USB=y
CONFIG_SYMTAB_ORDEREDBYNAME=y CONFIG_SYMTAB_ORDEREDBYNAME=y
CONFIG_TASK_NAME_SIZE=15 CONFIG_TASK_NAME_SIZE=15
CONFIG_USART1_SERIAL_CONSOLE=y CONFIG_USART1_SERIAL_CONSOLE=y
CONFIG_USBDEV_TRACE_NRECORDS=32
CONFIG_USBDEV_TRACE=y CONFIG_USBDEV_TRACE=y
CONFIG_USBDEV_TRACE_NRECORDS=32
CONFIG_USER_ENTRYPOINT="nsh_main" CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_WDOG_INTRESERVE=0 CONFIG_WDOG_INTRESERVE=0

1
configs/maple/scripts/ld.script
View File

@ -48,6 +48,7 @@ MEMORY
} }
OUTPUT_ARCH(arm) OUTPUT_ARCH(arm)
EXTERN(_vectors)
ENTRY(_stext) ENTRY(_stext)
SECTIONS SECTIONS
{ {

1
configs/maple/scripts/ld.script.dfu
View File

@ -47,6 +47,7 @@ MEMORY
} }
OUTPUT_ARCH(arm) OUTPUT_ARCH(arm)
EXTERN(_vectors)
ENTRY(_stext) ENTRY(_stext)
SECTIONS SECTIONS

14
configs/maple/usbnsh/defconfig
View File

@ -1,9 +1,9 @@
# CONFIG_DEV_CONSOLE is not set # CONFIG_DEV_CONSOLE is not set
# CONFIG_DISABLE_OS_API is not set # CONFIG_DISABLE_OS_API is not set
# CONFIG_NSH_DISABLE_ADDROUTE is not set # CONFIG_NSH_DISABLEBG is not set
# CONFIG_NSH_DISABLESCRIPT is not set
# CONFIG_NSH_DISABLE_CMP is not set # CONFIG_NSH_DISABLE_CMP is not set
# CONFIG_NSH_DISABLE_DD is not set # CONFIG_NSH_DISABLE_DD is not set
# CONFIG_NSH_DISABLE_DELROUTE is not set
# CONFIG_NSH_DISABLE_EXEC is not set # CONFIG_NSH_DISABLE_EXEC is not set
# CONFIG_NSH_DISABLE_EXIT is not set # CONFIG_NSH_DISABLE_EXIT is not set
# CONFIG_NSH_DISABLE_GET is not set # CONFIG_NSH_DISABLE_GET is not set
@ -15,20 +15,18 @@
# CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PUT is not set
# CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_WGET is not set
# CONFIG_NSH_DISABLE_XD is not set # CONFIG_NSH_DISABLE_XD is not set
# CONFIG_NSH_DISABLEBG is not set CONFIG_ARCH="arm"
# CONFIG_NSH_DISABLESCRIPT is not set
CONFIG_ARCH_BOARD_MAPLE=y
CONFIG_ARCH_BOARD="maple" CONFIG_ARCH_BOARD="maple"
CONFIG_ARCH_BOARD_MAPLE=y
CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32F103CB=y CONFIG_ARCH_CHIP_STM32F103CB=y
CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm"
CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BOARD_LOOPSPERMSEC=5483
CONFIG_BUILTIN=y CONFIG_BUILTIN=y
CONFIG_CDCACM=y
CONFIG_CDCACM_CONSOLE=y CONFIG_CDCACM_CONSOLE=y
CONFIG_CDCACM_RXBUFSIZE=256 CONFIG_CDCACM_RXBUFSIZE=256
CONFIG_CDCACM_TXBUFSIZE=256 CONFIG_CDCACM_TXBUFSIZE=256
CONFIG_CDCACM=y
CONFIG_DEFAULT_SMALL=y CONFIG_DEFAULT_SMALL=y
CONFIG_DISABLE_POLL=y CONFIG_DISABLE_POLL=y
CONFIG_EXAMPLES_NSH=y CONFIG_EXAMPLES_NSH=y
@ -61,7 +59,7 @@ CONFIG_STM32_USB=y
CONFIG_SYMTAB_ORDEREDBYNAME=y CONFIG_SYMTAB_ORDEREDBYNAME=y
CONFIG_TASK_NAME_SIZE=0 CONFIG_TASK_NAME_SIZE=0
CONFIG_USART1_SERIAL_CONSOLE=y CONFIG_USART1_SERIAL_CONSOLE=y
CONFIG_USBDEV_TRACE_NRECORDS=32
CONFIG_USBDEV_TRACE=y CONFIG_USBDEV_TRACE=y
CONFIG_USBDEV_TRACE_NRECORDS=32
CONFIG_USER_ENTRYPOINT="nsh_main" CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_WDOG_INTRESERVE=0 CONFIG_WDOG_INTRESERVE=0

38
configs/mikroe-stm32f4/README.txt
View File

@ -129,35 +129,29 @@ FPU Configuration Options
There are two version of the FPU support built into the STM32 port. There are two version of the FPU support built into the STM32 port.
1. Lazy Floating Point Register Save. 1. Non-Lazy Floating Point Register Save
This is an untested implementation that saves and restores FPU registers In this configuration floating point register save and restore is
only on context switches. This means: (1) floating point registers are implemented on interrupt entry and return, respectively. In this
not stored on each context switch and, hence, possibly better interrupt case, you may use floating point operations for interrupt handling
logic if necessary. This FPU behavior logic is enabled by default
with:
CONFIG_ARCH_FPU=y
2. Lazy Floating Point Register Save.
An alternative mplementation only saves and restores FPU registers only
on context switches. This means: (1) floating point registers are not
stored on each context switch and, hence, possibly better interrupt
performance. But, (2) since floating point registers are not saved, performance. But, (2) since floating point registers are not saved,
you cannot use floating point operations within interrupt handlers. you cannot use floating point operations within interrupt handlers.
This logic can be enabled by simply adding the following to your .config This logic can be enabled by simply adding the following to your .config
file: file:
CONFIG_ARCH_FPU=y CONFIG_ARCH_FPU=y
CONFIG_ARMV7M_LAZYFPU=y
2. Non-Lazy Floating Point Register Save
Mike Smith has contributed an extensive re-write of the ARMv7-M exception
handling logic. This includes verified support for the FPU. These changes
have not yet been incorporated into the mainline and are still considered
experimental. These FPU logic can be enabled with:
CONFIG_ARCH_FPU=y
CONFIG_ARMV7M_CMNVECTOR=y
You will probably also changes to the ld.script in if this option is selected.
This should work:
-ENTRY(_stext)
+ENTRY(__start) /* Treat __start as the anchor for dead code stripping */
+EXTERN(_vectors) /* Force the vectors to be included in the output */
MIO283QT-2/MIO283QT-9A MIO283QT-2/MIO283QT-9A
====================== ======================

51
configs/mikroe-stm32f4/fulldemo/defconfig
View File

@ -2,37 +2,37 @@
# CONFIG_DEV_CONSOLE is not set # CONFIG_DEV_CONSOLE is not set
# CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set
# CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PS is not set
# CONFIG_NX_DISABLE_16BPP is not set
# CONFIG_NXFONTS_DISABLE_16BPP is not set # CONFIG_NXFONTS_DISABLE_16BPP is not set
# CONFIG_NXPLAYER_INCLUDE_PREFERRED_DEVICE is not set # CONFIG_NXPLAYER_INCLUDE_PREFERRED_DEVICE is not set
# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set # CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set
# CONFIG_NX_DISABLE_16BPP is not set
# CONFIG_STM32_CCMEXCLUDE is not set # CONFIG_STM32_CCMEXCLUDE is not set
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="mikroe-stm32f4"
CONFIG_ARCH_BOARD_MIKROE_STM32F4=y CONFIG_ARCH_BOARD_MIKROE_STM32F4=y
CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y
CONFIG_ARCH_BOARD="mikroe-stm32f4"
CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F407VG=y
CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm" CONFIG_AUDIO=y
CONFIG_AUDIO_FORMAT_MIDI=y CONFIG_AUDIO_FORMAT_MIDI=y
CONFIG_AUDIO_VS1053=y CONFIG_AUDIO_VS1053=y
CONFIG_AUDIO=y
CONFIG_BOARD_LOOPSPERMSEC=16717
CONFIG_BOARDCTL_USBDEVCTRL=y CONFIG_BOARDCTL_USBDEVCTRL=y
CONFIG_BOARD_LOOPSPERMSEC=16717
CONFIG_BUILTIN=y CONFIG_BUILTIN=y
CONFIG_CDCACM=y
CONFIG_CDCACM_CONSOLE=y CONFIG_CDCACM_CONSOLE=y
CONFIG_CDCACM_RXBUFSIZE=256 CONFIG_CDCACM_RXBUFSIZE=256
CONFIG_CDCACM_TXBUFSIZE=256 CONFIG_CDCACM_TXBUFSIZE=256
CONFIG_CDCACM=y
CONFIG_DEBUG_SYMBOLS=y CONFIG_DEBUG_SYMBOLS=y
CONFIG_DEV_LOOP=y CONFIG_DEV_LOOP=y
CONFIG_DEV_ZERO=y CONFIG_DEV_ZERO=y
CONFIG_DISABLE_POLL=y CONFIG_DISABLE_POLL=y
CONFIG_DRIVERS_AUDIO=y CONFIG_DRIVERS_AUDIO=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_EXAMPLES_NSH=y CONFIG_EXAMPLES_NSH=y
CONFIG_EXAMPLES_NX_BPP=16 CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_EXAMPLES_NX=y CONFIG_EXAMPLES_NX=y
CONFIG_EXAMPLES_NX_BPP=16
CONFIG_EXAMPLES_TOUCHSCREEN=y CONFIG_EXAMPLES_TOUCHSCREEN=y
CONFIG_FS_BINFS=y CONFIG_FS_BINFS=y
CONFIG_FS_FAT=y CONFIG_FS_FAT=y
@ -42,24 +42,23 @@ CONFIG_HAVE_CXXINITIALIZE=y
CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_IDLETHREAD_STACKSIZE=2048
CONFIG_INPUT=y CONFIG_INPUT=y
CONFIG_INTELHEX_BINARY=y CONFIG_INTELHEX_BINARY=y
CONFIG_LCD_MIO283QT2=y
CONFIG_LCD=y CONFIG_LCD=y
CONFIG_LCD_MIO283QT2=y
CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_PERROR_STDOUT=y
CONFIG_LIB_BOARDCTL=y
CONFIG_LIBC_STRERROR=y CONFIG_LIBC_STRERROR=y
CONFIG_M25P_MANUFACTURER=0x1C CONFIG_M25P_MANUFACTURER=0x1C
CONFIG_M25P_MEMORY_TYPE=0x31 CONFIG_M25P_MEMORY_TYPE=0x31
CONFIG_M25P_SUBSECTOR_ERASE=y CONFIG_M25P_SUBSECTOR_ERASE=y
CONFIG_MAX_TASKS=16 CONFIG_MAX_TASKS=16
CONFIG_MAX_WDOGPARMS=2 CONFIG_MAX_WDOGPARMS=2
CONFIG_MIKROE_FLASH_PART=y
CONFIG_MIKROE_FLASH=y CONFIG_MIKROE_FLASH=y
CONFIG_MM_REGIONS=2 CONFIG_MIKROE_FLASH_PART=y
CONFIG_MMCSD_SPICLOCK=30000000
CONFIG_MMCSD=y CONFIG_MMCSD=y
CONFIG_MMCSD_SPICLOCK=30000000
CONFIG_MM_REGIONS=2
CONFIG_MQ_MAXMSGSIZE=64 CONFIG_MQ_MAXMSGSIZE=64
CONFIG_MTD_CONFIG_ERASEDVALUE=0xFF
CONFIG_MTD_CONFIG=y CONFIG_MTD_CONFIG=y
CONFIG_MTD_CONFIG_ERASEDVALUE=0xFF
CONFIG_MTD_PARTITION=y CONFIG_MTD_PARTITION=y
CONFIG_MTD_SMART_SECTOR_SIZE=512 CONFIG_MTD_SMART_SECTOR_SIZE=512
CONFIG_NFILE_DESCRIPTORS=8 CONFIG_NFILE_DESCRIPTORS=8
@ -73,9 +72,6 @@ CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y CONFIG_NSH_READLINE=y
CONFIG_NSH_ROMFSETC=y CONFIG_NSH_ROMFSETC=y
CONFIG_NSH_STRERROR=y CONFIG_NSH_STRERROR=y
CONFIG_NX_BLOCKING=y
CONFIG_NX_KBD=y
CONFIG_NX_XYINPUT_TOUCHSCREEN=y
CONFIG_NX=y CONFIG_NX=y
CONFIG_NXFONT_SANS17X23B=y CONFIG_NXFONT_SANS17X23B=y
CONFIG_NXFONT_SANS20X27B=y CONFIG_NXFONT_SANS20X27B=y
@ -84,44 +80,47 @@ CONFIG_NXFONT_SANS28X37B=y
CONFIG_NXFONT_SERIF22X28B=y CONFIG_NXFONT_SERIF22X28B=y
CONFIG_NXPLAYER_DEFAULT_MEDIADIR="/usr/sounds" CONFIG_NXPLAYER_DEFAULT_MEDIADIR="/usr/sounds"
CONFIG_NXPLAYER_INCLUDE_SYSTEM_RESET=y CONFIG_NXPLAYER_INCLUDE_SYSTEM_RESET=y
CONFIG_NXTERM_CURSORCHAR=95
CONFIG_NXTERM=y CONFIG_NXTERM=y
CONFIG_NXTERM_CURSORCHAR=95
CONFIG_NXTK_BORDERCOLOR1=0x8410 CONFIG_NXTK_BORDERCOLOR1=0x8410
CONFIG_NXTK_BORDERCOLOR2=0x4208 CONFIG_NXTK_BORDERCOLOR2=0x4208
CONFIG_NXTK_BORDERCOLOR3=0xc618 CONFIG_NXTK_BORDERCOLOR3=0xc618
CONFIG_NXTK_BORDERWIDTH=3 CONFIG_NXTK_BORDERWIDTH=3
CONFIG_NXWIDGETS=y
CONFIG_NXWIDGETS_BPP=16 CONFIG_NXWIDGETS_BPP=16
CONFIG_NXWIDGETS_SIZEOFCHAR=1 CONFIG_NXWIDGETS_SIZEOFCHAR=1
CONFIG_NXWIDGETS=y CONFIG_NXWM=y
CONFIG_NXWM_BACKGROUND_IMAGE="" CONFIG_NXWM_BACKGROUND_IMAGE=""
CONFIG_NXWM_HEXCALCULATOR_BACKGROUNDCOLOR=0x39C7 CONFIG_NXWM_HEXCALCULATOR_BACKGROUNDCOLOR=0x39C7
CONFIG_NXWM_HEXCALCULATOR_CUSTOM_COLORS=y CONFIG_NXWM_HEXCALCULATOR_CUSTOM_COLORS=y
CONFIG_NXWM_KEYBOARD=y
CONFIG_NXWM_KEYBOARD_DEVPATH="/dev/ttyS0" CONFIG_NXWM_KEYBOARD_DEVPATH="/dev/ttyS0"
CONFIG_NXWM_KEYBOARD_LISTENERPRIO=100 CONFIG_NXWM_KEYBOARD_LISTENERPRIO=100
CONFIG_NXWM_KEYBOARD=y
CONFIG_NXWM_MEDIAPLAYER=y CONFIG_NXWM_MEDIAPLAYER=y
CONFIG_NXWM_TASKBAR_LEFT=y CONFIG_NXWM_TASKBAR_LEFT=y
CONFIG_NXWM_TOUCHSCREEN_CONFIGDATA=y CONFIG_NXWM_TOUCHSCREEN_CONFIGDATA=y
CONFIG_NXWM_TOUCHSCREEN_LISTENERPRIO=100 CONFIG_NXWM_TOUCHSCREEN_LISTENERPRIO=100
CONFIG_NXWM_UNITTEST=y CONFIG_NXWM_UNITTEST=y
CONFIG_NXWM=y CONFIG_NX_BLOCKING=y
CONFIG_NX_KBD=y
CONFIG_NX_XYINPUT_TOUCHSCREEN=y
CONFIG_PLATFORM_CONFIGDATA=y CONFIG_PLATFORM_CONFIGDATA=y
CONFIG_PREALLOC_TIMERS=4 CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=8 CONFIG_PREALLOC_WDOGS=8
CONFIG_RAM_SIZE=114688
CONFIG_RAM_START=0x20000000
CONFIG_RAMDISK=y CONFIG_RAMDISK=y
CONFIG_RAMMTD=y CONFIG_RAMMTD=y
CONFIG_RAM_SIZE=114688
CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200 CONFIG_RR_INTERVAL=200
CONFIG_RTC=y
CONFIG_RTC_ALARM=y CONFIG_RTC_ALARM=y
CONFIG_RTC_DATETIME=y CONFIG_RTC_DATETIME=y
CONFIG_RTC=y
CONFIG_SCHED_HPWORK=y CONFIG_SCHED_HPWORK=y
CONFIG_SCHED_HPWORKPERIOD=20000 CONFIG_SCHED_HPWORKPERIOD=20000
CONFIG_SCHED_HPWORKPRIORITY=192 CONFIG_SCHED_HPWORKPRIORITY=192
CONFIG_SCHED_ONEXIT_MAX=4
CONFIG_SCHED_ONEXIT=y CONFIG_SCHED_ONEXIT=y
CONFIG_SCHED_ONEXIT_MAX=4
CONFIG_SCHED_WAITPID=y CONFIG_SCHED_WAITPID=y
CONFIG_SDCLONE_DISABLE=y CONFIG_SDCLONE_DISABLE=y
CONFIG_STM32_ADC2=y CONFIG_STM32_ADC2=y
@ -132,8 +131,8 @@ CONFIG_STM32_JTAG_SW_ENABLE=y
CONFIG_STM32_OTGFS=y CONFIG_STM32_OTGFS=y
CONFIG_STM32_PWR=y CONFIG_STM32_PWR=y
CONFIG_STM32_RNG=y CONFIG_STM32_RNG=y
CONFIG_STM32_SPI_DMA=y
CONFIG_STM32_SPI2=y CONFIG_STM32_SPI2=y
CONFIG_STM32_SPI_DMA=y
CONFIG_STM32_TIM1=y CONFIG_STM32_TIM1=y
CONFIG_STM32_USART2=y CONFIG_STM32_USART2=y
CONFIG_SYSLOG_CHAR=y CONFIG_SYSLOG_CHAR=y

24
configs/mikroe-stm32f4/kostest/defconfig
View File

@ -2,21 +2,21 @@
# CONFIG_DEV_CONSOLE is not set # CONFIG_DEV_CONSOLE is not set
# CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set
# CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_CALLBACK is not set
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="mikroe-stm32f4"
CONFIG_ARCH_BOARD_MIKROE_STM32F4=y CONFIG_ARCH_BOARD_MIKROE_STM32F4=y
CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y
CONFIG_ARCH_BOARD="mikroe-stm32f4"
CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F407VG=y
CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm"
CONFIG_ARM_MPU=y CONFIG_ARM_MPU=y
CONFIG_BOARD_LOOPSPERMSEC=16717
CONFIG_BOARDCTL_USBDEVCTRL=y CONFIG_BOARDCTL_USBDEVCTRL=y
CONFIG_BOARD_LOOPSPERMSEC=16717
CONFIG_BUILD_PROTECTED=y CONFIG_BUILD_PROTECTED=y
CONFIG_CDCACM=y
CONFIG_CDCACM_CONSOLE=y CONFIG_CDCACM_CONSOLE=y
CONFIG_CDCACM_RXBUFSIZE=256 CONFIG_CDCACM_RXBUFSIZE=256
CONFIG_CDCACM_TXBUFSIZE=256 CONFIG_CDCACM_TXBUFSIZE=256
CONFIG_CDCACM=y
CONFIG_DEBUG_SYMBOLS=y CONFIG_DEBUG_SYMBOLS=y
CONFIG_DEV_LOOP=y CONFIG_DEV_LOOP=y
CONFIG_DEV_ZERO=y CONFIG_DEV_ZERO=y
@ -36,11 +36,11 @@ CONFIG_M25P_MEMORY_TYPE=0x31
CONFIG_M25P_SUBSECTOR_ERASE=y CONFIG_M25P_SUBSECTOR_ERASE=y
CONFIG_MAX_TASKS=16 CONFIG_MAX_TASKS=16
CONFIG_MAX_WDOGPARMS=2 CONFIG_MAX_WDOGPARMS=2
CONFIG_MIKROE_FLASH_PART_LIST="256,768"
CONFIG_MIKROE_FLASH_PART=y
CONFIG_MIKROE_FLASH=y CONFIG_MIKROE_FLASH=y
CONFIG_MM_REGIONS=2 CONFIG_MIKROE_FLASH_PART=y
CONFIG_MIKROE_FLASH_PART_LIST="256,768"
CONFIG_MMCSD=y CONFIG_MMCSD=y
CONFIG_MM_REGIONS=2
CONFIG_MTD_PARTITION=y CONFIG_MTD_PARTITION=y
CONFIG_MTD_SMART_SECTOR_SIZE=512 CONFIG_MTD_SMART_SECTOR_SIZE=512
CONFIG_NFILE_DESCRIPTORS=8 CONFIG_NFILE_DESCRIPTORS=8
@ -55,20 +55,20 @@ CONFIG_PASS1_BUILDIR="configs/mikroe-stm32f4/kernel"
CONFIG_PREALLOC_MQ_MSGS=4 CONFIG_PREALLOC_MQ_MSGS=4
CONFIG_PREALLOC_TIMERS=4 CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=8 CONFIG_PREALLOC_WDOGS=8
CONFIG_RAM_SIZE=114688
CONFIG_RAM_START=0x20000000
CONFIG_RAMDISK=y CONFIG_RAMDISK=y
CONFIG_RAMMTD=y CONFIG_RAMMTD=y
CONFIG_RAM_SIZE=114688
CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200 CONFIG_RR_INTERVAL=200
CONFIG_RTC=y
CONFIG_RTC_ALARM=y CONFIG_RTC_ALARM=y
CONFIG_RTC_DATETIME=y CONFIG_RTC_DATETIME=y
CONFIG_RTC=y
CONFIG_SCHED_HPWORK=y CONFIG_SCHED_HPWORK=y
CONFIG_SCHED_HPWORKPERIOD=20000 CONFIG_SCHED_HPWORKPERIOD=20000
CONFIG_SCHED_HPWORKPRIORITY=192 CONFIG_SCHED_HPWORKPRIORITY=192
CONFIG_SCHED_ONEXIT_MAX=4
CONFIG_SCHED_ONEXIT=y CONFIG_SCHED_ONEXIT=y
CONFIG_SCHED_ONEXIT_MAX=4
CONFIG_SCHED_WAITPID=y CONFIG_SCHED_WAITPID=y
CONFIG_SDCLONE_DISABLE=y CONFIG_SDCLONE_DISABLE=y
CONFIG_STM32_ADC2=y CONFIG_STM32_ADC2=y
@ -81,9 +81,9 @@ CONFIG_STM32_RNG=y
CONFIG_STM32_SPI2=y CONFIG_STM32_SPI2=y
CONFIG_STM32_TIM1=y CONFIG_STM32_TIM1=y
CONFIG_STM32_USART2=y CONFIG_STM32_USART2=y
CONFIG_SYS_RESERVED=8
CONFIG_SYSLOG_CHAR=y CONFIG_SYSLOG_CHAR=y
CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" CONFIG_SYSLOG_DEVPATH="/dev/ttyS0"
CONFIG_SYS_RESERVED=8
CONFIG_TASK_NAME_SIZE=11 CONFIG_TASK_NAME_SIZE=11
CONFIG_USBDEV=y CONFIG_USBDEV=y
CONFIG_USER_ENTRYPOINT="ostest_main" CONFIG_USER_ENTRYPOINT="ostest_main"

16
configs/mikroe-stm32f4/nsh/defconfig
View File

@ -4,20 +4,20 @@
# CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set
# CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PS is not set
# CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_CALLBACK is not set
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="mikroe-stm32f4"
CONFIG_ARCH_BOARD_MIKROE_STM32F4=y CONFIG_ARCH_BOARD_MIKROE_STM32F4=y
CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y
CONFIG_ARCH_BOARD="mikroe-stm32f4"
CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F407VG=y
CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm"
CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BOARD_LOOPSPERMSEC=16717
CONFIG_BUILTIN=y CONFIG_BUILTIN=y
CONFIG_DEV_LOOP=y CONFIG_DEV_LOOP=y
CONFIG_DEV_ZERO=y CONFIG_DEV_ZERO=y
CONFIG_DISABLE_POLL=y CONFIG_DISABLE_POLL=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_EXAMPLES_NSH=y CONFIG_EXAMPLES_NSH=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_FS_FAT=y CONFIG_FS_FAT=y
CONFIG_FS_ROMFS=y CONFIG_FS_ROMFS=y
CONFIG_HAVE_CXX=y CONFIG_HAVE_CXX=y
@ -31,11 +31,11 @@ CONFIG_M25P_MEMORY_TYPE=0x31
CONFIG_M25P_SUBSECTOR_ERASE=y CONFIG_M25P_SUBSECTOR_ERASE=y
CONFIG_MAX_TASKS=16 CONFIG_MAX_TASKS=16
CONFIG_MAX_WDOGPARMS=2 CONFIG_MAX_WDOGPARMS=2
CONFIG_MIKROE_FLASH_PART_LIST="256,768"
CONFIG_MIKROE_FLASH_PART=y
CONFIG_MIKROE_FLASH=y CONFIG_MIKROE_FLASH=y
CONFIG_MM_REGIONS=2 CONFIG_MIKROE_FLASH_PART=y
CONFIG_MIKROE_FLASH_PART_LIST="256,768"
CONFIG_MMCSD=y CONFIG_MMCSD=y
CONFIG_MM_REGIONS=2
CONFIG_MTD_PARTITION=y CONFIG_MTD_PARTITION=y
CONFIG_MTD_SMART_SECTOR_SIZE=512 CONFIG_MTD_SMART_SECTOR_SIZE=512
CONFIG_NFILE_DESCRIPTORS=8 CONFIG_NFILE_DESCRIPTORS=8
@ -49,10 +49,10 @@ CONFIG_NSH_STRERROR=y
CONFIG_PREALLOC_MQ_MSGS=4 CONFIG_PREALLOC_MQ_MSGS=4
CONFIG_PREALLOC_TIMERS=4 CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=4 CONFIG_PREALLOC_WDOGS=4
CONFIG_RAM_SIZE=114688
CONFIG_RAM_START=0x20000000
CONFIG_RAMDISK=y CONFIG_RAMDISK=y
CONFIG_RAMMTD=y CONFIG_RAMMTD=y
CONFIG_RAM_SIZE=114688
CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200 CONFIG_RR_INTERVAL=200
CONFIG_SCHED_WAITPID=y CONFIG_SCHED_WAITPID=y

12
configs/mikroe-stm32f4/nx/defconfig
View File

@ -3,28 +3,28 @@
# CONFIG_DEV_NULL is not set # CONFIG_DEV_NULL is not set
# CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set
# CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PS is not set
# CONFIG_NX_DISABLE_16BPP is not set
# CONFIG_NXFONTS_DISABLE_16BPP is not set # CONFIG_NXFONTS_DISABLE_16BPP is not set
# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set # CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set
# CONFIG_NX_DISABLE_16BPP is not set
# CONFIG_SERIAL is not set # CONFIG_SERIAL is not set
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="mikroe-stm32f4"
CONFIG_ARCH_BOARD_MIKROE_STM32F4=y CONFIG_ARCH_BOARD_MIKROE_STM32F4=y
CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y
CONFIG_ARCH_BOARD="mikroe-stm32f4"
CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F407VG=y
CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm"
CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BOARD_LOOPSPERMSEC=16717
CONFIG_BUILTIN=y CONFIG_BUILTIN=y
CONFIG_DISABLE_POLL=y CONFIG_DISABLE_POLL=y
CONFIG_EXAMPLES_NX_BPP=16
CONFIG_EXAMPLES_NX=y CONFIG_EXAMPLES_NX=y
CONFIG_EXAMPLES_NX_BPP=16
CONFIG_HAVE_CXX=y CONFIG_HAVE_CXX=y
CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HAVE_CXXINITIALIZE=y
CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_IDLETHREAD_STACKSIZE=2048
CONFIG_INTELHEX_BINARY=y CONFIG_INTELHEX_BINARY=y
CONFIG_LCD_MIO283QT2=y
CONFIG_LCD=y CONFIG_LCD=y
CONFIG_LCD_MIO283QT2=y
CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_PERROR_STDOUT=y
CONFIG_LIBC_STRERROR=y CONFIG_LIBC_STRERROR=y
CONFIG_MAX_TASKS=16 CONFIG_MAX_TASKS=16
@ -40,13 +40,13 @@ CONFIG_NSH_LIBRARY=y
CONFIG_NSH_LINELEN=64 CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y CONFIG_NSH_READLINE=y
CONFIG_NSH_STRERROR=y CONFIG_NSH_STRERROR=y
CONFIG_NX_BLOCKING=y
CONFIG_NX=y CONFIG_NX=y
CONFIG_NXFONT_SERIF22X28B=y CONFIG_NXFONT_SERIF22X28B=y
CONFIG_NXTK_BORDERCOLOR1=0x8410 CONFIG_NXTK_BORDERCOLOR1=0x8410
CONFIG_NXTK_BORDERCOLOR2=0x4208 CONFIG_NXTK_BORDERCOLOR2=0x4208
CONFIG_NXTK_BORDERCOLOR3=0xc618 CONFIG_NXTK_BORDERCOLOR3=0xc618
CONFIG_NXTK_BORDERWIDTH=3 CONFIG_NXTK_BORDERWIDTH=3
CONFIG_NX_BLOCKING=y
CONFIG_PREALLOC_MQ_MSGS=4 CONFIG_PREALLOC_MQ_MSGS=4
CONFIG_PREALLOC_TIMERS=4 CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=4 CONFIG_PREALLOC_WDOGS=4

14
configs/mikroe-stm32f4/nxlines/defconfig
View File

@ -4,34 +4,34 @@
# CONFIG_EXAMPLES_NXLINES_DEFAULT_COLORS is not set # CONFIG_EXAMPLES_NXLINES_DEFAULT_COLORS is not set
# CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set
# CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PS is not set
# CONFIG_NX_DISABLE_16BPP is not set
# CONFIG_NX_WRITEONLY is not set
# CONFIG_NXFONTS_DISABLE_16BPP is not set # CONFIG_NXFONTS_DISABLE_16BPP is not set
# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set # CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set
# CONFIG_NX_DISABLE_16BPP is not set
# CONFIG_NX_WRITEONLY is not set
# CONFIG_SERIAL is not set # CONFIG_SERIAL is not set
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="mikroe-stm32f4"
CONFIG_ARCH_BOARD_MIKROE_STM32F4=y CONFIG_ARCH_BOARD_MIKROE_STM32F4=y
CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y
CONFIG_ARCH_BOARD="mikroe-stm32f4"
CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F407VG=y
CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm"
CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BOARD_LOOPSPERMSEC=16717
CONFIG_BUILTIN=y CONFIG_BUILTIN=y
CONFIG_DISABLE_POLL=y CONFIG_DISABLE_POLL=y
CONFIG_EXAMPLES_NXLINES=y
CONFIG_EXAMPLES_NXLINES_BGCOLOR=0x0 CONFIG_EXAMPLES_NXLINES_BGCOLOR=0x0
CONFIG_EXAMPLES_NXLINES_BORDERCOLOR=0xFFE0 CONFIG_EXAMPLES_NXLINES_BORDERCOLOR=0xFFE0
CONFIG_EXAMPLES_NXLINES_BPP=16 CONFIG_EXAMPLES_NXLINES_BPP=16
CONFIG_EXAMPLES_NXLINES_CIRCLECOLOR=0x87F0 CONFIG_EXAMPLES_NXLINES_CIRCLECOLOR=0x87F0
CONFIG_EXAMPLES_NXLINES_LINECOLOR=0x861F CONFIG_EXAMPLES_NXLINES_LINECOLOR=0x861F
CONFIG_EXAMPLES_NXLINES=y
CONFIG_HAVE_CXX=y CONFIG_HAVE_CXX=y
CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HAVE_CXXINITIALIZE=y
CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_IDLETHREAD_STACKSIZE=2048
CONFIG_INTELHEX_BINARY=y CONFIG_INTELHEX_BINARY=y
CONFIG_LCD=y
CONFIG_LCD_MIO283QT2=y CONFIG_LCD_MIO283QT2=y
CONFIG_LCD_NOGETRUN=y CONFIG_LCD_NOGETRUN=y
CONFIG_LCD=y
CONFIG_MAX_TASKS=16 CONFIG_MAX_TASKS=16
CONFIG_MAX_WDOGPARMS=2 CONFIG_MAX_WDOGPARMS=2
CONFIG_MM_REGIONS=2 CONFIG_MM_REGIONS=2
@ -44,13 +44,13 @@ CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LIBRARY=y CONFIG_NSH_LIBRARY=y
CONFIG_NSH_LINELEN=64 CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y CONFIG_NSH_READLINE=y
CONFIG_NX_BLOCKING=y
CONFIG_NX=y CONFIG_NX=y
CONFIG_NXFONT_SERIF22X28B=y CONFIG_NXFONT_SERIF22X28B=y
CONFIG_NXTK_BORDERCOLOR1=0x8410 CONFIG_NXTK_BORDERCOLOR1=0x8410
CONFIG_NXTK_BORDERCOLOR2=0x4208 CONFIG_NXTK_BORDERCOLOR2=0x4208
CONFIG_NXTK_BORDERCOLOR3=0xc618 CONFIG_NXTK_BORDERCOLOR3=0xc618
CONFIG_NXTK_BORDERWIDTH=3 CONFIG_NXTK_BORDERWIDTH=3
CONFIG_NX_BLOCKING=y
CONFIG_PREALLOC_MQ_MSGS=4 CONFIG_PREALLOC_MQ_MSGS=4
CONFIG_PREALLOC_TIMERS=4 CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=4 CONFIG_PREALLOC_WDOGS=4

12
configs/mikroe-stm32f4/nxtext/defconfig
View File

@ -3,29 +3,29 @@
# CONFIG_DEV_NULL is not set # CONFIG_DEV_NULL is not set
# CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set
# CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PS is not set
# CONFIG_NX_DISABLE_16BPP is not set
# CONFIG_NXFONTS_DISABLE_16BPP is not set # CONFIG_NXFONTS_DISABLE_16BPP is not set
# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set # CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set
# CONFIG_NX_DISABLE_16BPP is not set
# CONFIG_SERIAL is not set # CONFIG_SERIAL is not set
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="mikroe-stm32f4"
CONFIG_ARCH_BOARD_MIKROE_STM32F4=y CONFIG_ARCH_BOARD_MIKROE_STM32F4=y
CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y
CONFIG_ARCH_BOARD="mikroe-stm32f4"
CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F407VG=y
CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm"
CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BOARD_LOOPSPERMSEC=16717
CONFIG_BUILTIN=y CONFIG_BUILTIN=y
CONFIG_DEBUG_SYMBOLS=y CONFIG_DEBUG_SYMBOLS=y
CONFIG_DISABLE_POLL=y CONFIG_DISABLE_POLL=y
CONFIG_EXAMPLES_NXTEXT_BPP=16
CONFIG_EXAMPLES_NXTEXT=y CONFIG_EXAMPLES_NXTEXT=y
CONFIG_EXAMPLES_NXTEXT_BPP=16
CONFIG_HAVE_CXX=y CONFIG_HAVE_CXX=y
CONFIG_HAVE_CXXINITIALIZE=y CONFIG_HAVE_CXXINITIALIZE=y
CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_IDLETHREAD_STACKSIZE=2048
CONFIG_INTELHEX_BINARY=y CONFIG_INTELHEX_BINARY=y
CONFIG_LCD_MIO283QT2=y
CONFIG_LCD=y CONFIG_LCD=y
CONFIG_LCD_MIO283QT2=y
CONFIG_MAX_TASKS=16 CONFIG_MAX_TASKS=16
CONFIG_MAX_WDOGPARMS=2 CONFIG_MAX_WDOGPARMS=2
CONFIG_MM_REGIONS=2 CONFIG_MM_REGIONS=2
@ -38,13 +38,13 @@ CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LIBRARY=y CONFIG_NSH_LIBRARY=y
CONFIG_NSH_LINELEN=64 CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y CONFIG_NSH_READLINE=y
CONFIG_NX_BLOCKING=y
CONFIG_NX=y CONFIG_NX=y
CONFIG_NXFONT_SERIF22X28B=y CONFIG_NXFONT_SERIF22X28B=y
CONFIG_NXTK_BORDERCOLOR1=0x8410 CONFIG_NXTK_BORDERCOLOR1=0x8410
CONFIG_NXTK_BORDERCOLOR2=0x4208 CONFIG_NXTK_BORDERCOLOR2=0x4208
CONFIG_NXTK_BORDERCOLOR3=0xc618 CONFIG_NXTK_BORDERCOLOR3=0xc618
CONFIG_NXTK_BORDERWIDTH=3 CONFIG_NXTK_BORDERWIDTH=3
CONFIG_NX_BLOCKING=y
CONFIG_PREALLOC_MQ_MSGS=4 CONFIG_PREALLOC_MQ_MSGS=4
CONFIG_PREALLOC_TIMERS=4 CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=4 CONFIG_PREALLOC_WDOGS=4

1
configs/mikroe-stm32f4/scripts/kernel-space.ld
View File

@ -38,6 +38,7 @@
*/ */
OUTPUT_ARCH(arm) OUTPUT_ARCH(arm)
EXTERN(_vectors)
ENTRY(_stext) ENTRY(_stext)
SECTIONS SECTIONS
{ {

1
configs/mikroe-stm32f4/scripts/ld.script
View File

@ -53,6 +53,7 @@ MEMORY
} }
OUTPUT_ARCH(arm) OUTPUT_ARCH(arm)
EXTERN(_vectors)
ENTRY(_stext) ENTRY(_stext)
SECTIONS SECTIONS
{ {

18
configs/mikroe-stm32f4/usbnsh/defconfig
View File

@ -3,25 +3,25 @@
# CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set
# CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PS is not set
# CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_CALLBACK is not set
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="mikroe-stm32f4"
CONFIG_ARCH_BOARD_MIKROE_STM32F4=y CONFIG_ARCH_BOARD_MIKROE_STM32F4=y
CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y
CONFIG_ARCH_BOARD="mikroe-stm32f4"
CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32=y
CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F407VG=y
CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm"
CONFIG_BOARD_LOOPSPERMSEC=16717
CONFIG_BOARDCTL_USBDEVCTRL=y CONFIG_BOARDCTL_USBDEVCTRL=y
CONFIG_BOARD_LOOPSPERMSEC=16717
CONFIG_BUILTIN=y CONFIG_BUILTIN=y
CONFIG_CDCACM=y
CONFIG_CDCACM_CONSOLE=y CONFIG_CDCACM_CONSOLE=y
CONFIG_CDCACM_RXBUFSIZE=256 CONFIG_CDCACM_RXBUFSIZE=256
CONFIG_CDCACM_TXBUFSIZE=256 CONFIG_CDCACM_TXBUFSIZE=256
CONFIG_CDCACM=y
CONFIG_DEV_LOOP=y CONFIG_DEV_LOOP=y
CONFIG_DEV_ZERO=y CONFIG_DEV_ZERO=y
CONFIG_DISABLE_POLL=y CONFIG_DISABLE_POLL=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_EXAMPLES_NSH=y CONFIG_EXAMPLES_NSH=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_FS_FAT=y CONFIG_FS_FAT=y
CONFIG_FS_ROMFS=y CONFIG_FS_ROMFS=y
CONFIG_HAVE_CXX=y CONFIG_HAVE_CXX=y
@ -35,12 +35,12 @@ CONFIG_M25P_MEMORY_TYPE=0x31
CONFIG_M25P_SUBSECTOR_ERASE=y CONFIG_M25P_SUBSECTOR_ERASE=y
CONFIG_MAX_TASKS=16 CONFIG_MAX_TASKS=16
CONFIG_MAX_WDOGPARMS=2 CONFIG_MAX_WDOGPARMS=2
CONFIG_MIKROE_FLASH_PART_LIST="256,768"
CONFIG_MIKROE_FLASH_PART=y
CONFIG_MIKROE_FLASH=y CONFIG_MIKROE_FLASH=y
CONFIG_MIKROE_FLASH_PART=y
CONFIG_MIKROE_FLASH_PART_LIST="256,768"
CONFIG_MIKROE_RAMMTD=y CONFIG_MIKROE_RAMMTD=y
CONFIG_MM_REGIONS=2
CONFIG_MMCSD=y CONFIG_MMCSD=y
CONFIG_MM_REGIONS=2
CONFIG_MTD_PARTITION=y CONFIG_MTD_PARTITION=y
CONFIG_MTD_SMART_SECTOR_SIZE=512 CONFIG_MTD_SMART_SECTOR_SIZE=512
CONFIG_NFILE_DESCRIPTORS=8 CONFIG_NFILE_DESCRIPTORS=8
@ -54,9 +54,9 @@ CONFIG_NSH_STRERROR=y
CONFIG_PREALLOC_MQ_MSGS=4 CONFIG_PREALLOC_MQ_MSGS=4
CONFIG_PREALLOC_TIMERS=4 CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=8 CONFIG_PREALLOC_WDOGS=8
CONFIG_RAMDISK=y
CONFIG_RAM_SIZE=114688 CONFIG_RAM_SIZE=114688
CONFIG_RAM_START=0x20000000 CONFIG_RAM_START=0x20000000
CONFIG_RAMDISK=y
CONFIG_RAW_BINARY=y CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200 CONFIG_RR_INTERVAL=200
CONFIG_SCHED_WAITPID=y CONFIG_SCHED_WAITPID=y

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