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arch/arm/src/stm32l4/stm32l4_usbdev.c: add missing PWR USBV enable, correct two USB register bits

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This commit is contained in:
Juha Niskanen 2019-05-14 06:32:07 -06:00 committed by Gregory Nutt
parent 8905bd6fa6
commit 8bf2e45b6c
3 changed files with 37 additions and 22 deletions
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45
arch/arm/src/stm32l4/chip/stm32l4_usbdev.h
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@ -90,29 +90,29 @@
/* Endpoint Registers */
#define STM32L4_USB_EPR(n) (STM32L4_USB_FS_BASE+STM32L4_USB_EPR_OFFSET(n))
#define STM32L4_USB_EP0R (STM32L4_USB_FS_BASE+STM32L4_USB_EP0R_OFFSET)
#define STM32L4_USB_EP1R (STM32L4_USB_FS_BASE+STM32L4_USB_EP1R_OFFSET)
#define STM32L4_USB_EP2R (STM32L4_USB_FS_BASE+STM32L4_USB_EP2R_OFFSET)
#define STM32L4_USB_EP3R (STM32L4_USB_FS_BASE+STM32L4_USB_EP3R_OFFSET)
#define STM32L4_USB_EP4R (STM32L4_USB_FS_BASE+STM32L4_USB_EP4R_OFFSET)
#define STM32L4_USB_EP5R (STM32L4_USB_FS_BASE+STM32L4_USB_EP5R_OFFSET)
#define STM32L4_USB_EP6R (STM32L4_USB_FS_BASE+STM32L4_USB_EP6R_OFFSET)
#define STM32L4_USB_EP7R (STM32L4_USB_FS_BASE+STM32L4_USB_EP7R_OFFSET)
#define STM32L4_USB_EPR(n) (STM32L4_USB_FS_BASE + STM32L4_USB_EPR_OFFSET(n))
#define STM32L4_USB_EP0R (STM32L4_USB_FS_BASE + STM32L4_USB_EP0R_OFFSET)
#define STM32L4_USB_EP1R (STM32L4_USB_FS_BASE + STM32L4_USB_EP1R_OFFSET)
#define STM32L4_USB_EP2R (STM32L4_USB_FS_BASE + STM32L4_USB_EP2R_OFFSET)
#define STM32L4_USB_EP3R (STM32L4_USB_FS_BASE + STM32L4_USB_EP3R_OFFSET)
#define STM32L4_USB_EP4R (STM32L4_USB_FS_BASE + STM32L4_USB_EP4R_OFFSET)
#define STM32L4_USB_EP5R (STM32L4_USB_FS_BASE + STM32L4_USB_EP5R_OFFSET)
#define STM32L4_USB_EP6R (STM32L4_USB_FS_BASE + STM32L4_USB_EP6R_OFFSET)
#define STM32L4_USB_EP7R (STM32L4_USB_FS_BASE + STM32L4_USB_EP7R_OFFSET)
/* Common Registers */
#define STM32L4_USB_CNTR (STM32L4_USB_FS_BASE+STM32L4_USB_CNTR_OFFSET)
#define STM32L4_USB_ISTR (STM32L4_USB_FS_BASE+STM32L4_USB_ISTR_OFFSET)
#define STM32L4_USB_FNR (STM32L4_USB_FS_BASE+STM32L4_USB_FNR_OFFSET)
#define STM32L4_USB_DADDR (STM32L4_USB_FS_BASE+STM32L4_USB_DADDR_OFFSET)
#define STM32L4_USB_BTABLE (STM32L4_USB_FS_BASE+STM32L4_USB_BTABLE_OFFSET)
#define STM32L4_USB_LPMCSR (STM32L4_USB_FS_BASE+STM32L4_USB_LPMCSR_OFFSET)
#define STM32L4_USB_BCDR (STM32L4_USB_FS_BASE+STM32L4_USB_BCDR_OFFSET)
#define STM32L4_USB_CNTR (STM32L4_USB_FS_BASE + STM32L4_USB_CNTR_OFFSET)
#define STM32L4_USB_ISTR (STM32L4_USB_FS_BASE + STM32L4_USB_ISTR_OFFSET)
#define STM32L4_USB_FNR (STM32L4_USB_FS_BASE + STM32L4_USB_FNR_OFFSET)
#define STM32L4_USB_DADDR (STM32L4_USB_FS_BASE + STM32L4_USB_DADDR_OFFSET)
#define STM32L4_USB_BTABLE (STM32L4_USB_FS_BASE + STM32L4_USB_BTABLE_OFFSET)
#define STM32L4_USB_LPMCSR (STM32L4_USB_FS_BASE + STM32L4_USB_LPMCSR_OFFSET)
#define STM32L4_USB_BCDR (STM32L4_USB_FS_BASE + STM32L4_USB_BCDR_OFFSET)
/* Buffer Descriptor Table (Relatative to BTABLE address) */
#define STM32L4_USB_BTABLE_ADDR(ep,o) (STM32L4_USB_SRAM_BASE+STM32L4_USB_BTABLE_RADDR(ep,o))
#define STM32L4_USB_BTABLE_ADDR(ep,o) (STM32L4_USB_SRAM_BASE + STM32L4_USB_BTABLE_RADDR(ep,o))
#define STM32L4_USB_ADDR_TX(ep) STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_ADDR_TX_WOFFSET)
#define STM32L4_USB_COUNT_TX(ep) STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_COUNT_TX_WOFFSET)
#define STM32L4_USB_ADDR_RX(ep) STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_ADDR_RX_WOFFSET)
@ -171,8 +171,9 @@
#define USB_CNTR_PMAOVRNM (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun Interrupt Mask */
#define USB_CNTR_CTRM (1 << 15) /* Bit 15: Correct Transfer Interrupt Mask */
#define USB_CNTR_ALLINTS (USB_CNTR_ESOFM|USB_CNTR_SOFM|USB_CNTR_RESETM|USB_CNTR_SUSPM|\
USB_CNTR_WKUPM|USB_CNTR_ERRM|USB_CNTR_PMAOVRNM|USB_CNTR_CTRM)
#define USB_CNTR_ALLINTS (USB_CNTR_L1REQM | USB_CNTR_ESOFM|USB_CNTR_SOFM | USB_CNTR_RESETM | \
USB_CNTR_SUSPM | USB_CNTR_WKUPM | USB_CNTR_ERRM | USB_CNTR_PMAOVRNM | \
USB_CNTR_CTRM)
/* USB interrupt status register */
@ -189,8 +190,8 @@
#define USB_ISTR_PMAOVRN (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun */
#define USB_ISTR_CTR (1 << 15) /* Bit 15: Correct Transfer */
#define USB_ISTR_ALLINTS (USB_ISTR_L1REQ|USB_ISTR_ESOF|USB_ISTR_SOF|USB_ISTR_RESET|\
USB_ISTR_SUSP|USB_ISTR_WKUP|USB_ISTR_ERR|USB_ISTR_PMAOVRN|\
#define USB_ISTR_ALLINTS (USB_ISTR_L1REQ | USB_ISTR_ESOF | USB_ISTR_SOF | USB_ISTR_RESET | \
USB_ISTR_SUSP | USB_ISTR_WKUP | USB_ISTR_ERR | USB_ISTR_PMAOVRN | \
USB_ISTR_CTR)
/* USB frame number register */
@ -243,7 +244,7 @@
#define USB_LPMCSR_LPMEN (1 << 0) /* Bit 0: LPM support enable */
#define USB_LPMCSR_LPMACK (1 << 1) /* Bit 1: LPM Token acknowledge enable */
#define USB_LPMCSR_REMWAKE (1 << 2) /* Bit 2: bRemoteWake value */
#define USB_LPMCSR_REMWAKE (1 << 3) /* Bit 3: bRemoteWake value */
#define USB_LPMCSR_BESL_SHIFT (4) /* Bits 7-4: BESL value */
#define USB_LPMCSR_BESL_MASK (0x0f << USB_LPMCSR_BESL_SHIFT)

5
arch/arm/src/stm32l4/chip/stm32l4x3xx_pinmap.h
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@ -598,4 +598,9 @@
#define GPIO_LPUART1_RTS_DE_1 (GPIO_ALT|GPIO_AF8 |GPIO_PORTB|GPIO_PIN1)
#define GPIO_LPUART1_RTS_DE_2 (GPIO_ALT|GPIO_AF8 |GPIO_PORTB|GPIO_PIN12)
/* USB */
#define GPIO_USB_DM (GPIO_ALT|GPIO_AF10|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN11)
#define GPIO_USB_DP (GPIO_ALT|GPIO_AF10|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN12)
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X3XX_PINMAP_H */

9
arch/arm/src/stm32l4/stm32l4_usbdev.c
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@ -3694,6 +3694,10 @@ void up_usbinitialize(void)
usbtrace(TRACE_DEVINIT, 0);
stm32l4_checksetup();
/* Enable Vbus monitoring in the Power control */
stm32l4_pwr_enableusv(true);
/* Power up the USB controller, but leave it in the reset state */
stm32l4_hwsetup(priv);
@ -3746,6 +3750,11 @@ void up_usbuninitialize(void)
/* Put the hardware in an inactive state */
stm32l4_hwshutdown(priv);
/* Disable Vbus monitoring in the Power control */
stm32l4_pwr_enableusv(false);
leave_critical_section(flags);
}