XMC4xxx: Finishes implementation of GPIO support.
This commit is contained in:
Gregory Nutt
parent
41758d8e4c
commit
8bfb735351
@ -148,6 +148,7 @@
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#define XMC4_USIC2_CH0_BASE 0x48024000
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#define XMC4_USIC2_CH1_BASE 0x48024200
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#define XMC4_USIC2_RAM_BASE 0x48024400
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#define XMC4_PORT_BASE(n) (0x48028000 + ((n) << 8))
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#define XMC4_PORT0_BASE 0x48028000
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#define XMC4_PORT1_BASE 0x48028100
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#define XMC4_PORT2_BASE 0x48028200
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@ -58,6 +58,8 @@
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#include <nuttx/config.h>
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#include "chip/xmc4_memorymap.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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@ -68,13 +70,19 @@
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#define XMC4_PORT_OUT_OFFSET 0x0000 /* Port Output Register */
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#define XMC4_PORT_OMR_OFFSET 0x0004 /* Port Output Modification Register */
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#define XMC4_PORT_IOCR_OFFSET(n) (0x0010 + ((n) & 3))
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#define XMC4_PORT_IOCR0_OFFSET 0x0010 /* Port Input/Output Control Register 0 */
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#define XMC4_PORT_IOCR4_OFFSET 0x0014 /* Port Input/Output Control Register 4 */
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#define XMC4_PORT_IOCR8_OFFSET 0x0018 /* Port Input/Output Control Register 8 */
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#define XMC4_PORT_IOCR12_OFFSET 0x001c /* Port Input/Output Control Register 12 */
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#define XMC4_PORT_IN_OFFSET 0x0024 /* Port Input Register */
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#define XMC4_PORT_PDR_OFFSET(n) (0x0010 + (((n) >> 1) & 3))
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#define XMC4_PORT_PDR0_OFFSET 0x0040 /* Port Pad Driver Mode 0 Register */
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#define XMC4_PORT_PDR1_OFFSET 0x0044 /* Port Pad Driver Mode 1 Register */
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#define XMC4_PORT_PDISC_OFFSET 0x0060 /* Port Pin Function Decision Control Register */
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#define XMC4_PORT_PPS_OFFSET 0x0070 /* Port Pin Power Save Register */
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#define XMC4_PORT_HWSEL_OFFSET 0x0074 /* Port Pin Hardware Select Register */
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@ -44,6 +44,7 @@
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#include <errno.h>
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#include <nuttx/arch.h>
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#include <nuttx/irq.h>
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#include "up_arch.h"
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#include "up_internal.h"
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@ -51,6 +52,301 @@
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#include "chip/xmc4_ports.h"
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#include "xmc4_gpio.h"
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: xmc4_gpio_getreg
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*
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* Description:
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* Return the pin number for this pin configuration
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*
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****************************************************************************/
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static inline uint32_t xmc4_gpio_getreg(uintptr_t portbase,
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unsigned int offset)
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{
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return getreg32(portbase + offset);
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}
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/****************************************************************************
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* Name: xmc4_gpio_putreg
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*
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* Description:
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* Return the pin number for this pin configuration
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*
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****************************************************************************/
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static inline void xmc4_gpio_putreg(uintptr_t portbase, unsigned int offset,
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uint32_t regval)
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{
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putreg32(regval, portbase + offset);
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}
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/****************************************************************************
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* Name: xmc4_gpio_port
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*
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* Description:
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* Return the port number for this pin configuration
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*
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****************************************************************************/
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static inline int xmc4_gpio_port(gpioconfig_t pinconfig)
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{
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return ((pinconfig & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT);
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}
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/****************************************************************************
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* Name: xmc4_gpio_portbase
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*
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* Description:
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* Return the base address of the port register for this pin configuration.
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*
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****************************************************************************/
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static uintptr_t xmc4_gpio_portbase(gpioconfig_t pinconfig)
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{
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return XMC4_PORT_BASE(xmc4_gpio_port(pinconfig));
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}
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/****************************************************************************
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* Name: xmc4_gpio_pin
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*
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* Description:
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* Return the pin number for this pin configuration
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*
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****************************************************************************/
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static unsigned int xmc4_gpio_pin(gpioconfig_t pinconfig)
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{
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return ((pinconfig & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT);
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}
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/****************************************************************************
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* Name: xmc4_gpio_pintype
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*
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* Description:
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* Return the pintype for this pin configuration
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*
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****************************************************************************/
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static inline unsigned int xmc4_gpio_pintype(gpioconfig_t pinconfig)
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{
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return ((pinconfig & GPIO_PINTYPE_MASK) >> GPIO_PINTYPE_SHIFT);
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}
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/****************************************************************************
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* Name: xmc4_gpio_pinctrl
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*
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* Description:
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* Return the pintype for this pin configuration
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*
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****************************************************************************/
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static inline unsigned int xmc4_gpio_pinctrl(gpioconfig_t pinconfig)
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{
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return ((pinconfig & GPIO_PINCTRL_MASK) >> GPIO_PINCTRL_SHIFT);
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}
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/****************************************************************************
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* Name: xmc4_gpio_padtype
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*
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* Description:
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* Return the padtype for this pin configuration
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*
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****************************************************************************/
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static inline unsigned int xmc4_gpio_padtype(gpioconfig_t pinconfig)
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{
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return ((pinconfig & GPIO_PADTYPE_MASK) >> GPIO_PADTYPE_SHIFT);
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}
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/****************************************************************************
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* Name: xmc4_gpio_iocr
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*
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* Description:
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* Update the IOCR register
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*
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****************************************************************************/
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static void xmc4_gpio_iocr(uintptr_t portbase, unsigned int pin,
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unsigned int value)
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{
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uint32_t regval;
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uint32_t mask;
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unsigned int offset;
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unsigned int shift;
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/* Read the IOCR register */
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offset = XMC4_PORT_IOCR_OFFSET(pin);
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regval = xmc4_gpio_getreg(portbase, offset);
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/* Set the new value for this field */
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pin &= 3;
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shift = PORT_IOCR0_PC_SHIFT(pin);
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mask = PORT_IOCR0_PC_MASK(pin);
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regval &= ~mask;
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regval |= (uint32_t)value << shift;
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xmc4_gpio_putreg(portbase, offset, regval);
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}
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/****************************************************************************
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* Name: xmc4_gpio_hwsel
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*
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* Description:
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* Update the HWSEL register
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*
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****************************************************************************/
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static inline void xmc4_gpio_hwsel(uintptr_t portbase, unsigned int pin,
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unsigned int value)
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{
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uint32_t regval;
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uint32_t mask;
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unsigned int shift;
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/* Read the HWSEL register */
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regval = xmc4_gpio_getreg(portbase, XMC4_PORT_HWSEL_OFFSET);
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/* Set the new value for this field */
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shift = PORT_HWSEL_HW_SHIFT(pin);
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mask = PORT_HWSEL_HW_MASK(pin);
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regval &= ~mask;
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regval |= (uint32_t)value << shift;
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xmc4_gpio_putreg(portbase, XMC4_PORT_HWSEL_OFFSET, regval);
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}
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/****************************************************************************
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* Name: xmc4_gpio_pdisc
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*
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* Description:
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* Update the PDISC register
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*
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****************************************************************************/
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static inline void xmc4_gpio_pdisc(uintptr_t portbase, unsigned int pin,
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bool value)
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{
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uint32_t regval;
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uint32_t mask;
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/* Read the PDISC register */
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regval = xmc4_gpio_getreg(portbase, XMC4_PORT_PDISC_OFFSET);
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/* Set/clear the enable/disable (or analg) value for this field */
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mask = PORT_PIN(pin);
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if (value)
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{
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regval |= mask;
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}
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else
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{
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regval &= ~mask;
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}
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xmc4_gpio_putreg(portbase, XMC4_PORT_PDISC_OFFSET, regval);
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}
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/****************************************************************************
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* Name: xmc4_gpio_pps
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*
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* Description:
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* Update the PPS register
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*
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****************************************************************************/
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static inline void xmc4_gpio_pps(uintptr_t portbase, unsigned int pin,
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bool value)
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{
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uint32_t regval;
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uint32_t mask;
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/* Read the PPS register */
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regval = xmc4_gpio_getreg(portbase, XMC4_PORT_PPS_OFFSET);
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/* Set/clear the enable/disable (or analg) value for this field */
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mask = PORT_PIN(pin);
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if (value)
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{
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regval |= mask;
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}
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else
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{
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regval &= ~mask;
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}
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xmc4_gpio_putreg(portbase, XMC4_PORT_PPS_OFFSET, regval);
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}
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/****************************************************************************
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* Name: xmc4_gpio_pdr
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*
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* Description:
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* Update the IOCR register
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*
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****************************************************************************/
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static void xmc4_gpio_pdr(uintptr_t portbase, unsigned int pin,
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unsigned int value)
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{
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uint32_t regval;
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uint32_t mask;
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unsigned int offset;
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unsigned int shift;
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/* Read the PDRregister */
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offset = XMC4_PORT_PDR_OFFSET(pin);
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regval = xmc4_gpio_getreg(portbase, offset);
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/* Set the new value for this field */
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pin &= 7;
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shift = PORT_PDR0_PD_SHIFT(pin);
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mask = PORT_PDR0_PD_MASK(pin);
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regval &= ~mask;
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regval |= (uint32_t)value << shift;
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xmc4_gpio_putreg(portbase, offset, regval);
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}
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/****************************************************************************
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* Name: xmc4_gpio_inverted
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*
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* Description:
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* Check if the input is inverted
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*
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****************************************************************************/
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static inline bool xmc4_gpio_inverted(gpioconfig_t pinconfig)
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{
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return ((pinconfig & GPIO_INPUT_INVERT) != 0);
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}
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/****************************************************************************
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* Name: xmc4_gpio_opendrain
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*
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* Description:
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* Check if the output is opendram
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*
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****************************************************************************/
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#define xmc4_gpio_opendrain(p) xmc4_gpio_inverted(p)
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@ -66,8 +362,71 @@
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int xmc4_gpio_config(gpioconfig_t pinconfig)
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{
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#warning Missing logic
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return -EINVAL;
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uintptr_t portbase = xmc4_gpio_portbase(pinconfig);
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unsigned int pin = xmc4_gpio_pin(pinconfig);
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unsigned int value;
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irqstate_t flags;
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flags = enter_critical_section();
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if (GPIO_ISINPUT(pinconfig))
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{
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/* Get input pin type (IOCR) */
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value = xmc4_gpio_pintype(pinconfig);
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/* Check if the input is inverted */
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if (xmc4_gpio_inverted(pinconfig))
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{
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value |= IOCR_INPUT_INVERT;
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}
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}
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else
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{
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/* Force input while we configure */
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xmc4_gpio_iocr(portbase, pin, IOCR_INPUT_NOPULL);
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/* Set output value before enabling output */
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xmc4_gpio_write(pinconfig, ((pinconfig & GPIO_OUTPUT_SET) != 0));
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/* Get output pin type (IOCR) */
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value = xmc4_gpio_pintype(pinconfig);
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/* Get if the output is opendrain */
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if (xmc4_gpio_opendrain(pinconfig))
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{
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value |= IOCR_OUTPUT_OPENDRAIN;
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}
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}
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/* Update the IOCR register to instantiate the pin type */
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xmc4_gpio_iocr(portbase, pin, value);
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/* Select pin control (HWSEL) */
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value = xmc4_gpio_pinctrl(pinconfig);
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xmc4_gpio_hwsel(portbase, pin, value);
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/* Select drive strength */
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value = xmc4_gpio_padtype(pinconfig);
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xmc4_gpio_pdr(portbase, pin, value);
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/* Enable/enable pad or Analog only (PDISC) */
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xmc4_gpio_pdisc(portbase, pin, ((pinconfig & GPIO_PAD_DISABLE) != 0));
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/* Make sure pin is not in power save mode (PDR) */
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xmc4_gpio_pdisc(portbase, pin, false);
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leave_critical_section(flags);
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return OK;
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}
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/****************************************************************************
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@ -80,7 +439,28 @@ int xmc4_gpio_config(gpioconfig_t pinconfig)
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void xmc4_gpio_write(gpioconfig_t pinconfig, bool value)
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{
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#warning Missing logic
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uintptr_t portbase = xmc4_gpio_portbase(pinconfig);
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unsigned int pin = xmc4_gpio_pin(pinconfig);
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uint32_t regval;
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uint32_t mask;
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/* Read the OUT register */
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regval = xmc4_gpio_getreg(portbase, XMC4_PORT_OUT_OFFSET);
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/* Set/clear output value for this pin */
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mask = PORT_PIN(pin);
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if (value)
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{
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regval |= mask;
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}
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else
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{
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regval &= ~mask;
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}
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xmc4_gpio_putreg(portbase, XMC4_PORT_OUT_OFFSET, regval);
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}
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/****************************************************************************
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@ -93,6 +473,15 @@ void xmc4_gpio_write(gpioconfig_t pinconfig, bool value)
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bool xmc4_gpio_read(gpioconfig_t pinconfig)
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{
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#warning Missing logic
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return false;
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uintptr_t portbase = xmc4_gpio_portbase(pinconfig);
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unsigned int pin = xmc4_gpio_pin(pinconfig);
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uint32_t regval;
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/* Read the OUT register */
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regval = xmc4_gpio_getreg(portbase, XMC4_PORT_IN_OFFSET);
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/* Return in the input state for this pin */
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return ((regval & PORT_PIN(pin)) != 0);
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}
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@ -50,16 +50,16 @@
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/* 32-bit GIO encoding:
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*
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* .... TTTT TMDD DCC. .... .... PPPP BBBB
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* TTTT TMPD DDCC V.... .... .... PPPP BBBB
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*/
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/* This identifies the GPIO pint type:
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*
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* .... TTTT T... .... .... .... .... ....
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* TTTT T... .... .... .... .... .... ....
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*/
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#define GPIO_PINTYPE_SHIFT (23) /* Bits 23-27: Pin type */
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#define GPIO_PINTYPE_SHIFT (27) /* Bits 27-31: Pin type */
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#define GPIO_PINTYPE_MASK (31 << GPIO_PINTYPE_SHIFT)
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/* See chip/xmc4_ports.h for the IOCR definitions */
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@ -84,60 +84,79 @@
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/* Pin type modifier:
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*
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* .... .... .M.. .... .... .... .... ....
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* .... .M.. .... .... .... .... .... ....
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*/
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#define GPIO_INPUT_INVERT (1 << 22) /* Inverted direct input modifier */
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#define GPIO_INPUT_INVERT (1 << 26) /* Bit 26: Inverted direct input modifier */
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#define GPIOS_OUTPUT_PUSHPULL (0) /* Push-ull output is the default */
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#define GPIOS_OUTPUT_OPENDRAIN (1 << 22) /* Output drain output modifier */
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#define GPIO_OUTPUT_OPENDRAIN (1 << 26) /* Bit 26: Output drain output modifier */
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#define GPIO_OUTPUT_PUSHPULL (0) /* Push-pull output is the default */
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/* Disable PAD:
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*
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* .... ..P. .... ..... .... .... .... ....
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*
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* For P0-P6, the PDISC register is ready only.
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* For P14-P15, the bit setting also selects Analog+Digital or Analog only
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*/
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#define GPIO_PAD_DISABLE (1 << 25) /* Bit 25: Disable Pad (P7-P9) */
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#define GPIO_PAD_ANALOG (1 << 25) /* Bit 25: Analog only (P14-P15) */
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/* Pad driver strength:
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*
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* .... .... ..DD D... .... .... .... ....
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* .... ...D DD.. ..... .... ......... ....
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*/
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#define GPIO_PADTYPE_SHIFT (19) /* Bits 19-21: Pad driver strength */
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#define GPIO_PADTYPE_MASK (7 << GPIO_PADTYPE_SHIFT)
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#define GPIO_PADTYPE_SHIFT (22) /* Bits 22-24: Pad driver strength */
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#define GPIO_PADTYPE_MASK (7 << GPIO_PADTYPE_SHIFT)
|
||||
|
||||
/* See chip/xmc4_ports.h for the PDR definitions */
|
||||
/* Pad class A1: */
|
||||
|
||||
# define GPIO_PADA1_MEDIUM (PDR_PADA1_MEDIUM << GPIO_PADTYPE_SHIFT)
|
||||
# define GPIO_PADA1_WEAK (PDR_PADA1_WEAK << GPIO_PADTYPE_SHIFT)
|
||||
# define GPIO_PADA1_MEDIUM (PDR_PADA1_MEDIUM << GPIO_PADTYPE_SHIFT)
|
||||
# define GPIO_PADA1_WEAK (PDR_PADA1_WEAK << GPIO_PADTYPE_SHIFT)
|
||||
|
||||
/* Pad class A1+: */
|
||||
|
||||
# define GPIO_PADA1P_STRONGSOFT (PDR_PADA1P_STRONGSOFT << GPIO_PADTYPE_SHIFT)
|
||||
# define GPIO_PADA1P_STRONGSLOW (PDR_PADA1P_STRONGSLOW << GPIO_PADTYPE_SHIFT)
|
||||
# define GPIO_PADA1P_MEDIUM (PDR_PADA1P_MEDIUM << GPIO_PADTYPE_SHIFT)
|
||||
# define GPIO_PADA1P_WEAK (PDR_PADA1P_WEAK << GPIO_PADTYPE_SHIFT)
|
||||
# define GPIO_PADA1P_STRONGSOFT (PDR_PADA1P_STRONGSOFT << GPIO_PADTYPE_SHIFT)
|
||||
# define GPIO_PADA1P_STRONGSLOW (PDR_PADA1P_STRONGSLOW << GPIO_PADTYPE_SHIFT)
|
||||
# define GPIO_PADA1P_MEDIUM (PDR_PADA1P_MEDIUM << GPIO_PADTYPE_SHIFT)
|
||||
# define GPIO_PADA1P_WEAK (PDR_PADA1P_WEAK << GPIO_PADTYPE_SHIFT)
|
||||
|
||||
/* Pad class A2: */
|
||||
|
||||
# define GPIO_PADA2_STRONGSHARP (PDR_PADA2_STRONGSHARP << GPIO_PADTYPE_SHIFT)
|
||||
# define GPIO_PADA2_STRONGMEDIUM (PDR_PADA2_STRONGMEDIUM << GPIO_PADTYPE_SHIFT)
|
||||
# define GPIO_PADA2_STRONGSOFT (PDR_PADA2_STRONGSOFT << GPIO_PADTYPE_SHIFT)
|
||||
# define GPIO_PADA2_MEDIUM (PDR_PADA2_MEDIUM << GPIO_PADTYPE_SHIFT)
|
||||
# define GPIO_PADA2_WEAK (PDR_PADA2_WEAK << GPIO_PADTYPE_SHIFT)
|
||||
# define GPIO_PADA2_STRONGSHARP (PDR_PADA2_STRONGSHARP << GPIO_PADTYPE_SHIFT)
|
||||
# define GPIO_PADA2_STRONGMEDIUM (PDR_PADA2_STRONGMEDIUM << GPIO_PADTYPE_SHIFT)
|
||||
# define GPIO_PADA2_STRONGSOFT (PDR_PADA2_STRONGSOFT << GPIO_PADTYPE_SHIFT)
|
||||
# define GPIO_PADA2_MEDIUM (PDR_PADA2_MEDIUM << GPIO_PADTYPE_SHIFT)
|
||||
# define GPIO_PADA2_WEAK (PDR_PADA2_WEAK << GPIO_PADTYPE_SHIFT)
|
||||
|
||||
/* Pin control:
|
||||
*
|
||||
* .... .... .... .CC. .... .... .... ....
|
||||
* .... .... ..CC ..... .... .... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_PINCTRL_SHIFT (17) /* Bits 17-18: Pad driver strength */
|
||||
#define GPIO_PINCTRL_MASK (3 << GPIO_PINCTRL_SHIFT)
|
||||
#define GPIO_PINCTRL_SHIFT (20) /* Bits 20-21: Pad driver strength */
|
||||
#define GPIO_PINCTRL_MASK (3 << GPIO_PINCTRL_SHIFT)
|
||||
|
||||
/* See chip/xmc4_ports.h for the PDR definitions */
|
||||
|
||||
# define GPIO_PINCTRL_SOFTWARE (HWSEL_SOFTWARE << GPIO_PINCTRL_SHIFT)
|
||||
# define GPIO_PINCTRL_OVERRIDE0 (HWSEL_OVERRIDE0 << GPIO_PINCTRL_SHIFT)
|
||||
# define GPIO_PINCTRL_OVERRIDE1 (HWSEL_OVERRIDE1 << GPIO_PINCTRL_SHIFT)
|
||||
# define GPIO_PINCTRL_SOFTWARE (HWSEL_SOFTWARE << GPIO_PINCTRL_SHIFT)
|
||||
# define GPIO_PINCTRL_OVERRIDE0 (HWSEL_OVERRIDE0 << GPIO_PINCTRL_SHIFT)
|
||||
# define GPIO_PINCTRL_OVERRIDE1 (HWSEL_OVERRIDE1 << GPIO_PINCTRL_SHIFT)
|
||||
|
||||
/* If the pin is an GPIO output, then this identifies the initial output value:
|
||||
*
|
||||
* .... .... .... V.... .... .... PPPP BBBB
|
||||
*/
|
||||
|
||||
#define GPIO_OUTPUT_SET (1 << 19) /* Bit 19: Initial value of output */
|
||||
#define GPIO_OUTPUT_CLEAR (0)
|
||||
|
||||
/* This identifies the GPIO port:
|
||||
*
|
||||
* .... ... .... .... .... .... PPPP ....
|
||||
* .... .... .... .... .... .... PPPP ....
|
||||
*/
|
||||
|
||||
#define GPIO_PORT_SHIFT (4) /* Bit 4-7: Port number */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user