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arch/z80/src/ez80: Fix eZ80F92 Interrupt Controller

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The eZ80F92 interrupt controller is very different from the eZ80F91.  The eZ80F91 has:

1. Four byte interrupt vectors
2. The vector base address register is 16-bit so the vector table can lie in RAM

Whereas the eZ80F92 has:

1. Two byte interrupt vectors
2. An 8-bit vector base address

This means that the vectors must lie in the first 16-bits of FLASH and there must be a "trampoline" to get to interrupt handlers outside of the first 64-Kb of FLASH.
This commit is contained in:
Gregory Nutt 2020-02-28 12:34:23 -06:00 committed by Ouss4
parent 774bd6f0fc
commit 8c00e43c1a
7 changed files with 214 additions and 81 deletions
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63
arch/z80/src/ez80/ez80_vectors.asm
View File

@ -37,9 +37,7 @@
; Constants
;**************************************************************************
NVECTORS EQU 64 ; max possible interrupt vectors
;* Bits in the Z80 FLAGS register *****************************************
; Bits in the Z80 FLAGS register *****************************************
EZ80_C_FLAG EQU 01h ; Bit 0: Carry flag
EZ80_N_FLAG EQU 02h ; Bit 1: Add/Subtract flag
@ -52,8 +50,6 @@ EZ80_S_FLAG EQU 80h ; Bit 7: Sign flag
; Global Symbols Imported
;**************************************************************************
xref _ez80_handlers
xref _handlersize
xref _ez80_startup
xref _z80_doirq
@ -62,10 +58,7 @@ EZ80_S_FLAG EQU 80h ; Bit 7: Sign flag
;**************************************************************************
xdef _ez80_reset
xdef _ez80_initvectors
xdef _ez80_rstcommon
xdef _ez80_initvectors
xdef _ez80_vectable
;**************************************************************************
; Macros
@ -199,58 +192,4 @@ _ez80_rstcommon:
nointenable:
ex af, af' ; Restore AF
reti
;**************************************************************************
; Vector Setup Logic
;**************************************************************************
_ez80_initvectors:
; Initialize the vector table
ld iy, _ez80_vectable
ld ix, 4
ld bc, 4
ld b, NVECTORS
xor a, a ; Clear carry
ld de, _handlersize ; Length of one irq handler in de
ld hl, _ez80_handlers ; Start of handlers in hl
ld a, 0
$1:
ld (iy), hl ; Store IRQ handler
ld (iy+3), a ; Pad to 4 bytes
add hl, de ; Point to next handler
push de
ld de, 4
add iy, de ; Point to next entry in vector table
pop de
djnz $1 ; Loop until all vectors have been written
; Select interrupt mode 2
im 2 ; Interrupt mode 2
; Write the address of the vector table into the interrupt vector base
ld hl, _ez80_vectable >> 8
ld i, hl
ret
;**************************************************************************
; Vector Table
;**************************************************************************
; This segment must be aligned on a 512 byte boundary anywhere in RAM
; Each entry will be a 3-byte address in a 4-byte space
define .IVECTS, space = RAM, align = 200h
segment .IVECTS
; The first 64 bytes are not used... the vectors actually start at +0x40
_ez80_vecreserve:
ds 64
_ez80_vectable:
ds NVECTORS * 4
end

76
arch/z80/src/ez80/ez80f91_handlers.asm
View File

@ -36,8 +36,13 @@ EZ80_UNUSED EQU 40h
; Global Symbols Exported
;**************************************************************************
xdef _ez80_handlers
xdef _handlersize
xdef _ez80_initvectors
;**************************************************************************
; Constants
;**************************************************************************
NVECTORS EQU 64 ; max possible interrupt vectors
;**************************************************************************
; Macros
@ -130,4 +135,71 @@ _ez80_handlers:
irqhandler EZ80_UNUSED+15 ; 61 0x134
irqhandler EZ80_UNUSED+16 ; 62 0x138
irqhandler EZ80_UNUSED+17 ; 63 0x13c
;**************************************************************************
; Vector Setup Logic
;**************************************************************************
; Still in .STARTUP section
_ez80_initvectors:
; Initialize the vector table
ld iy, _ez80_vectable
ld ix, 4
ld bc, 4
ld b, NVECTORS
xor a, a ; Clear carry; Set A to zero
ld de, _handlersize ; Length of one irq handler in DE
ld hl, _ez80_handlers ; Start of handlers in HL
; "The size of I register is modified to 16 bits in the eZ80F91 device
; differing from the previous versions of eZ80® CPU, to allow for a 16
; MB range of interrupt vector table placement.
;
; "Additionally, the size of the IVECT register is increased from 8 bits
; to 9 bits to provide an interrupt vector table that is expanded and
; more easily integrated with other interrupts.
;
; "The vectors are 4 bytes (32 bits) apart, even though only 3 bytes
; (24 bits) are required. A fourth byte is implemented for both
; programmability and expansion purposes."
$1:
ld (iy), hl ; Store IRQ handler
ld (iy+3), a ; Pad with zero to 4 bytes
add hl, de ; Point to next handler
push de
ld de, 4
add iy, de ; Point to next entry in vector table
pop de
djnz $1 ; Loop until all vectors have been written
; Select interrupt mode 2
im 2 ; Interrupt mode 2
; Write the address of the vector table into the interrupt vector base
ld hl, _ez80_vectable >> 8
ld i, hl
ret
;**************************************************************************
; Vector Table
;**************************************************************************
; This segment must be aligned on a 512 byte boundary anywhere in RAM
; Each entry will be a 3-byte address in a 4-byte space
define .IVECTS, space = RAM, align = 200h
segment .IVECTS
; The first 64 bytes are not used... the vectors actually start at +0x40
_ez80_vecreserve:
ds 64
_ez80_vectable:
ds NVECTORS * 2
end

117
arch/z80/src/ez80/ez80f92_handlers.asm
View File

@ -36,8 +36,13 @@ EZ80_UNUSED EQU 40h
; Global Symbols Exported
;**************************************************************************
xdef _ez80_handlers
xdef _handlersize
xdef _ez80_initvectors
;**************************************************************************
; Constants
;**************************************************************************
NVECTORS EQU 64 ; max possible interrupt vectors
;**************************************************************************
; Macros
@ -54,12 +59,93 @@ irqhandler: macro vectno
jp _ez80_rstcommon ; Remaining RST handling is common
endmac irqhandler
;**************************************************************************
; Vector Table
;**************************************************************************
; This segment must be aligned on a 256 byte boundary anywhere in RAM
; Each entry will be a 2-byte address in a 2-byte space
define .IVECTS, space = RAM, align = 100h
segment .IVECTS
; Vector table is a 2-bit address. The MSB is the I register; the LSB is
; the vector number. The vector table lies in FLASH. The addresses
; contained in the refers to an entry in the handler table that re-
; directs the interrupt to common interrupt handling logic.
_ez80_vectable:
dw _ez80_handlers + 0*_handlersize
dw _ez80_handlers + 1*_handlersize
dw _ez80_handlers + 2*_handlersize
dw _ez80_handlers + 3*_handlersize
dw _ez80_handlers + 4*_handlersize
dw _ez80_handlers + 5*_handlersize
dw _ez80_handlers + 6*_handlersize
dw _ez80_handlers + 7*_handlersize
dw _ez80_handlers + 8*_handlersize
dw _ez80_handlers + 9*_handlersize
dw _ez80_handlers + 10*_handlersize
dw _ez80_handlers + 11*_handlersize
dw _ez80_handlers + 12*_handlersize
dw _ez80_handlers + 13*_handlersize
dw _ez80_handlers + 14*_handlersize
dw _ez80_handlers + 15*_handlersize
dw _ez80_handlers + 16*_handlersize
dw _ez80_handlers + 17*_handlersize
dw _ez80_handlers + 18*_handlersize
dw _ez80_handlers + 19*_handlersize
dw _ez80_handlers + 20*_handlersize
dw _ez80_handlers + 21*_handlersize
dw _ez80_handlers + 22*_handlersize
dw _ez80_handlers + 23*_handlersize
dw _ez80_handlers + 24*_handlersize
dw _ez80_handlers + 25*_handlersize
dw _ez80_handlers + 26*_handlersize
dw _ez80_handlers + 27*_handlersize
dw _ez80_handlers + 28*_handlersize
dw _ez80_handlers + 29*_handlersize
dw _ez80_handlers + 30*_handlersize
dw _ez80_handlers + 31*_handlersize
dw _ez80_handlers + 32*_handlersize
dw _ez80_handlers + 33*_handlersize
dw _ez80_handlers + 34*_handlersize
dw _ez80_handlers + 35*_handlersize
dw _ez80_handlers + 36*_handlersize
dw _ez80_handlers + 37*_handlersize
dw _ez80_handlers + 38*_handlersize
dw _ez80_handlers + 39*_handlersize
dw _ez80_handlers + 40*_handlersize
dw _ez80_handlers + 41*_handlersize
dw _ez80_handlers + 42*_handlersize
dw _ez80_handlers + 43*_handlersize
dw _ez80_handlers + 44*_handlersize
dw _ez80_handlers + 45*_handlersize
dw _ez80_handlers + 46*_handlersize
dw _ez80_handlers + 47*_handlersize
dw _ez80_handlers + 48*_handlersize
dw _ez80_handlers + 49*_handlersize
dw _ez80_handlers + 50*_handlersize
dw _ez80_handlers + 51*_handlersize
dw _ez80_handlers + 52*_handlersize
dw _ez80_handlers + 53*_handlersize
dw _ez80_handlers + 54*_handlersize
dw _ez80_handlers + 55*_handlersize
dw _ez80_handlers + 56*_handlersize
dw _ez80_handlers + 57*_handlersize
dw _ez80_handlers + 58*_handlersize
dw _ez80_handlers + 59*_handlersize
dw _ez80_handlers + 60*_handlersize
dw _ez80_handlers + 61*_handlersize
dw _ez80_handlers + 62*_handlersize
dw _ez80_handlers + 63*_handlersize
;**************************************************************************
; Interrupt Vector Handlers
;**************************************************************************
define .STARTUP, space = ROM
segment .STARTUP
; Still in .IVECTS section
.assume ADL=1
; Symbol Val VecNo Addr
@ -130,4 +216,27 @@ _ez80_handlers:
irqhandler EZ80_UNUSED+26 ; 61 0x134
irqhandler EZ80_UNUSED+27 ; 62 0x138
irqhandler EZ80_UNUSED+28 ; 63 0x13c
;**************************************************************************
; Vector Setup Logic
;**************************************************************************
define .STARTUP, space = ROM
segment .STARTUP
.assume ADL=1
_ez80_initvectors:
; We don't need to do much here. The interrupt vectors and handlers
; are all in FLASH.
; Select interrupt mode 2
im 2 ; Interrupt mode 2
; Write the address of the vector table into the interrupt vector base
ld a, _ez80_vectable >> 8 & 0ffh
ld i, a
ret
end

15
boards/z80/ez80/z20x/README.txt
View File

@ -34,6 +34,7 @@ Contents
o ZDS-II Compiler Versions
o Environments
o Memory Constaints
o Serial Console
o LEDs and Buttons
- LEDs
@ -83,6 +84,17 @@ Native
The Windows native build has not been attempt. I would expect that it
would have numerous problems.
Memory Constaints
=================
The eZ80F92 has a smaller FLASH memory of 128Kb. That combined with the
fact that the size of NuttX is increasing means that it is very easy to
exceed the ROM address space.
The sdboot configuration will fit into the ROM address space, but NOT if
you enable assertions, debug outputs, or even debug symbols. It is very
unlikely that the nsh_flash configuration will fit into FLASH at all!
Serial Console
==============
@ -200,6 +212,9 @@ Configuration Subdirectories
information see: apps/system/nsh/README.txt and
Documentation/NuttShell.html.
UNVERIFIED! I doubt that the nsh_flash program will fit into the
smaller FLASH memory of the eZ80F92 part.
NOTES:
1. The two configurations different only in that one builds for

6
boards/z80/ez80/z20x/configs/nsh_flash/defconfig
View File

@ -47,9 +47,9 @@ CONFIG_RTC_ALARM=y
CONFIG_SCHED_HPWORK=y
CONFIG_SDCLONE_DISABLE=y
CONFIG_SPI=y
CONFIG_START_DAY=16
CONFIG_START_MONTH=6
CONFIG_START_YEAR=2019
CONFIG_START_DAY=20
CONFIG_START_MONTH=2
CONFIG_START_YEAR=2020
CONFIG_SYSTEM_NSH=y
CONFIG_UART1_BITS=0
CONFIG_UART1_RXBUFSIZE=192

6
boards/z80/ez80/z20x/configs/nsh_ram/defconfig
View File

@ -48,9 +48,9 @@ CONFIG_RTC_ALARM=y
CONFIG_SCHED_HPWORK=y
CONFIG_SDCLONE_DISABLE=y
CONFIG_SPI=y
CONFIG_START_DAY=16
CONFIG_START_MONTH=6
CONFIG_START_YEAR=2019
CONFIG_START_DAY=20
CONFIG_START_MONTH=2
CONFIG_START_YEAR=2020
CONFIG_SYSTEM_NSH=y
CONFIG_UART1_BITS=0
CONFIG_UART1_RXBUFSIZE=192

12
boards/z80/ez80/z20x/configs/sdboot/defconfig
View File

@ -26,7 +26,6 @@ CONFIG_FAT_LFN=y
CONFIG_FS_FAT=y
CONFIG_HOST_WINDOWS=y
CONFIG_LIB_HEX2BIN=y
CONFIG_Z20X_SDBOOT=y
CONFIG_MAX_TASKS=8
CONFIG_MAX_WDOGPARMS=2
CONFIG_MMCSD=y
@ -37,16 +36,15 @@ CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=4
CONFIG_PTHREAD_STACK_DEFAULT=1024
CONFIG_RAM_SIZE=65536
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_HPWORK=y
CONFIG_SDCLONE_DISABLE=y
CONFIG_SPI=y
CONFIG_START_DAY=26
CONFIG_START_MONTH=6
CONFIG_START_YEAR=2019
CONFIG_START_DAY=20
CONFIG_START_MONTH=2
CONFIG_START_YEAR=2020
CONFIG_UART1_BITS=0
CONFIG_UART1_RXBUFSIZE=192
CONFIG_UART1_RXBUFSIZE=64
CONFIG_UART1_SERIAL_CONSOLE=y
CONFIG_UART1_TXBUFSIZE=64
CONFIG_USER_ENTRYPOINT="sd_main"
CONFIG_WDOG_INTRESERVE=1
CONFIG_Z20X_SDBOOT=y