Improvements on ADC driver
* Add option to start adc at setup * Add option to cofigure ADC resolution * Add option to cofigure ADC sample time * Add option to cofigure ADC DMA * Add suport for low level operations.
This commit is contained in:
Daniel P. Carvalho
Alan Carvalho de Assis
parent
d86fd84a8e
commit
8c04cc86c0
@ -5021,6 +5021,63 @@ endmenu # Timer Configuration
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menu "ADC Configuration"
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depends on STM32L4_ADC
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config STM32L4_ADC_NO_STARTUP_CONV
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bool "Do not start conversion when opening ADC device"
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default n
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---help---
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Do not start conversion when opening ADC device.
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config STM32L4_ADC_NOIRQ
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bool "Do not use default ADC interrupts"
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default n
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---help---
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Do not use default ADC interrupts handlers.
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config STM32L4_ADC_SMPR
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int "ADC sample time"
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default 0
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range 0 7
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---help---
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ADC sample time
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0 - 2.5 ADC clock cycles
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1 - 6.5 ADC clock cycles
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2 - 12.5 ADC clock cycles
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3 - 24.5 ADC clock cycles
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4 - 47.5 ADC clock cycles
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5 - 92.5 ADC clock cycles
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6 - 247.5 ADC clock cycles
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7 - 640.5 ADC clock cycles
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config STM32L4_ADC_LL_OPS
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bool "ADC low-level operations"
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default n
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---help---
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Enable low-level ADC ops.
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config STM32L4_ADC1_RESOLUTION
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int "ADC1 resolution"
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depends on STM32L4_ADC1
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default 0
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range 0 3
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---help---
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ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit
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config STM32L4_ADC2_RESOLUTION
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int "ADC2 resolution"
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depends on STM32L4_ADC2
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default 0
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range 0 3
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---help---
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ADC2 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit
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config STM32L4_ADC3_RESOLUTION
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int "ADC3 resolution"
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depends on STM32L4_ADC3
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default 0
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range 0 3
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---help---
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ADC3 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit
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config STM32L4_ADC1_DMA
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bool "ADC1 DMA"
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depends on STM32L4_ADC1
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@ -5030,6 +5087,14 @@ config STM32L4_ADC1_DMA
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DMA transfer, which is necessary if multiple channels are read
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or if very high trigger frequencies are used.
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config STM32L4_ADC1_DMA_CFG
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int "ADC1 DMA configuration"
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depends on STM32L4_ADC1_DMA
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range 0 1
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default 1
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---help---
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0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode
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config STM32L4_ADC2_DMA
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bool "ADC2 DMA"
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depends on STM32L4_ADC2
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@ -5039,6 +5104,14 @@ config STM32L4_ADC2_DMA
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DMA transfer, which is necessary if multiple channels are read
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or if very high trigger frequencies are used.
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config STM32L4_ADC2_DMA_CFG
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int "ADC2 DMA configuration"
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depends on STM32L4_ADC2_DMA
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range 0 1
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default 1
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---help---
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0 - ADC2 DMA in One Shot Mode, 1 - ADC2 DMA in Circular Mode
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config STM32L4_ADC3_DMA
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bool "ADC3 DMA"
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depends on STM32L4_ADC3
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@ -5048,6 +5121,14 @@ config STM32L4_ADC3_DMA
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DMA transfer, which is necessary if multiple channels are read
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or if very high trigger frequencies are used.
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config STM32L4_ADC3_DMA_CFG
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int "ADC3 DMA configuration"
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depends on STM32L4_ADC3_DMA
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range 0 1
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default 1
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---help---
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0 - ADC3 DMA in One Shot Mode, 1 - ADC3 DMA in Circular Mode
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config STM32L4_ADC1_OUTPUT_DFSDM
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bool "ADC1 output to DFSDM"
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depends on STM32L4_ADC1 && STM32L4_DFSDM1 && (STM32L4_STM32L496XX || STM32L4_STM32L4XR)
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File diff suppressed because it is too large
Load Diff
@ -1,4 +1,4 @@
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/************************************************************************************
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/*****************************************************************************
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* arch/arm/src/stm32L4/stm32l4_adc.h
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*
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* Copyright (C) 2009, 2011, 2015-2017 Gregory Nutt. All rights reserved.
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@ -34,27 +34,28 @@
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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*****************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_ADC_H
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#define __ARCH_ARM_SRC_STM32L4_STM32L4_ADC_H
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/************************************************************************************
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/*****************************************************************************
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* Included Files
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************************************************************************************/
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*****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/analog/adc.h>
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#include "chip.h"
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#include "hardware/stm32l4_adc.h"
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/************************************************************************************
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/*****************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Configuration ********************************************************************/
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*****************************************************************************/
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/* Timer devices may be used for different purposes. One special purpose is to
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* control periodic ADC sampling. If CONFIG_STM32L4_TIMn is defined then
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/* Configuration *************************************************************/
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/* Timer devices may be used for different purposes. One special purpose is
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* to control periodic ADC sampling. If CONFIG_STM32L4_TIMn is defined then
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* CONFIG_STM32L4_TIMn_ADC must also be defined to indicate that timer "n" is
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* intended to be used for that purpose. Timers 1,2,3,6 and 15 may be used on
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* STM32L4X3, while STM32L4X6 adds support for timers 4 and 8 as well.
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@ -441,6 +442,9 @@
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#define ADC3_EXTSEL_T15CC4 ADC_CFGR_EXTSEL_T15CC4
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#define ADC3_EXTSEL_T15TRGO ADC_CFGR_EXTSEL_T15TRGO
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/* EXTSEL configuration ******************************************************/
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/* Configure external event for regular group */
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#if defined(CONFIG_STM32L4_TIM1_ADC1)
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# if CONFIG_STM32L4_ADC1_TIMTRIG == 0
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@ -754,13 +758,110 @@
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# endif
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#endif
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/* ADC interrupts ************************************************************/
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/************************************************************************************
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#define ADC_ISR_EOC ADC_INT_EOC
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#define ADC_IER_EOC ADC_INT_EOC
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#define ADC_ISR_AWD ADC_INT_AWD1
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#define ADC_IER_AWD ADC_INT_AWD1
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#define ADC_ISR_JEOC ADC_INT_JEOC
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#define ADC_IER_JEOC ADC_INT_JEOC
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#define ADC_ISR_OVR ADC_INT_OVR
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#define ADC_IER_OVR ADC_INT_OVR
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#define ADC_ISR_JEOS ADC_INT_JEOS
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#define ADC_IER_JEOS ADC_INT_JEOS
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#define ADC_ISR_ALLINTS (ADC_ISR_EOC | ADC_ISR_AWD | ADC_ISR_JEOC | \
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ADC_ISR_JEOS | ADC_ISR_OVR)
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#define ADC_IER_ALLINTS (ADC_IER_EOC | ADC_IER_AWD | ADC_IER_JEOC | \
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ADC_IER_JEOS | ADC_IER_OVR)
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/* Low-level ops helpers *****************************************************/
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#define ADC_INT_ACK(adc, source) \
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(adc)->llops->int_ack(adc, source)
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#define ADC_INT_GET(adc) \
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(adc)->llops->int_get(adc)
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#define ADC_INT_ENABLE(adc, source) \
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(adc)->llops->int_en(adc, source)
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#define ADC_INT_DISABLE(adc, source) \
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(adc)->llops->int_dis(adc, source)
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#define ADC_REGDATA_GET(adc) \
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(adc)->llops->val_get(adc)
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#define ADC_REGBUF_REGISTER(adc, buffer, len) \
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(adc)->llops->regbuf_reg(adc, buffer, len)
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#define ADC_REG_STARTCONV(adc, state) \
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(adc)->llops->reg_startconv(adc, state)
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#define ADC_OFFSET_SET(adc, ch, i, o) \
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(adc)->llops->offset_set(adc, ch, i, o)
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#define ADC_DUMP_REGS(adc) \
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(adc)->llops->dump_regs(adc)
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/*****************************************************************************
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* Public Types
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*****************************************************************************/
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#ifdef CONFIG_STM32L4_ADC_LL_OPS
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/* This structure provides the publicly visable representation of the
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* "lower-half" ADC driver structure.
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*/
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struct stm32_adc_dev_s
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{
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/* Publicly visible portion of the "lower-half" ADC driver structure */
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FAR const struct stm32_adc_ops_s *llops;
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/* Require cast-compatibility with private "lower-half" ADC strucutre */
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};
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/* Low-level operations for ADC */
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struct stm32_adc_ops_s
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{
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/* Acknowledge interrupts */
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void (*int_ack)(FAR struct stm32_adc_dev_s *dev, uint32_t source);
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/* Get pending interrupts */
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uint32_t (*int_get)(FAR struct stm32_adc_dev_s *dev);
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/* Enable interrupts */
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void (*int_en)(FAR struct stm32_adc_dev_s *dev, uint32_t source);
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/* Disable interrupts */
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void (*int_dis)(FAR struct stm32_adc_dev_s *dev, uint32_t source);
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/* Get current ADC data register */
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uint32_t (*val_get)(FAR struct stm32_adc_dev_s *dev);
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/* Register buffer for ADC DMA transfer */
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int (*regbuf_reg)(FAR struct stm32_adc_dev_s *dev, uint16_t *buffer,
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uint8_t len);
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/* Start/stop regular conversion */
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void (*reg_startconv)(FAR struct stm32_adc_dev_s *dev, bool state);
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/* Set offset for channel */
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int (*offset_set)(FAR struct stm32_adc_dev_s *dev, uint8_t ch, uint8_t i,
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uint16_t offset);
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void (*dump_regs)(FAR struct stm32_adc_dev_s *dev);
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};
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#endif /* CONFIG_STM32L4_ADC_LL_OPS */
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/*****************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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*****************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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@ -771,7 +872,7 @@ extern "C"
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#define EXTERN extern
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#endif
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/****************************************************************************
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/*****************************************************************************
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* Name: stm32l4_adc_initialize
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*
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* Description:
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@ -785,7 +886,7 @@ extern "C"
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* Returned Value:
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* Valid ADC device structure reference on success; a NULL on failure
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*
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****************************************************************************/
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*****************************************************************************/
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struct adc_dev_s;
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struct adc_dev_s *stm32l4_adc_initialize(int intf,
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@ -798,4 +899,4 @@ struct adc_dev_s *stm32l4_adc_initialize(int intf,
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#endif /* __ASSEMBLY__ */
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#endif /* CONFIG_STM32L4_ADC1 || CONFIG_STM32L4_ADC2 || CONFIG_STM32L4_ADC3 */
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#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_ADC_H */
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#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_ADC_H */
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