Add logic to clear pending EMAC interrupts

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3118 42af7a65-404d-4744-a932-0658087f49c3

arch/arm/src/lpc17xx/Make.defs

@@ -51,9 +51,9 @@ CMN_CSRCS	= up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
 # Required LPC17xx files
 
 CHIP_ASRCS	=
-CHIP_CSRCS	= lpc17_allocateheap.c lpc17_clockconfig.c lpc17_gpio.c \
+CHIP_CSRCS	= lpc17_allocateheap.c lpc17_clockconfig.c lpc17_clrpend.c \
-		  lpc17_irq.c lpc17_lowputc.c lpc17_serial.c lpc17_spi.c \
+		  lpc17_gpio.c lpc17_irq.c lpc17_lowputc.c lpc17_serial.c \
-		  lpc17_ssp.c lpc17_start.c lpc17_timerisr.c
+		  lpc17_spi.c lpc17_ssp.c lpc17_start.c lpc17_timerisr.c
 
 # Configuration-dependent LPC17xx files
 

arch/arm/src/lpc17xx/lpc17_clrpend.c

@@ -0,0 +1,97 @@
+/****************************************************************************
+ * arch/arm/src/lpc17/lpc17_clrpend.c
+ * arch/arm/src/chip/lpc17_clrpend.c
+ *
+ *   Copyright (C) 2010 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <arch/irq.h>
+
+#include "nvic.h"
+#include "up_arch.h"
+#include "lpc17_internal.h"
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc17_clrpend
+ *
+ * Description:
+ *   Clear a pending interrupt at the NVIC.  This does not seem to be required
+ *   for most interrupts.  Don't know why... but the LPC1766 Ethernet EMAC
+ *   interrupt definitely needs it!
+ *
+ *   I keep it in a separate file so that it will not increase the footprint
+ *   on LPC17xx platforms that do not need this function.
+ *
+ ****************************************************************************/
+
+void lpc17_clrpend(int irq)
+{
+  /* Check for external interrupt */
+
+  if (irq >= LPC17_IRQ_EXTINT)
+    {
+      if (irq < (LPC17_IRQ_EXTINT+32))
+        {
+          putreg32(1 << (irq - LPC17_IRQ_EXTINT), NVIC_IRQ0_31_CLRPEND);
+        }
+      else if (irq < LPC17_IRQ_NIRQS)
+        {
+          putreg32(1 << (irq - LPC17_IRQ_EXTINT - 32), NVIC_IRQ32_63_CLRPEND);
+        }
+    }
+}

arch/arm/src/lpc17xx/lpc17_ethernet.c

@@ -1115,67 +1115,8 @@ static int lpc17_interrupt(int irq, void *context)
   status = lpc17_getreg(LPC17_ETH_INTST);
   if (status != 0)
     {
-      /* Handle each pending interrupt */
+      /* Handle each pending interrupt **************************************/
-      /* Check for receive errors */
+      /* Check for Wake-Up on Lan *******************************************/
-
-      if ((status & ETH_INT_RXOVR) != 0)
-        {
-          lpc17_putreg(ETH_INT_RXOVR, LPC17_ETH_INTCLR);
-          EMAC_STAT(priv, rx_ovrerrors);
-        }
-
-      if ((status & ETH_INT_RXERR) != 0)
-        {
-          lpc17_putreg(ETH_INT_RXERR, LPC17_ETH_INTCLR);
-          EMAC_STAT(priv, rx_errors);
-        }
-
-      /* Check if we received an incoming packet, if so, call lpc17_rxdone() */
-
-      if ((status & ETH_INT_RXFIN) != 0)
-        {
-          lpc17_putreg(ETH_INT_RXFIN, LPC17_ETH_INTCLR);
-          EMAC_STAT(priv, rx_finished);
-          DEBUGASSERT(lpc17_getreg(LPC17_ETH_RXPRODIDX) == lpc17_getreg(LPC17_ETH_RXCONSIDX));
-        }
-
-      if ((status & ETH_INT_RXDONE) != 0)
-        {
-          lpc17_putreg(ETH_INT_RXDONE, LPC17_ETH_INTCLR);
-          EMAC_STAT(priv, rx_done);
-          lpc17_rxdone(priv);
-        }
-
-      /* Check for Tx errors */
-
-      if ((status & ETH_INT_TXUNR) != 0)
-        {
-          lpc17_putreg(ETH_INT_TXUNR, LPC17_ETH_INTCLR);
-          EMAC_STAT(priv, tx_underrun);
-        }
-
-      if ((status & ETH_INT_TXERR) != 0)
-        {
-          lpc17_putreg(ETH_INT_TXERR, LPC17_ETH_INTCLR);
-          EMAC_STAT(priv, tx_errors);
-        }
-
-      /* Check is a packet transmission just completed.  If so, call lpc17_txdone */
-
-      if ((status & ETH_INT_TXFIN) != 0)
-        {
-          lpc17_putreg(ETH_INT_TXFIN, LPC17_ETH_INTCLR);
-          EMAC_STAT(priv, tx_finished);
-        }
-
-      if ((status & ETH_INT_TXDONE) != 0)
-        {
-          lpc17_putreg(ETH_INT_TXDONE, LPC17_ETH_INTCLR);
-          EMAC_STAT(priv, tx_done);
-          lpc17_txdone(priv);
-        }
-
-      /* Check for Wake-Up on Lan */
 
 #ifdef CONFIG_NET_WOL
       if ((status & ETH_INT_WKUP) != 0)
@@ -1183,10 +1124,132 @@ static int lpc17_interrupt(int irq, void *context)
           lpc17_putreg(ETH_INT_WKUP, LPC17_ETH_INTCLR);
           EMAC_STAT(priv, wol);
 #         warning "Missing logic"
+          goto intexit;
         }
+      else
 #endif
+      /* Fatal Errors *******************************************************/
+      /* RX OVERRUN -- Fatal overrun error in the receive queue. The fatal
+       * interrupt should be resolved by a Rx soft-reset. The bit is not
+       * set when there is a nonfatal overrun error.
+       *
+       * TX UNDERRUN -- Interrupt set on a fatal underrun error in the
+       * transmit queue. The fatal interrupt should be resolved by a Tx
+       * soft-reset. The bit is not set when there is a nonfatal underrun
+       * error.
+       */
+
+      if ((status & (ETH_INT_RXOVR|ETH_INT_TXUNR)) != 0)
+        {
+          if ((status & ETH_INT_RXOVR) != 0)
+            {
+               lpc17_putreg(ETH_INT_RXOVR, LPC17_ETH_INTCLR);
+               EMAC_STAT(priv, rx_ovrerrors);
+            }
+
+          if ((status & ETH_INT_TXUNR) != 0)
+            {
+              lpc17_putreg(ETH_INT_TXUNR, LPC17_ETH_INTCLR);
+              EMAC_STAT(priv, tx_underrun);
+            }
+
+           /* ifup() will reset the EMAC and bring it back up */
+
+           (void)lpc17_ifup(&priv->lp_dev);
+        }
+      else
+        {      
+          /* Check for receive events ***************************************/
+          /* RX ERROR -- Triggered on receive errors: AlignmentError,
+           * RangeError, LengthError, SymbolError, CRCError or
+           * NoDescriptor or Overrun.
+           */
+
+          if ((status & ETH_INT_RXERR) != 0)
+            {
+              lpc17_putreg(ETH_INT_RXERR, LPC17_ETH_INTCLR);
+              EMAC_STAT(priv, rx_errors);
+            }
+          else
+            {
+              /* RX FINISHED -- Triggered when all receive descriptors have
+               * been processed i.e. on the transition to the situation
+               * where ProduceIndex == ConsumeIndex.
+               */
+
+              if ((status & ETH_INT_RXFIN) != 0)
+                {
+                  lpc17_putreg(ETH_INT_RXFIN, LPC17_ETH_INTCLR);
+                  EMAC_STAT(priv, rx_finished);
+                  DEBUGASSERT(lpc17_getreg(LPC17_ETH_RXPRODIDX) == lpc17_getreg(LPC17_ETH_RXCONSIDX));
+                }
+
+              /* RX DONE -- Triggered when a receive descriptor has been
+               * processed while the Interrupt bit in the Control field of
+               * the descriptor was set.
+               */
+
+              if ((status & ETH_INT_RXDONE) != 0)
+                {
+                  lpc17_putreg(ETH_INT_RXDONE, LPC17_ETH_INTCLR);
+                  EMAC_STAT(priv, rx_done);
+
+                  /* We have received at least one new incoming packet. */
+
+                  lpc17_rxdone(priv);
+                }
+            }
+
+          /* Check for Tx events ********************************************/
+          /* TX ERROR -- Triggered on transmit errors: LateCollision,
+           * ExcessiveCollision and ExcessiveDefer, NoDescriptor or Underrun.
+           */
+
+          if ((status & ETH_INT_TXERR) != 0)
+            {
+              lpc17_putreg(ETH_INT_TXERR, LPC17_ETH_INTCLR);
+              EMAC_STAT(priv, tx_errors);
+            }
+          else
+            {
+              /* TX FINISHED -- Triggered when all transmit descriptors have
+               * been processed i.e. on the transition to the situation
+               * where ProduceIndex == ConsumeIndex.
+               */
+
+              if ((status & ETH_INT_TXFIN) != 0)
+                {
+                  lpc17_putreg(ETH_INT_TXFIN, LPC17_ETH_INTCLR);
+                  EMAC_STAT(priv, tx_finished);
+                }
+
+              /* TX DONE -- Triggered when a descriptor has been transmitted
+               * while the Interrupt bit in the Control field of the
+               * descriptor was set.
+               */
+
+              if ((status & ETH_INT_TXDONE) != 0)
+                {
+                  lpc17_putreg(ETH_INT_TXDONE, LPC17_ETH_INTCLR);
+                  EMAC_STAT(priv, tx_done);
+
+                  /* A packet transmission just completed */
+
+                  lpc17_txdone(priv);
+                }
+            }
+        }
     }
 
+  /* Clear the pending interrupt.  Hmmm.. I don't normally do this on 
+   * Cortex-M3 interrupts.  Why is this needed for the EMAC interrupt?
+   */
+
+#if CONFIG_LPC17_NINTERFACES > 1
+  lpc17_clrpend(priv->irq);
+#else
+  lpc17_clrpend(LPC17_IRQ_ETH);
+#endif
   return OK;
 }
 

arch/arm/src/lpc17xx/lpc17_internal.h

@@ -542,6 +542,18 @@ EXTERN int lpc17_dumpgpio(uint16_t pinset, const char *msg);
 #  define lpc17_dumpgpio(p,m)
 #endif
 
+/************************************************************************************
+ * Name: lpc17_clrpend
+ *
+ * Description:
+ *   Clear a pending interrupt at the NVIC.  This does not seem to be required
+ *   for most interrupts.  Don't know why... but the LPC1766 Ethernet EMAC
+ *   interrupt definitely needs it!
+ *
+ ************************************************************************************/
+
+EXTERN void lpc17_clrpend(int irq);
+
 /************************************************************************************
  * Name:  lpc17_spi/ssp0/ssp1select and lpc17_spi/ssp0/ssp1status
  *

arch/arm/src/lpc17xx/lpc17_irq.c

@@ -259,33 +259,6 @@ static int lpc17_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit)
   return OK;
 }
 
-/****************************************************************************
- * Name: lpc17_clrpend
- *
- * Description:
- *  Clear a pending interrupt.
- *
- ****************************************************************************/
-
-static inline void lpc17_clrpend(int irq)
-{
-#if 0 /* Necessary? */
-  /* Check for external interrupt */
-
-  if (irq >= LPC17_IRQ_EXTINT)
-    {
-      if (irq < (LPC17_IRQ_EXTINT+32))
-        {
-          putreg32(1 << (irq - LPC17_IRQ_EXTINT), NVIC_IRQ0_31_CLRPEND);
-        }
-      else if (irq < LPC17_IRQ_NIRQS)
-        {
-          putreg32(1 << (irq - LPC17_IRQ_EXTINT - 32), NVIC_IRQ32_63_CLRPEND);
-        }
-    }
-#endif
-}
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -453,7 +426,10 @@ void up_enable_irq(int irq)
 void up_maskack_irq(int irq)
 {
   up_disable_irq(irq);
+
+#if 0 /* Does not appear to be necessary in most cases */
   lpc17_clrpend(irq);
+#endif
 }
 
 /****************************************************************************