Fixes to last SAMA5 PMIC checkin
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@ -528,11 +528,13 @@ void up_irqinitialize(void)
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putreg32(AXIMX_REMAP_REMAP1, SAM_AXIMX_REMAP); /* Remap NOR FLASH on CS0 */
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#endif
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/* Make sure that there is no trace of any previous mapping */
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/* Make sure that there is no trace of any previous mapping (here we
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* that the L2 cache has not yet been enabled.
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*/
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vectorsize = sam_vectorsize();
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arch_invalidate_icache();
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arch_invalidate_dcache(0, vectorsize);
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cp15_invalidate_icache();
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cp15_invalidate_dcache(0, vectorsize);
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mmu_invalidate_region(0, vectorsize);
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#if 0 /* Disabled on reset */
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@ -112,6 +112,12 @@ CONFIG_ARCH_LOWVECTORS=y
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#
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# ARMv7-A Configuration Options
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#
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CONFIG_ARMV7A_HAVE_L2CC=y
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CONFIG_ARMV7A_HAVE_L2CC_PL310=y
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#
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# L2 Cache Configuration
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#
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# CONFIG_ARMV7A_TOOLCHAIN_BUILDROOT is not set
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CONFIG_ARMV7A_TOOLCHAIN_CODESOURCERYW=y
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# CONFIG_ARMV7A_TOOLCHAIN_DEVKITARM is not set
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@ -133,7 +139,6 @@ CONFIG_SAMA5_HAVE_USART4=y
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# CONFIG_SAMA5_HAVE_DMA is not set
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CONFIG_SAMA5_HAVE_DDR32=y
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CONFIG_SAMA5_HAVE_XDMA=y
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CONFIG_SAMA5_HAVE_L2CC=y
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CONFIG_SAMA5_HAVE_LCDC=y
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# CONFIG_SAMA5_HAVE_GMAC is not set
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# CONFIG_SAMA5_HAVE_EMACA is not set
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@ -168,7 +173,6 @@ CONFIG_ARCH_CHIP_ATSAMA5D44=y
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# CONFIG_SAMA5_TDES is not set
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# CONFIG_SAMA5_AESB is not set
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# CONFIG_SAMA5_DBGU is not set
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# CONFIG_SAMA5_L2CC is not set
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# CONFIG_SAMA5_PIT is not set
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# CONFIG_SAMA5_WDT is not set
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# CONFIG_SAMA5_RTC is not set
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@ -246,6 +250,7 @@ CONFIG_SAMA5_DDRCS_HEAP_SIZE=0
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# CONFIG_ARCH_VECNOTIRQ is not set
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# CONFIG_ARCH_DMA is not set
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CONFIG_ARCH_HAVE_IRQPRIO=y
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# CONFIG_ARCH_L2CACHE is not set
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# CONFIG_CUSTOM_STACK is not set
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# CONFIG_ADDRENV is not set
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CONFIG_ARCH_HAVE_VFORK=y
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@ -317,6 +322,7 @@ CONFIG_SAMA5D4EK_MT47H128M16RT=y
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# CONFIG_SAMA5D4EK_MT47H64M16HR is not set
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CONFIG_SAMA5D4EK_DRAM_MAIN=y
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# CONFIG_SAMA5D4EK_DRAM_START is not set
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# CONFIG_SAMA5D4EK_AT25_MAIN is not set
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#
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# RTOS Features
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@ -415,11 +421,17 @@ CONFIG_DISABLE_POLL=y
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CONFIG_DEV_NULL=y
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# CONFIG_DEV_ZERO is not set
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# CONFIG_LOOP is not set
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#
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# Buffering
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#
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# CONFIG_DRVR_WRITEBUFFER is not set
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# CONFIG_DRVR_READAHEAD is not set
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# CONFIG_RAMDISK is not set
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# CONFIG_CAN is not set
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# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set
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# CONFIG_PWM is not set
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# CONFIG_ARCH_HAVE_I2CRESET is not set
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CONFIG_ARCH_HAVE_I2CRESET=y
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# CONFIG_I2C is not set
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# CONFIG_SPI is not set
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# CONFIG_I2S is not set
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@ -506,6 +518,11 @@ CONFIG_USART3_2STOP=0
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# CONFIG_ARCH_HAVE_PHY is not set
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# CONFIG_NET is not set
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#
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# Crypto API
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#
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# CONFIG_CRYPTO is not set
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#
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# File Systems
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#
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@ -784,6 +801,10 @@ CONFIG_READLINE_ECHO=y
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# P-Code Support
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#
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#
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# PHY Tool
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#
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#
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# Power Off
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#
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@ -111,7 +111,7 @@ int dram_main(int argc, char *argv)
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* JP23 will be closed and the PMIC will be initialized.
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*/
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sam_pmic_initialize()
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sam_pmic_initialize();
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/* DRAM was already initialized at boot time, so we are ready to load the
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* Intel HEX stream into DRAM.
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@ -167,8 +167,8 @@ int dram_main(int argc, char *argv)
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/* Invalidate caches and TLBs */
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arch_invalidate_icache();
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arch_invalidate_dcache_all();
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cp15_invalidate_icache();
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cp15_invalidate_dcache_all();
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cp15_invalidate_tlbs();
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/* Then jump into NOR flash */
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@ -39,17 +39,12 @@
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#include <nuttx/config.h>
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#include <stdbool.h>
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#include <stdio.h>
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#include <debug.h>
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#include <assert.h>
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#include <stdint.h>
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#include <errno.h>
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#include <debug.h>
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#include <nuttx/i2c.h>
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#include <arch/board/board.h>
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#include "up_arch.h"
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#include "sam_twi.h"
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#include "sama5d4-ek.h"
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@ -113,15 +108,15 @@ void sam_pmic_initialize(void)
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buffer[0] = 0x0b;
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buffer[1] = 0xee;
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(void)I2C_SEND(i2c, buffer, 2);
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(void)I2C_WRITE(i2c, buffer, 2);
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buffer[0] = 0x02;
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buffer[1] = 0x0f;
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(void)I2C_SEND(i2c, buffer, 2);
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(void)I2C_WRITE(i2c, buffer, 2);
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buffer[0] = 0x03;
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buffer[1] = 0x0f;
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(void)I2C_SEND(i2c, buffer, 2);
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(void)I2C_WRITE(i2c, buffer, 2);
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}
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}
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@ -985,7 +985,7 @@ int sam_audio_null_initialize(int minor);
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****************************************************************************/
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#ifdef HAVE_PMIC
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void sam_pmic_initialize(void)
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void sam_pmic_initialize(void);
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#else
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# define sam_pmic_initialize()
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#endif
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