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Merge remote-tracking branch 'origin/master' into afunix

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This commit is contained in:
Gregory Nutt 2015-01-27 11:51:57 -06:00
commit 8c3358e721
4 changed files with 61 additions and 7 deletions
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11
ChangeLog
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@ -9524,3 +9524,14 @@
* include/nuttx/math.h and libc/math: Add math library defines for
nan(), copysign(), and trunc() functions. From Brennan Ashton
(2015-01-26).
* sched/wqueue/kwork_process and libc/wqueue/lib_usrthread.c: Fix
a backward calculation when determining the time to the next event.
This is a bug in the back-up, "fail safe", work queue timing so it
not as bad as it seems. From Liio Chen via the PX4 repository
(2015-01-27).
* arch/arm/src/stm32/stm32_exti_gpio.c: Disabling any of EXTI 5-9
interrupts was disabling interrupts for all EXTI 5-9. Same issue with
EXTI 10-15. From Jussi Kivilinna (2015-01-27).
* arch/arm/src/stm32/stm32_rtcc.c and Kconfig: Recent changes to
stm32_rtcc.c do not compile with STM32L15XX configurations. From
Jussi Kivilinna (2015-01-27).

2
arch/arm/src/stm32/Kconfig
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@ -3251,11 +3251,13 @@ config RTC_LSECLOCK
config RTC_LSICLOCK
bool "LSI clock"
depends on !STM32_STM32L15XX
---help---
Drive the RTC with the LSI clock
config RTC_HSECLOCK
bool "HSE clock"
depends on !STM32_STM32L15XX
---help---
Drive the RTC with the HSE clock, divided down to 1MHz.

38
arch/arm/src/stm32/stm32_exti_gpio.c
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@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/stm32/stm32_exti_gpio.c
*
* Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2011-2012, 2015 Gregory Nutt. All rights reserved.
* Copyright (C) 2011 Uros Platise. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Uros Platise <uros.platise@isotel.eu>
@ -245,12 +245,17 @@ xcpt_t stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
int irq;
xcpt_t handler;
xcpt_t oldhandler = NULL;
int nshared;
xcpt_t *shared_cbs;
int i;
/* Select the interrupt handler for this EXTI pin */
if (pin < 5)
{
irq = pin + STM32_IRQ_EXTI0;
irq = pin + STM32_IRQ_EXTI0;
nshared = 1;
shared_cbs = &stm32_exti_callbacks[pin];
switch (pin)
{
case 0:
@ -276,13 +281,17 @@ xcpt_t stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
}
else if (pin < 10)
{
irq = STM32_IRQ_EXTI95;
handler = stm32_exti95_isr;
irq = STM32_IRQ_EXTI95;
handler = stm32_exti95_isr;
shared_cbs = &stm32_exti_callbacks[5];
nshared = 5;
}
else
{
irq = STM32_IRQ_EXTI1510;
handler = stm32_exti1510_isr;
irq = STM32_IRQ_EXTI1510;
handler = stm32_exti1510_isr;
shared_cbs = &stm32_exti_callbacks[10];
nshared = 6;
}
/* Get the previous GPIO IRQ handler; Save the new IRQ handler. */
@ -299,7 +308,22 @@ xcpt_t stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
}
else
{
up_disable_irq(irq);
/* Only disable IRQ if shared handler does not have any active
* callbacks.
*/
for (i = 0; i < nshared; i++)
{
if (shared_cbs[i] != NULL)
{
break;
}
}
if (i == nshared)
{
up_disable_irq(irq);
}
}
/* Configure GPIO, enable EXTI line enabled if event or interrupt is

17
arch/arm/src/stm32/stm32_rtcc.c
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@ -51,6 +51,8 @@
#include "up_arch.h"
#include "stm32_rcc.h"
#include "stm32_pwr.h"
#include "stm32_rtc.h"
#ifdef CONFIG_RTC
@ -77,6 +79,14 @@
# undef CONFIG_DEBUG_RTC
#endif
#ifdef CONFIG_STM32_STM32L15XX
# if defined(CONFIG_RTC_HSECLOCK)
# error "RTC with HSE clock not yet implemented for STM32L15XXX"
# elif defined(CONFIG_RTC_LSICLOCK)
# error "RTC with LSI clock not yet implemented for STM32L15XXX"
# endif
#endif
/* Constants ************************************************************************/
#define SYNCHRO_TIMEOUT (0x00020000)
@ -435,6 +445,7 @@ static int rtc_setup(void)
uint32_t regval;
int ret;
#ifndef CONFIG_STM32_STM32L15XX
/* We might be changing RTCSEL - to ensure such changes work, we must reset the
* backup domain
*/
@ -475,6 +486,12 @@ static int rtc_setup(void)
stm32_rcc_enablelse();
#endif
#else
/* Enable the LSE clock */
stm32_rcc_enablelse();
#endif /* CONFIG_STM32_STM32L15XX */
/* Wait for the RTC Time and Date registers to be synchronized with RTC APB
* clock.