diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h
index f2b1428709..d2bc1952db 100644
--- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h
@@ -737,9 +737,9 @@
 
 /* Alternate function option register 2 (TIMx_AF2) */
 
-#define ATIM_AF1_BK2INE           (1 << 0)  /* Bit 0: BRK2 BKIN input enable */
-#define ATIM_AF1_BK2DFBKE         (1 << 8)  /* Bit 8: BRK2 DFSDM_BREAK enable */
-#define ATIM_AF1_BK2INP           (1 << 9)  /* Bit 9: BRK2 BKIN2 input polarity */
+#define ATIM_AF2_BK2INE           (1 << 0)  /* Bit 0: BRK2 BKIN input enable */
+#define ATIM_AF2_BK2DFBKE         (1 << 8)  /* Bit 8: BRK2 DFSDM_BREAK enable */
+#define ATIM_AF2_BK2INP           (1 << 9)  /* Bit 9: BRK2 BKIN2 input polarity */
 
 /* Break and dead-time register */
 
diff --git a/arch/arm/src/stm32h7/hardware/stm32_tim.h b/arch/arm/src/stm32h7/hardware/stm32_tim.h
index 2ca0e169f5..1beaebe70f 100644
--- a/arch/arm/src/stm32h7/hardware/stm32_tim.h
+++ b/arch/arm/src/stm32h7/hardware/stm32_tim.h
@@ -750,9 +750,9 @@
 
 /* Alternate function option register 2 (TIMx_AF2) */
 
-#define ATIM_AF1_BK2INE           (1 << 0)  /* Bit 0: BRK2 BKIN input enable */
-#define ATIM_AF1_BK2DFBKE         (1 << 8)  /* Bit 8: BRK2 DFSDM_BREAK enable */
-#define ATIM_AF1_BK2INP           (1 << 9)  /* Bit 9: BRK2 BKIN2 input polarity */
+#define ATIM_AF2_BK2INE           (1 << 0)  /* Bit 0: BRK2 BKIN input enable */
+#define ATIM_AF2_BK2DFBKE         (1 << 8)  /* Bit 8: BRK2 DFSDM_BREAK enable */
+#define ATIM_AF2_BK2INP           (1 << 9)  /* Bit 9: BRK2 BKIN2 input polarity */
 
 /* Break and dead-time register */
 
@@ -807,7 +807,7 @@
 #  define ATIM_BDTR_BK2F_FDTSd326 (14 << ATIM_BDTR_BK2F_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */
 #  define ATIM_BDTR_BK2F_FDTSd328 (15 << ATIM_BDTR_BK2F_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */
 #define ATIM_BDTR_BK2E            (1 << 24) /* Bit 24: Break 2 enable */
-#define ATIM_BDTR_BK2P            (1 << 1525 /* Bit 25:Break 2 polarity */
+#define ATIM_BDTR_BK2P            (1 << 25) /* Bit 25: Break 2 polarity */
 
 /* DMA control register */
 
diff --git a/arch/arm/src/stm32h7/stm32_tim.c b/arch/arm/src/stm32h7/stm32_tim.c
index 6efe2e8e95..57d28a4413 100644
--- a/arch/arm/src/stm32h7/stm32_tim.c
+++ b/arch/arm/src/stm32h7/stm32_tim.c
@@ -203,7 +203,7 @@
 #if defined(CONFIG_STM32H7_TIM8)
 #  if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\
       defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT)||\
-      defined(GPIO_TIM1_CH5OUT) ||defined(GPIO_TIM1_CH6OUT)
+      defined(GPIO_TIM8_CH5OUT) ||defined(GPIO_TIM8_CH6OUT)
 #    define HAVE_TIM8_GPIOCONFIG 1
 #  endif
 #endif
@@ -1344,13 +1344,13 @@ FAR struct stm32_tim_dev_s *stm32_tim_init(int timer)
 #endif
 #ifdef CONFIG_STM32H7_TIM13
       case 13:
-        dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv;
+        dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv;
         modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM13EN);
         break;
 #endif
 #ifdef CONFIG_STM32H7_TIM14
       case 14:
-        dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv;
+        dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv;
         modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM14EN);
         break;
 #endif