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xtensa/esp32: Fix RTC watchdog timer deinit at startup

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Write protection must be disabled before performing changes to the WDT
registers. Furthermore, the routine was resetting the wrong field from
the RTC WDT register.
The RTC_CNTL_WDT_FLASHBOOT_MOD_EN field relates to Flash Boot Protection
and it is enabled by the 1st stage bootloader. The 2nd stage bootloader
takes care of disabling it.
Then the 2nd stage bootloader enables the RTC WDT for checking the
startup sequence of the application image.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
This commit is contained in:
Gustavo Henrique Nihei 2021-06-24 14:32:03 -03:00 committed by Alan Carvalho de Assis
parent e890e2e45c
commit 8c70e4f1c1
2 changed files with 9 additions and 1 deletions
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4
arch/xtensa/src/esp32/esp32_start.c
View File

@ -88,9 +88,11 @@ void IRAM_ATTR __start(void)
/* Kill the watchdog timer */
putreg32(RTC_CNTL_WDT_WKEY_VALUE, RTC_CNTL_WDTWPROTECT_REG);
regval = getreg32(RTC_CNTL_WDTCONFIG0_REG);
regval &= ~RTC_CNTL_WDT_FLASHBOOT_MOD_EN;
regval &= ~RTC_CNTL_WDT_EN;
putreg32(regval, RTC_CNTL_WDTCONFIG0_REG);
putreg32(0, RTC_CNTL_WDTWPROTECT_REG);
/* Make sure that normal interrupts are disabled. This is really only an
* issue when we are started in un-usual ways (such as from IRAM). In this

6
arch/xtensa/src/esp32/hardware/esp32_rtccntl.h
View File

@ -47,6 +47,12 @@
#define RWDT_INT_ENA_REG_OFFSET 0x003c
#define RWDT_INT_CLR_REG_OFFSET 0x0048
/* The value that needs to be written to RTC_CNTL_WDT_WKEY to
* write-enable the wdt registers
*/
#define RTC_CNTL_WDT_WKEY_VALUE 0x50d83aa1
/* CLK */
#define CK_XTAL_32K_MASK (BIT(30))
#define CK8M_D256_OUT_MASK (BIT(31))