diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig index 07ced000a6..b43c48a9dd 100644 --- a/arch/arm/src/stm32f7/Kconfig +++ b/arch/arm/src/stm32f7/Kconfig @@ -1866,7 +1866,7 @@ endchoice config STM32F7_ETHMAC_REGDEBUG bool "Register-Level Debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_NET_INFO ---help--- Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. diff --git a/arch/arm/src/stm32f7/stm32_dma.c b/arch/arm/src/stm32f7/stm32_dma.c index cddacbc115..7b03377bcc 100644 --- a/arch/arm/src/stm32f7/stm32_dma.c +++ b/arch/arm/src/stm32f7/stm32_dma.c @@ -606,8 +606,8 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, uint32_t regoffset; uint32_t regval; - dmaerr("paddr: %08x maddr: %08x ntransfers: %d scr: %08x\n", - paddr, maddr, ntransfers, scr); + dmainfo("paddr: %08x maddr: %08x ntransfers: %d scr: %08x\n", + paddr, maddr, ntransfers, scr); #ifdef CONFIG_STM32_DMACAPABLE DEBUGASSERT(stm32_dmacapable(maddr, ntransfers, scr)); @@ -1033,22 +1033,22 @@ void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, const char *msg) { struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle; uint32_t dmabase = DMA_BASE(dmast->base); - dmaerr("DMA Registers: %s\n", msg); - dmaerr(" LISR[%08x]: %08x\n", dmabase + STM32_DMA_LISR_OFFSET, regs->lisr); - dmaerr(" HISR[%08x]: %08x\n", dmabase + STM32_DMA_HISR_OFFSET, regs->hisr); - dmaerr(" SCR[%08x]: %08x\n", dmast->base + STM32_DMA_SCR_OFFSET, regs->scr); - dmaerr(" SNDTR[%08x]: %08x\n", dmast->base + STM32_DMA_SNDTR_OFFSET, regs->sndtr); - dmaerr(" SPAR[%08x]: %08x\n", dmast->base + STM32_DMA_SPAR_OFFSET, regs->spar); - dmaerr(" SM0AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM0AR_OFFSET, regs->sm0ar); - dmaerr(" SM1AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM1AR_OFFSET, regs->sm1ar); - dmaerr(" SFCR[%08x]: %08x\n", dmast->base + STM32_DMA_SFCR_OFFSET, regs->sfcr); + dmainfo("DMA Registers: %s\n", msg); + dmainfo(" LISR[%08x]: %08x\n", dmabase + STM32_DMA_LISR_OFFSET, regs->lisr); + dmainfo(" HISR[%08x]: %08x\n", dmabase + STM32_DMA_HISR_OFFSET, regs->hisr); + dmainfo(" SCR[%08x]: %08x\n", dmast->base + STM32_DMA_SCR_OFFSET, regs->scr); + dmainfo(" SNDTR[%08x]: %08x\n", dmast->base + STM32_DMA_SNDTR_OFFSET, regs->sndtr); + dmainfo(" SPAR[%08x]: %08x\n", dmast->base + STM32_DMA_SPAR_OFFSET, regs->spar); + dmainfo(" SM0AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM0AR_OFFSET, regs->sm0ar); + dmainfo(" SM1AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM1AR_OFFSET, regs->sm1ar); + dmainfo(" SFCR[%08x]: %08x\n", dmast->base + STM32_DMA_SFCR_OFFSET, regs->sfcr); } #endif diff --git a/arch/arm/src/stm32f7/stm32_dma.h b/arch/arm/src/stm32f7/stm32_dma.h index 67c9cbf4c8..f78221c949 100644 --- a/arch/arm/src/stm32f7/stm32_dma.h +++ b/arch/arm/src/stm32f7/stm32_dma.h @@ -265,7 +265,7 @@ bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs); #else # define stm32_dmasample(handle,regs) @@ -282,7 +282,7 @@ void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs); * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, const char *msg); #else diff --git a/arch/arm/src/stm32f7/stm32_dumpgpio.c b/arch/arm/src/stm32f7/stm32_dumpgpio.c index a826720bbc..79210b4e8e 100644 --- a/arch/arm/src/stm32f7/stm32_dumpgpio.c +++ b/arch/arm/src/stm32f7/stm32_dumpgpio.c @@ -51,7 +51,7 @@ #include "stm32_gpio.h" #include "stm32_rcc.h" -#ifdef CONFIG_DEBUG_FEATURES +#ifdef CONFIG_DEBUG_GPIO_INFO /* Content of this file requires verification before it is used with other * families @@ -65,7 +65,6 @@ ****************************************************************************/ /* Port letters for prettier debug output */ -#ifdef CONFIG_DEBUG_FEATURES static const char g_portchar[STM32F7_NGPIO] = { #if STM32F7_NGPIO > 11 @@ -96,7 +95,6 @@ static const char g_portchar[STM32F7_NGPIO] = # error "Bad number of GPIOs" #endif }; -#endif /**************************************************************************** * Public Functions @@ -127,28 +125,28 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg) DEBUGASSERT(port < STM32F7_NGPIO); - llerr("GPIO%c pinset: %08x base: %08x -- %s\n", + gpioinfo("GPIO%c pinset: %08x base: %08x -- %s\n", g_portchar[port], pinset, base, msg); if ((getreg32(STM32_RCC_AHB1ENR) & RCC_AHB1ENR_GPIOEN(port)) != 0) { - llerr(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n", - getreg32(base + STM32_GPIO_MODER_OFFSET), - getreg32(base + STM32_GPIO_OTYPER_OFFSET), - getreg32(base + STM32_GPIO_OSPEED_OFFSET), - getreg32(base + STM32_GPIO_PUPDR_OFFSET)); - llerr(" IDR: %04x ODR: %04x LCKR: %05x\n", - getreg32(base + STM32_GPIO_IDR_OFFSET), - getreg32(base + STM32_GPIO_ODR_OFFSET), - getreg32(base + STM32_GPIO_LCKR_OFFSET)); - llerr(" AFRH: %08x AFRL: %08x\n", - getreg32(base + STM32_GPIO_AFRH_OFFSET), - getreg32(base + STM32_GPIO_AFRL_OFFSET)); + gpioinfo(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n", + getreg32(base + STM32_GPIO_MODER_OFFSET), + getreg32(base + STM32_GPIO_OTYPER_OFFSET), + getreg32(base + STM32_GPIO_OSPEED_OFFSET), + getreg32(base + STM32_GPIO_PUPDR_OFFSET)); + gpioinfo(" IDR: %04x ODR: %04x LCKR: %05x\n", + getreg32(base + STM32_GPIO_IDR_OFFSET), + getreg32(base + STM32_GPIO_ODR_OFFSET), + getreg32(base + STM32_GPIO_LCKR_OFFSET)); + gpioinfo(" AFRH: %08x AFRL: %08x\n", + getreg32(base + STM32_GPIO_AFRH_OFFSET), + getreg32(base + STM32_GPIO_AFRL_OFFSET)); } else { - llerr(" GPIO%c not enabled: AHB1ENR: %08x\n", - g_portchar[port], getreg32(STM32_RCC_AHB1ENR)); + gpioinfo(" GPIO%c not enabled: AHB1ENR: %08x\n", + g_portchar[port], getreg32(STM32_RCC_AHB1ENR)); } leave_critical_section(flags); @@ -156,4 +154,4 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg) } #endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ -#endif /* CONFIG_DEBUG_FEATURES */ +#endif /* CONFIG_DEBUG_GPIO_INFO */ diff --git a/arch/arm/src/stm32f7/stm32_ethernet.c b/arch/arm/src/stm32f7/stm32_ethernet.c index 4845e564d5..6129d3e75f 100644 --- a/arch/arm/src/stm32f7/stm32_ethernet.c +++ b/arch/arm/src/stm32f7/stm32_ethernet.c @@ -263,7 +263,7 @@ * enabled. */ -#ifndef CONFIG_DEBUG_FEATURES +#ifndef CONFIG_DEBUG_NET_INFO # undef CONFIG_STM32F7_ETHMAC_REGDEBUG #endif @@ -664,7 +664,7 @@ static struct stm32_ethmac_s g_stm32ethmac[STM32F7_NETHERNET]; ****************************************************************************/ /* Register operations ******************************************************/ -#if defined(CONFIG_STM32F7_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_STM32F7_ETHMAC_REGDEBUG static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); static void stm32_checksetup(void); @@ -795,7 +795,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv); * ****************************************************************************/ -#if defined(CONFIG_STM32F7_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_STM32F7_ETHMAC_REGDEBUG static uint32_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -816,7 +816,7 @@ static uint32_t stm32_getreg(uint32_t addr) { if (count == 4) { - llerr("...\n"); + ninfo("...\n"); } return val; @@ -833,7 +833,7 @@ static uint32_t stm32_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - llerr("[repeats %d more times]\n", count-3); + ninfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -845,7 +845,7 @@ static uint32_t stm32_getreg(uint32_t addr) /* Show the register value read */ - llerr("%08x->%08x\n", addr, val); + ninfo("%08x->%08x\n", addr, val); return val; } #endif @@ -867,12 +867,12 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#if defined(CONFIG_STM32F7_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_STM32F7_ETHMAC_REGDEBUG static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ - llerr("%08x<-%08x\n", addr, val); + ninfo("%08x<-%08x\n", addr, val); /* Write the value */ @@ -894,7 +894,7 @@ static void stm32_putreg(uint32_t val, uint32_t addr) * ****************************************************************************/ -#if defined(CONFIG_STM32F7_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_STM32F7_ETHMAC_REGDEBUG static void stm32_checksetup(void) { } @@ -1589,7 +1589,7 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv) if (!stm32_isfreebuffer(priv)) { - nllerr("No free buffers\n"); + nllerr("ERROR: No free buffers\n"); return -ENOMEM; } @@ -1718,7 +1718,7 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv) * scanning logic, and continue scanning with the next frame. */ - nllerr("DROPPED: RX descriptor errors: %08x\n", rxdesc->rdes0); + nllwarn("WARNING: DROPPED RX descriptor errors: %08x\n", rxdesc->rdes0); stm32_freesegment(priv, rxcurr, priv->segments); } } @@ -1784,7 +1784,7 @@ static void stm32_receive(struct stm32_ethmac_s *priv) if (dev->d_len > CONFIG_NET_ETH_MTU) { - nllerr("DROPPED: Too big: %d\n", dev->d_len); + nllwarn("WARNING: DROPPED Too big: %d\n", dev->d_len); continue; } @@ -1894,7 +1894,7 @@ static void stm32_receive(struct stm32_ethmac_s *priv) else #endif { - nllerr("DROPPED: Unknown type: %04x\n", BUF->type); + nllwarn("WARNING: DROPPED Unknown type: %04x\n", BUF->type); } /* We are finished with the RX buffer. NOTE: If the buffer is @@ -2158,7 +2158,7 @@ static inline void stm32_interrupt_process(struct stm32_ethmac_s *priv) { /* Just let the user know what happened */ - nllerr("Abormal event(s): %08x\n", dmasr); + nllerr("ERROR: Abormal event(s): %08x\n", dmasr); /* Clear all pending abnormal events */ @@ -2362,7 +2362,7 @@ static void stm32_txtimeout_expiry(int argc, uint32_t arg, ...) { struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)arg; - nllerr("Timeout!\n"); + nllerr("ERROR: Timeout!\n"); #ifdef CONFIG_NET_NOINTS /* Disable further Ethernet interrupts. This will prevent some race diff --git a/arch/arm/src/stm32f7/stm32_i2c.c b/arch/arm/src/stm32f7/stm32_i2c.c index bc34aa25aa..e6fa309cd7 100644 --- a/arch/arm/src/stm32f7/stm32_i2c.c +++ b/arch/arm/src/stm32f7/stm32_i2c.c @@ -1093,7 +1093,7 @@ static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv, if (priv->tndx >= (CONFIG_I2C_NTRACE-1)) { - i2cerr("Trace table overflow\n"); + i2cerr("ERROR: Trace table overflow\n"); return; } @@ -1134,7 +1134,7 @@ static void stm32_i2c_traceevent(FAR struct stm32_i2c_priv_s *priv, if (priv->tndx >= (CONFIG_I2C_NTRACE-1)) { - i2cerr("Trace table overflow\n"); + i2cerr("ERROR: Trace table overflow\n"); return; } @@ -1362,13 +1362,13 @@ static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv) if ((priv->flags & I2C_M_NORESTART) || priv->dcnt > 255) { - i2cerr("RELOAD enabled: dcnt = %i msgc = %i\n", + i2cinfo("RELOAD enabled: dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); stm32_i2c_enable_reload(priv); } else { - i2cerr("RELOAD disable: dcnt = %i msgc = %i\n", + i2cinfo("RELOAD disable: dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); stm32_i2c_disable_reload(priv); } @@ -1407,7 +1407,7 @@ static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv) * START condition using the address and transfer direction data entered. */ - i2cerr("Sending START: dcnt=%i msgc=%i flags=0x%04x\n", + i2cinfo("Sending START: dcnt=%i msgc=%i flags=0x%04x\n", priv->dcnt, priv->msgc, priv->flags); stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, 0, I2C_CR2_START); @@ -1427,7 +1427,7 @@ static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv) static inline void stm32_i2c_sendstop(FAR struct stm32_i2c_priv_s *priv) { - i2cerr("Sending STOP\n"); + i2cinfo("Sending STOP\n"); stm32_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, 0); stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, 0, I2C_CR2_STOP); @@ -1655,7 +1655,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) { /* Unsupported state */ - i2cerr("TXIS: UNSUPPORTED STATE DETECTED, dcnt=%i, status 0x%08x\n", + i2cerr("ERROR: TXIS Unsupported state detected, dcnt=%i, status 0x%08x\n", priv->dcnt, status); stm32_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0); } @@ -1741,7 +1741,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) stm32_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); status = stm32_i2c_getreg(priv, STM32F7_I2C_ISR_OFFSET); - i2cerr("RXNE: UNSUPPORTED STATE DETECTED, dcnt=%i, status 0x%08x\n", + i2cerr("ERROR: RXNE Unsupported state detected, dcnt=%i, status 0x%08x\n", priv->dcnt, status); /* Set signals that will terminate ISR and wake waiting thread */ @@ -1976,7 +1976,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) else if (priv->dcnt == -1 && priv->msgc == 0) { status = stm32_i2c_getreg(priv, STM32F7_I2C_ISR_OFFSET); - i2cerr("EMPTY CALL: Stopping ISR: status 0x%08x\n", status); + i2cwarn("WARNING: EMPTY CALL: Stopping ISR: status 0x%08x\n", status); stm32_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); } @@ -1999,7 +1999,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) status = stm32_i2c_getreg(priv, STM32F7_I2C_ISR_OFFSET); - i2cerr("INVALID STATE DETECTED, status 0x%08x\n", status); + i2cerr("ERROR: Invalid state detected, status 0x%08x\n", status); /* set condition to terminate ISR and wake waiting thread */ @@ -2303,16 +2303,16 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s /* Connection timed out */ errval = ETIMEDOUT; - i2cerr("Waitdone timed out: CR1: 0x%08x CR2: 0x%08x status: 0x%08x\n", + i2cerr("ERROR: Waitdone timed out CR1: 0x%08x CR2: 0x%08x status: 0x%08x\n", cr1, cr2,status); } else { - i2cerr("Waitdone success: CR1: 0x%08x CR2: 0x%08x status: 0x%08x\n", + i2cinfo("Waitdone success: CR1: 0x%08x CR2: 0x%08x status: 0x%08x\n", cr1, cr2,status ); } - i2cerr("priv->status: 0x%08x\n", priv->status); + i2cinfo("priv->status: 0x%08x\n", priv->status); /* Check for error status conditions */ @@ -2330,7 +2330,7 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s { /* Bus Error, ignore it because of errata (revision A,Z) */ - i2cerr("I2C: Bus Error\n"); + i2cerr("ERROR: I2C Bus Error\n"); /* errval = EIO; */ } @@ -2338,7 +2338,7 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s { /* Arbitration Lost (master mode) */ - i2cerr("I2C: Arbitration Lost\n"); + i2cerr("ERROR: I2C Arbitration Lost\n"); errval = EAGAIN; } @@ -2346,21 +2346,21 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s { /* Overrun/Underrun */ - i2cerr("I2C: Overrun/Underrun\n"); + i2cerr("ERROR: I2C Overrun/Underrun\n"); errval = EIO; } else if (status & I2C_INT_PECERR) { /* PEC Error in reception (SMBus Only) */ - i2cerr("I2C: PEC Error\n"); + i2cerr("ERROR: I2C PEC Error\n"); errval = EPROTO; } else if (status & I2C_INT_TIMEOUT) { /* Timeout or Tlow Error (SMBus Only) */ - i2cerr("I2C: Timeout / Tlow Error\n"); + i2cerr("ERROR: I2C Timeout / Tlow Error\n"); errval = ETIME; } else if (status & I2C_INT_NACK) @@ -2369,12 +2369,12 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s if (priv->astart == TRUE) { - i2cerr("I2C: Address NACK\n"); + i2cwarn("WARNING: I2C Address NACK\n"); errval = EADDRNOTAVAIL; } else { - i2cerr("I2C: Data NACK\n"); + i2cwarn("WARNING: I2C Data NACK\n"); errval = ECOMM; } } @@ -2382,7 +2382,7 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s { /* Unrecognized error */ - i2cerr("I2C: Unrecognized Error"); + i2cerr("ERROR: I2C Unrecognized Error"); errval = EINTR; } } @@ -2413,7 +2413,7 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s { if((clock_systimer() - start) > timeout) { - i2cerr("I2C: Bus busy"); + i2cerr("ERROR: I2C Bus busy"); errval = EBUSY; break; } diff --git a/arch/arm/src/stm32l4/Kconfig b/arch/arm/src/stm32l4/Kconfig index 6bc1cc9920..1724fe8124 100644 --- a/arch/arm/src/stm32l4/Kconfig +++ b/arch/arm/src/stm32l4/Kconfig @@ -333,7 +333,7 @@ config STM32L4_QSPI_DMATHRESHOLD config STM32L4_QSPI_DMADEBUG bool "QSPI DMA transfer debug" - depends on STM32L4_QSPI_DMA && DEBUG_FEATURES && DEBUG_DMA + depends on STM32L4_QSPI_DMA && DEBUG_SPI && DEBUG_DMA default n ---help--- Enable special debug instrumentation to analyze QSPI DMA data transfers. @@ -343,11 +343,11 @@ config STM32L4_QSPI_DMADEBUG config STM32L4_QSPI_REGDEBUG bool "QSPI Register level debug" - depends on DEBUG_FEATURES + depends on DEBUG_SPI_INFO default n ---help--- Output detailed register-level QSPI device debug information. - Requires also CONFIG_DEBUG_FEATURES. + Requires also CONFIG_DEBUG_SPI_INFO. endif diff --git a/arch/arm/src/stm32l4/stm32l4_dma.h b/arch/arm/src/stm32l4/stm32l4_dma.h index ee11f8655c..c5ccf60b29 100644 --- a/arch/arm/src/stm32l4/stm32l4_dma.h +++ b/arch/arm/src/stm32l4/stm32l4_dma.h @@ -90,7 +90,7 @@ typedef FAR void *DMA_HANDLE; typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg); -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO struct stm32l4_dmaregs_s { uint32_t isr; /* Interrupt Status Register; each channel gets 4 bits */ @@ -267,7 +267,7 @@ bool stm32l4_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void stm32l4_dmasample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs); #else # define stm32l4_dmasample(handle,regs) @@ -284,7 +284,7 @@ void stm32l4_dmasample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs); * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void stm32l4_dmadump(DMA_HANDLE handle, const struct stm32l4_dmaregs_s *regs, const char *msg); #else diff --git a/arch/arm/src/stm32l4/stm32l4_i2c.c b/arch/arm/src/stm32l4/stm32l4_i2c.c index 63b0f5b048..ce6c91b677 100644 --- a/arch/arm/src/stm32l4/stm32l4_i2c.c +++ b/arch/arm/src/stm32l4/stm32l4_i2c.c @@ -910,7 +910,7 @@ static void stm32l4_i2c_tracenew(FAR struct stm32l4_i2c_priv_s *priv, if (priv->tndx >= (CONFIG_I2C_NTRACE-1)) { - i2cerr("Trace table overflow\n"); + i2cerr("ERROR: Trace table overflow\n"); return; } @@ -951,7 +951,7 @@ static void stm32l4_i2c_traceevent(FAR struct stm32l4_i2c_priv_s *priv, if (priv->tndx >= (CONFIG_I2C_NTRACE-1)) { - i2cerr("Trace table overflow\n"); + i2cerr("ERROR: Trace table overflow\n"); return; } @@ -1722,7 +1722,7 @@ static int stm32l4_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg status = stm32l4_i2c_getstatus(priv); ret = -ETIMEDOUT; - i2cerr("Timed out: CR1: %08x status: %08x\n", + i2cerr("ERROR: Timed out: CR1: %08x status: %08x\n", stm32l4_i2c_getreg32(priv, STM32L4_I2C_CR1_OFFSET), status); /* "Note: When the STOP, START or PEC bit is set, the software must diff --git a/arch/arm/src/stm32l4/stm32l4_qspi.c b/arch/arm/src/stm32l4/stm32l4_qspi.c index 14053a598f..1fe106a083 100644 --- a/arch/arm/src/stm32l4/stm32l4_qspi.c +++ b/arch/arm/src/stm32l4/stm32l4_qspi.c @@ -405,7 +405,7 @@ static bool qspi_checkreg(struct stm32l4_qspidev_s *priv, bool wr, uint32_t valu { /* Yes... show how many times we did it */ - llerr("...[Repeats %d times]...\n", priv->ntimes); + spillinfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -439,7 +439,7 @@ static inline uint32_t qspi_getreg(struct stm32l4_qspidev_s *priv, #ifdef CONFIG_STM32L4_QSPI_REGDEBUG if (qspi_checkreg(priv, false, value, address)) { - llerr("%08x->%08x\n", address, value); + spillinfo("%08x->%08x\n", address, value); } #endif @@ -462,7 +462,7 @@ static inline void qspi_putreg(struct stm32l4_qspidev_s *priv, uint32_t value, #ifdef CONFIG_STM32L4_QSPI_REGDEBUG if (qspi_checkreg(priv, true, value, address)) { - llerr("%08x<-%08x\n", address, value); + spillinfo("%08x<-%08x\n", address, value); } #endif diff --git a/arch/arm/src/stm32l4/stm32l4x6xx_dma.c b/arch/arm/src/stm32l4/stm32l4x6xx_dma.c index e854d32261..e05173d82c 100644 --- a/arch/arm/src/stm32l4/stm32l4x6xx_dma.c +++ b/arch/arm/src/stm32l4/stm32l4x6xx_dma.c @@ -727,7 +727,7 @@ bool stm32l4_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void stm32l4_dmasample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs) { struct stm32l4_dma_s *dmach = (struct stm32l4_dma_s *)handle; @@ -755,20 +755,19 @@ void stm32l4_dmasample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void stm32l4_dmadump(DMA_HANDLE handle, const struct stm32l4_dmaregs_s *regs, const char *msg) { struct stm32l4_dma_s *dmach = (struct stm32l4_dma_s *)handle; uint32_t dmabase = DMA_BASE(dmach->base); - dmaerr("DMA Registers: %s\n", msg); - dmaerr(" ISR[%08x]: %08x\n", dmabase + STM32L4_DMA_ISR_OFFSET, regs->isr); - dmaerr(" CSELR[%08x]: %08x\n", dmabase + STM32L4_DMA_CSELR_OFFSET, regs->cselr); - dmaerr(" CCR[%08x]: %08x\n", dmach->base + STM32L4_DMACHAN_CCR_OFFSET, regs->ccr); - dmaerr(" CNDTR[%08x]: %08x\n", dmach->base + STM32L4_DMACHAN_CNDTR_OFFSET, regs->cndtr); - dmaerr(" CPAR[%08x]: %08x\n", dmach->base + STM32L4_DMACHAN_CPAR_OFFSET, regs->cpar); - dmaerr(" CMAR[%08x]: %08x\n", dmach->base + STM32L4_DMACHAN_CMAR_OFFSET, regs->cmar); + dmainfo("DMA Registers: %s\n", msg); + dmainfo(" ISR[%08x]: %08x\n", dmabase + STM32L4_DMA_ISR_OFFSET, regs->isr); + dmainfo(" CSELR[%08x]: %08x\n", dmabase + STM32L4_DMA_CSELR_OFFSET, regs->cselr); + dmainfo(" CCR[%08x]: %08x\n", dmach->base + STM32L4_DMACHAN_CCR_OFFSET, regs->ccr); + dmainfo(" CNDTR[%08x]: %08x\n", dmach->base + STM32L4_DMACHAN_CNDTR_OFFSET, regs->cndtr); + dmainfo(" CPAR[%08x]: %08x\n", dmach->base + STM32L4_DMACHAN_CPAR_OFFSET, regs->cpar); + dmainfo(" CMAR[%08x]: %08x\n", dmach->base + STM32L4_DMACHAN_CMAR_OFFSET, regs->cmar); } #endif - diff --git a/arch/arm/src/tiva/lm3s_ethernet.c b/arch/arm/src/tiva/lm3s_ethernet.c index bc22d7439d..e5e242c624 100644 --- a/arch/arm/src/tiva/lm3s_ethernet.c +++ b/arch/arm/src/tiva/lm3s_ethernet.c @@ -686,7 +686,7 @@ static void tiva_receive(struct tiva_driver_s *priv) /* We will have to drop this packet */ - nllerr("Bad packet size dropped (%d)\n", pktlen); + nllwarn("WARNING: "Bad packet size dropped (%d)\n", pktlen); NETDEV_RXERRORS(&priv->ld_dev); /* The number of bytes and words left to read is pktlen - 4 (including, @@ -867,7 +867,8 @@ static void tiva_receive(struct tiva_driver_s *priv) else #endif { - nllerr("Unsupported packet type dropped (%02x)\n", htons(ETHBUF->type)); + nllwarn("WARNING: Unsupported packet type dropped (%02x)\n", + htons(ETHBUF->type)); NETDEV_RXDROPPED(&priv->ld_dev); } } @@ -1024,7 +1025,7 @@ static void tiva_txtimeout(int argc, uint32_t arg, ...) /* Increment statistics */ - nllerr("Tx timeout\n"); + nllerr("ERROR: Tx timeout\n"); NETDEV_TXTIMEOUTS(&priv->ld_dev); /* Then reset the hardware */ @@ -1104,9 +1105,9 @@ static int tiva_ifup(struct net_driver_s *dev) uint32_t div; uint16_t phyreg; - nllerr("Bringing up: %d.%d.%d.%d\n", - dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, - (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); + nllinfo("Bringing up: %d.%d.%d.%d\n", + dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, + (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); /* Enable and reset the Ethernet controller */ @@ -1168,13 +1169,13 @@ static int tiva_ifup(struct net_driver_s *dev) * set */ - nllerr("Waiting for link\n"); + nllinfo("Waiting for link\n"); do { phyreg = tiva_phyread(priv, MII_MSR); } while ((phyreg & MII_MSR_LINKSTATUS) == 0); - nllerr("Link established\n"); + nllinfo("Link established\n"); /* Reset the receive FIFO */ @@ -1258,9 +1259,9 @@ static int tiva_ifdown(struct net_driver_s *dev) irqstate_t flags; uint32_t regval; - nllerr("Taking down: %d.%d.%d.%d\n", - dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, - (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); + nllinfo("Taking down: %d.%d.%d.%d\n", + dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, + (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); /* Cancel the TX poll timer and TX timeout timers */ @@ -1455,7 +1456,7 @@ static inline int tiva_ethinitialize(int intf) /* Check if the Ethernet module is present */ - nerr("Setting up eth%d\n", intf); + ninfo("Setting up eth%d\n", intf); #if TIVA_NETHCONTROLLERS > 1 # error "This debug check only works with one interface" diff --git a/arch/arm/src/tiva/tiva_adclow.c b/arch/arm/src/tiva/tiva_adclow.c index 809cb65b3b..e2e20b9196 100644 --- a/arch/arm/src/tiva/tiva_adclow.c +++ b/arch/arm/src/tiva/tiva_adclow.c @@ -686,7 +686,7 @@ static void tiva_adc_read(void *arg) * and should cause a full system stop. */ - allerr("PANIC!!! Invalid ADC device number given %d\n", sse->adc); + allerr("ERROR: Invalid ADC device number given %d\n", sse->adc); PANIC(); return; } @@ -879,8 +879,8 @@ int tiva_adc_initialize(const char *devpath, struct tiva_adc_cfg_s *cfg, adc = tiva_adc_struct_init(cfg); if (adc == NULL) { - aerr("Invalid ADC device number: expected=%d actual=%d\n", - 0, cfg->adc); + aerr("ERROR: Invalid ADC device number: expected=%d actual=%d\n", + 0, cfg->adc); return -ENODEV; } @@ -889,7 +889,7 @@ int tiva_adc_initialize(const char *devpath, struct tiva_adc_cfg_s *cfg, if (tiva_adc_enable(adc->devno, true) < 0) { aerr("ERROR: failure to power ADC peripheral (devno=%d)\n", - cfg->adc); + cfg->adc); return ret; } @@ -926,7 +926,7 @@ int tiva_adc_initialize(const char *devpath, struct tiva_adc_cfg_s *cfg, if (ret < 0) { aerr("ERROR: Failed to register %s to character driver: %d\n", - devpath, ret); + devpath, ret); return ret; } diff --git a/arch/arm/src/tiva/tiva_i2c.c b/arch/arm/src/tiva/tiva_i2c.c index f3e47ac795..1d0127aa04 100644 --- a/arch/arm/src/tiva/tiva_i2c.c +++ b/arch/arm/src/tiva/tiva_i2c.c @@ -959,7 +959,7 @@ static void tiva_i2c_tracenew(struct tiva_i2c_priv_s *priv, uint32_t status) if (priv->tndx >= (CONFIG_I2C_NTRACE-1)) { - i2cerr("I2C%d: ERROR: Trace table overflow\n", priv->config->devno); + i2cerr("ERROR: I2C%d trace table overflow\n", priv->config->devno); return; } @@ -1008,7 +1008,7 @@ static void tiva_i2c_traceevent(struct tiva_i2c_priv_s *priv, if (priv->tndx >= (CONFIG_I2C_NTRACE-1)) { - i2cerr("I2C%d: ERROR: Trace table overflow\n", priv->config->devno); + i2cerr("ERROR: I2C%d trace table overflow\n", priv->config->devno); return; } @@ -1907,7 +1907,7 @@ static int tiva_i2c_transfer(struct i2c_master_s *dev, struct i2c_msg_s *msgv, if (tiva_i2c_sem_waitdone(priv) < 0) { - i2cerr("I2C%d: ERROR: Timed out\n", priv->config->devno); + i2cerr("ERROR: I2C%d timed out\n", priv->config->devno); ret = -ETIMEDOUT; } #if 0 /* I2CM_CS_CLKTO */ @@ -1916,7 +1916,7 @@ static int tiva_i2c_transfer(struct i2c_master_s *dev, struct i2c_msg_s *msgv, else if ((priv->mstatus & (I2CM_CS_ERROR | I2CM_CS_ARBLST)) != 0) #endif { - i2cerr("I2C%d: ERROR: I2C error status: %08x\n", + i2cerr("ERROR: I2C%d I2C error status: %08x\n", priv->config->devno, priv->mstatus); if ((priv->mstatus & I2CM_CS_ARBLST) != 0) @@ -1963,7 +1963,7 @@ static int tiva_i2c_transfer(struct i2c_master_s *dev, struct i2c_msg_s *msgv, * other bits are valid. */ - i2cerr("I2C%d: ERROR: I2C still busy: %08x\n", + i2cerr("ERROR: I2C%d I2C still busy: %08x\n", priv->config->devno, regval); /* Reset and reinitialize the I2C hardware */ @@ -2212,7 +2212,7 @@ struct i2c_master_s *tiva_i2cbus_initialize(int port) #endif default: - i2cerr("I2C%d: ERROR: Not supported\n", port); + i2cerr("ERROR: I2C%d not supported\n", port); return NULL; }