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Trivial changes from review of last PR

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This commit is contained in:
Gregory Nutt 2016-06-09 09:39:41 -06:00
parent 2dbd6b3d99
commit 8c9bc6da79
2 changed files with 5 additions and 12 deletions
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14
arch/arm/src/kinetis/kinetis_clockconfig.c
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@ -1,8 +1,7 @@
/****************************************************************************
* arch/arm/src/kinetis/kinetis_clockconfig.c
* arch/arm/src/chip/kinetis_clockconfig.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -66,14 +65,6 @@
void __ramfunc__
kinesis_setdividers(uint32_t div1, uint32_t div2, uint32_t div3, uint32_t div4);
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
@ -132,11 +123,12 @@ void kinetis_pllconfig(void)
* HGO = 1 (High Gain Oscillator Select)
* RANGE = 2 (Oscillator of 8 MHz to 32 MHz)
*/
#ifdef BOARD_EXTAL_LP
putreg8(MCG_C2_EREFS | MCG_C2_RANGE_VHIGH, KINETIS_MCG_C2);
#else
putreg8(MCG_C2_EREFS | MCG_C2_HGO | MCG_C2_RANGE_VHIGH, KINETIS_MCG_C2);
#endif /*BOARD_EXTAL_LP*/
#endif /* BOARD_EXTAL_LP */
#endif
/* Released latched state of oscillator and GPIO */

3
configs/teensy-3.x/include/board.h
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@ -2,7 +2,7 @@
* configs/teensy-3.x/include/board.h
* include/arch/board/board.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -63,6 +63,7 @@
* the C1 divider must be set so that the FLL clock is between 31.25 and 39.0625 khz.
* For teensy-3.x that works out to a divider of 512.
*/
#define BOARD_FR_DIV (4 << 3)
#define BOARD_EXTAL_FREQ 16000000 /* 16MHz crystal frequency (REFCLK) */
#define BOARD_XTAL32_FREQ 32768 /* 32KHz RTC Oscillator (not populated) */