arch/arm/src/stm32f: Added support for TICKLESS mode.

arch/arm/Kconfig

@@ -328,6 +328,8 @@ config ARCH_CHIP_STM32F7
 	select ARCH_HAVE_SPI_BITORDER
 	select ARM_HAVE_MPU_UNIFIED
 	select ARMV7M_HAVE_STACKCHECK
+	select ARCH_HAVE_TICKLESS
+	select ARCH_HAVE_TIMEKEEPING
 	---help---
 		STMicro STM32 architectures (ARM Cortex-M7).
 

arch/arm/src/stm32f7/Kconfig

@@ -2449,6 +2449,27 @@ config STM32F7_DMACAPABLE
 
 menu "Timer Configuration"
 
+if SCHED_TICKLESS
+
+config STM32F7_TICKLESS_TIMER
+	int "Tickless hardware timer"
+	default 2
+	range 1 14
+	---help---
+		If the Tickless OS feature is enabled, then one clock must be
+		assigned to provided the timer needed by the OS.
+
+config STM32F7_TICKLESS_CHANNEL
+	int "Tickless timer channel"
+	default 1
+	range 1 4
+	---help---
+		If the Tickless OS feature is enabled, the one clock must be
+		assigned to provided the free-running timer needed by the OS
+		and one channel on that clock is needed to handle intervals.
+
+endif # SCHED_TICKLESS
+
 config STM32F7_TIM1_PWM
 	bool "TIM1 PWM"
 	default n

arch/arm/src/stm32f7/stm32_tim.c

@@ -66,24 +66,27 @@
 /************************************************************************************
  * Private Types
  ************************************************************************************/
+
 /* Configuration ********************************************************************/
+
 /* Timer devices may be used for different purposes.  Such special purposes include:
  *
- * - To generate modulated outputs for such things as motor control.  If CONFIG_STM32F7_TIMn
+ * - To generate modulated outputs for such things as motor control.  If
- *   is defined then the CONFIG_STM32F7_TIMn_PWM may also be defined to indicate that
+ *   CONFIG_STM32F7_TIMn is defined then the CONFIG_STM32F7_TIMn_PWM may also be
- *   the timer is intended to be used for pulsed output modulation.
+ *   defined to indicate that the timer is intended to be used for pulsed output
+ *   modulation.
  *
  * - To control periodic ADC input sampling.  If CONFIG_STM32F7_TIMn is defined then
- *   CONFIG_STM32F7_TIMn_ADC may also be defined to indicate that timer "n" is intended
+ *   CONFIG_STM32F7_TIMn_ADC may also be defined to indicate that timer "n" is
- *   to be used for that purpose.
+ *   intended to be used for that purpose.
  *
  * - To control periodic DAC outputs.  If CONFIG_STM32F7_TIMn is defined then
- *   CONFIG_STM32F7_TIMn_DAC may also be defined to indicate that timer "n" is intended
+ *   CONFIG_STM32F7_TIMn_DAC may also be defined to indicate that timer "n" is
- *   to be used for that purpose.
+ *   intended to be used for that purpose.
  *
  * - To use a Quadrature Encoder.  If CONFIG_STM32F7_TIMn is defined then
- *   CONFIG_STM32F7_TIMn_QE may also be defined to indicate that timer "n" is intended
+ *   CONFIG_STM32F7_TIMn_QE may also be defined to indicate that timer "n" is
- *   to be used for that purpose.
+ *   intended to be used for that purpose.
  *
  * In any of these cases, the timer will not be used by this timer module.
  */
@@ -228,9 +231,8 @@
 #endif
 #endif
 
-
+/* This module then only compiles if there are enabled timers that are not
-/* This module then only compiles if there are enabled timers that are not intended for
+ * intended for some other purpose.
- * some other purpose.
  */
 
 #if defined(CONFIG_STM32F7_TIM1)  || defined(CONFIG_STM32F7_TIM2)  || \
@@ -325,6 +327,70 @@ static void stm32_tim_disable(FAR struct stm32_tim_dev_s *dev)
   stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val);
 }
 
+/************************************************************************************
+ * Name: stm32_tim_getwidth
+ ************************************************************************************/
+
+static int stm32_tim_getwidth(FAR struct stm32_tim_dev_s *dev)
+{
+  /* Only TIM2 and TIM5 timers may be 32-bits in width
+   *
+   * Reference Table 2 of en.DM00042534.pdf
+   */
+
+  switch (((struct stm32_tim_priv_s *)dev)->base)
+    {
+      /* TIM2 is 32-bits on all except F10x, L0x, and L1x lines */
+
+#if defined(CONFIG_STM32F7_TIM2)
+      case STM32_TIM2_BASE:
+        return 32;
+#endif
+
+      /* TIM5 is 32-bits on all except F10x lines */
+
+#if defined(CONFIG_STM32F7_TIM5)
+      case STM32_TIM5_BASE:
+        return 32;
+#endif
+
+      /* All others are 16-bit times */
+
+      default:
+        return 16;
+    }
+}
+
+/************************************************************************************
+ * Name: stm32_tim_getcounter
+ ************************************************************************************/
+
+static uint32_t stm32_tim_getcounter(FAR struct stm32_tim_dev_s *dev)
+{
+  DEBUGASSERT(dev != NULL);
+  return stm32_tim_getwidth(dev) > 16 ?
+    stm32_getreg32(dev, STM32_BTIM_CNT_OFFSET) :
+    (uint32_t)stm32_getreg16(dev, STM32_BTIM_CNT_OFFSET);
+}
+
+/************************************************************************************
+ * Name: stm32_tim_setcounter
+ ************************************************************************************/
+
+static void stm32_tim_setcounter(FAR struct stm32_tim_dev_s *dev, uint32_t count)
+{
+  DEBUGASSERT(dev != NULL);
+
+  if (stm32_tim_getwidth(dev) > 16)
+    {
+      stm32_putreg32(dev, STM32_BTIM_CNT_OFFSET, count);
+    }
+  else
+    {
+      stm32_putreg16(dev, STM32_BTIM_CNT_OFFSET, (uint16_t)count);
+    }
+}
+
 /* Reset timer into system default state, but do not affect output/input pins */
 
 static void stm32_tim_reset(FAR struct stm32_tim_dev_s *dev)
@@ -601,6 +667,12 @@ static void stm32_tim_disableint(FAR struct stm32_tim_dev_s *dev, int source)
   stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, ATIM_DIER_UIE, 0);
 }
 
+static int stm32_tim_checkint(FAR struct stm32_tim_dev_s *dev, int source)
+{
+  uint16_t regval = stm32_getreg16(dev, STM32_BTIM_SR_OFFSET);
+  return (regval & source) ? 1 : 0;
+}
+
 static void stm32_tim_ackint(FAR struct stm32_tim_dev_s *dev, int source)
 {
   stm32_putreg16(dev, STM32_BTIM_SR_OFFSET, ~ATIM_SR_UIF);
@@ -641,8 +713,9 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t m
         break;
 
       case STM32_TIM_MODE_UPDOWN:
+        /* Our default: Interrupts are generated on compare, when counting down */
+
         val |= ATIM_CR1_CENTER1;
-        // Our default: Interrupts are generated on compare, when counting down
         break;
 
       case STM32_TIM_MODE_PULSE:
@@ -699,7 +772,6 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
       return -EINVAL;
     }
 
-
   /* Decode configuration */
 
   switch (mode & STM32_TIM_CH_MODE_MASK)
@@ -708,12 +780,14 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
         break;
 
       case STM32_TIM_CH_OUTPWM:
-        ccmr_val  =  (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) + ATIM_CCMR1_OC1PE;
+        ccmr_val  = (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) +
+                     ATIM_CCMR1_OC1PE;
         ccer_val |= ATIM_CCER_CC1E << (channel << 2);
         break;
 
       case STM32_TIM_CH_OUTTOGGLE:
-          ccmr_val  =  (ATIM_CCMR_MODE_OCREFTOG << ATIM_CCMR1_OC1M_SHIFT) + ATIM_CCMR1_OC1PE;
+          ccmr_val  = (ATIM_CCMR_MODE_OCREFTOG << ATIM_CCMR1_OC1M_SHIFT) +
+                       ATIM_CCMR1_OC1PE;
           ccer_val |= ATIM_CCER_CC1E << (channel << 2);
           break;
 
@@ -1151,16 +1225,20 @@ static int stm32_tim_getcapture(FAR struct stm32_tim_dev_s *dev, uint8_t channel
 
 struct stm32_tim_ops_s stm32_tim_ops =
 {
-  .setmode        = &stm32_tim_setmode,
+  .setmode    = stm32_tim_setmode,
-  .setclock       = &stm32_tim_setclock,
+  .setclock   = stm32_tim_setclock,
-  .setperiod      = &stm32_tim_setperiod,
+  .setperiod  = stm32_tim_setperiod,
-  .setchannel     = &stm32_tim_setchannel,
+  .getcounter = stm32_tim_getcounter,
-  .setcompare     = &stm32_tim_setcompare,
+  .setcounter = stm32_tim_setcounter,
-  .getcapture     = &stm32_tim_getcapture,
+  .getwidth   = stm32_tim_getwidth,
-  .setisr         = &stm32_tim_setisr,
+  .setchannel = stm32_tim_setchannel,
-  .enableint      = &stm32_tim_enableint,
+  .setcompare = stm32_tim_setcompare,
-  .disableint     = &stm32_tim_disableint,
+  .getcapture = stm32_tim_getcapture,
-  .ackint         = &stm32_tim_ackint
+  .setisr     = stm32_tim_setisr,
+  .enableint  = stm32_tim_enableint,
+  .disableint = stm32_tim_disableint,
+  .ackint     = stm32_tim_ackint,
+  .checkint   = stm32_tim_checkint,
 };
 
 #ifdef CONFIG_STM32F7_TIM1
@@ -1288,7 +1366,6 @@ struct stm32_tim_priv_s stm32_tim14_priv =
 };
 #endif
 
-
 /************************************************************************************
  * Public Function - Initialization
  ************************************************************************************/

arch/arm/src/stm32f7/stm32_tim.h

@@ -58,6 +58,9 @@
 #define STM32_TIM_SETMODE(d,mode)       ((d)->ops->setmode(d,mode))
 #define STM32_TIM_SETCLOCK(d,freq)      ((d)->ops->setclock(d,freq))
 #define STM32_TIM_SETPERIOD(d,period)   ((d)->ops->setperiod(d,period))
+#define STM32_TIM_GETCOUNTER(d)         ((d)->ops->getcounter(d))
+#define STM32_TIM_SETCOUNTER(d,c)       ((d)->ops->setcounter(d,c))
+#define STM32_TIM_GETWIDTH(d)           ((d)->ops->getwidth(d))
 #define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode))
 #define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp))
 #define STM32_TIM_GETCAPTURE(d,ch)      ((d)->ops->getcapture(d,ch))
@@ -65,6 +68,7 @@
 #define STM32_TIM_ENABLEINT(d,s)        ((d)->ops->enableint(d,s))
 #define STM32_TIM_DISABLEINT(d,s)       ((d)->ops->disableint(d,s))
 #define STM32_TIM_ACKINT(d,s)           ((d)->ops->ackint(d,s))
+#define STM32_TIM_CHECKINT(d,s)         ((d)->ops->checkint(d,s))
 
 /************************************************************************************
  * Public Types
@@ -160,9 +164,12 @@ struct stm32_tim_ops_s
   int  (*setmode)(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode);
   int  (*setclock)(FAR struct stm32_tim_dev_s *dev, uint32_t freq);
   void (*setperiod)(FAR struct stm32_tim_dev_s *dev, uint32_t period);
+  uint32_t (*getcounter)(FAR struct stm32_tim_dev_s *dev);
+  void (*setcounter)(FAR struct stm32_tim_dev_s *dev, uint32_t count);
 
   /* General and Advanced Timers Adds */
 
+  int  (*getwidth)(FAR struct stm32_tim_dev_s *dev);
   int  (*setchannel)(FAR struct stm32_tim_dev_s *dev, uint8_t channel,
                      stm32_tim_channel_t mode);
   int  (*setcompare)(FAR struct stm32_tim_dev_s *dev, uint8_t channel,
@@ -171,11 +178,11 @@ struct stm32_tim_ops_s
 
   /* Timer interrupts */
 
-  int  (*setisr)(FAR struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg,
+  int  (*setisr)(FAR struct stm32_tim_dev_s *dev, xcpt_t handler, void * arg, int source);
-                 int source);
   void (*enableint)(FAR struct stm32_tim_dev_s *dev, int source);
   void (*disableint)(FAR struct stm32_tim_dev_s *dev, int source);
   void (*ackint)(FAR struct stm32_tim_dev_s *dev, int source);
+  int  (*checkint)(FAR struct stm32_tim_dev_s *dev, int source);
 };
 
 /************************************************************************************