Fix OpenOCD config
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2757 42af7a65-404d-4744-a932-0658087f49c3
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@ -135,7 +135,8 @@ void lpc17_clockconfig(void)
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/* Wait for PLL to report that it is connected and enabled */
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while ((getreg32(LPC17_SYSCON_PLL0STAT) & (SYSCON_PLL0STAT_PLLE|SYSCON_PLL0STAT_PLLC)) == 0);
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while ((getreg32(LPC17_SYSCON_PLL0STAT) & (SYSCON_PLL0STAT_PLLE|SYSCON_PLL0STAT_PLLC))
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!= (SYSCON_PLL0STAT_PLLE|SYSCON_PLL0STAT_PLLC));
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#endif
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/* PLL1 receives its clock input from the main oscillator only and can be used to
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@ -173,7 +174,8 @@ void lpc17_clockconfig(void)
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/* Wait for PLL to report that it is connected and enabled */
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while ((getreg32(LPC17_SYSCON_PLL1STAT) & (SYSCON_PLL1STAT_PLLE|SYSCON_PLL1STAT_PLLC)) == 0);
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while ((getreg32(LPC17_SYSCON_PLL1STAT) & (SYSCON_PLL1STAT_PLLE|SYSCON_PLL1STAT_PLLC))
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!= (SYSCON_PLL1STAT_PLLE|SYSCON_PLL1STAT_PLLC));
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#else
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/* Otherwise, setup up the USB clock divider to generate the USB clock from PLL0 */
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@ -158,7 +158,7 @@
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* BAUD <= CCLK / 16 / MinDL
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*/
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#if CONSOLE_BAUD < (LPC17_CCLK / 16 / UART_MINDL )
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#if CONSOLE_BAUD < (LPC17_CCLK / 16 / UART_MINDL)
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# define CONSOLE_CCLKDIV SYSCON_PCLKSEL_CCLK
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# define CONSOLE_NUMERATOR (LPC17_CCLK)
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@ -173,7 +173,7 @@
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* BAUD <= CCLK / 8 / MinDL
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*/
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#elif CONSOLE_BAUD < (LPC17_CCLK / 8 / UART_MINDL )
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#elif CONSOLE_BAUD < (LPC17_CCLK / 8 / UART_MINDL)
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# define CONSOLE_CCLKDIV SYSCON_PCLKSEL_CCLK2
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# define CONSOLE_NUMERATOR (LPC17_CCLK / 2)
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@ -188,7 +188,7 @@
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* BAUD <= CCLK / 4 / MinDL
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*/
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#elif CONSOLE_BAUD < (LPC17_CCLK / 4 / UART_MINDL )
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#elif CONSOLE_BAUD < (LPC17_CCLK / 4 / UART_MINDL)
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# define CONSOLE_CCLKDIV SYSCON_PCLKSEL_CCLK4
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# define CONSOLE_NUMERATOR (LPC17_CCLK / 4)
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@ -203,7 +203,7 @@
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* BAUD <= CCLK / 2 / MinDL
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*/
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#else /* if CONSOLE_BAUD < (LPC17_CCLK / 2 / UART_MINDL ) */
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#else /* if CONSOLE_BAUD < (LPC17_CCLK / 2 / UART_MINDL) */
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# define CONSOLE_CCLKDIV SYSCON_PCLKSEL_CCLK8
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# define CONSOLE_NUMERATOR (LPC17_CCLK / 8)
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#endif
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