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Fix OpenOCD config

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2757 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2010-06-22 03:43:47 +00:00
parent ff7790385b
commit 8db4c9e77b
2 changed files with 8 additions and 6 deletions
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6
arch/arm/src/lpc17xx/lpc17_clockconfig.c
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@ -135,7 +135,8 @@ void lpc17_clockconfig(void)
/* Wait for PLL to report that it is connected and enabled */ /* Wait for PLL to report that it is connected and enabled */
while ((getreg32(LPC17_SYSCON_PLL0STAT) & (SYSCON_PLL0STAT_PLLE|SYSCON_PLL0STAT_PLLC)) == 0); while ((getreg32(LPC17_SYSCON_PLL0STAT) & (SYSCON_PLL0STAT_PLLE|SYSCON_PLL0STAT_PLLC))
!= (SYSCON_PLL0STAT_PLLE|SYSCON_PLL0STAT_PLLC));
#endif #endif
/* PLL1 receives its clock input from the main oscillator only and can be used to /* PLL1 receives its clock input from the main oscillator only and can be used to
@ -173,7 +174,8 @@ void lpc17_clockconfig(void)
/* Wait for PLL to report that it is connected and enabled */ /* Wait for PLL to report that it is connected and enabled */
while ((getreg32(LPC17_SYSCON_PLL1STAT) & (SYSCON_PLL1STAT_PLLE|SYSCON_PLL1STAT_PLLC)) == 0); while ((getreg32(LPC17_SYSCON_PLL1STAT) & (SYSCON_PLL1STAT_PLLE|SYSCON_PLL1STAT_PLLC))
!= (SYSCON_PLL1STAT_PLLE|SYSCON_PLL1STAT_PLLC));
#else #else
/* Otherwise, setup up the USB clock divider to generate the USB clock from PLL0 */ /* Otherwise, setup up the USB clock divider to generate the USB clock from PLL0 */