diff --git a/ChangeLog b/ChangeLog index df87260fcb..3cbfc42bea 100644 --- a/ChangeLog +++ b/ChangeLog @@ -4992,4 +4992,6 @@ (2013-6-16). * configs/sam3u-ek/src/up_touchscreen.c: Fix polarity of the /PENIRQ signal (it is active low) (2013-6-16). + * configs/sam3u-ek/include/board.h: The SAM3U-EK board now runs at + 96MHz. This might have broken some things? (2013-6-17). diff --git a/configs/sam3u-ek/README.txt b/configs/sam3u-ek/README.txt index b26b96e4a4..3ee86c94f9 100644 --- a/configs/sam3u-ek/README.txt +++ b/configs/sam3u-ek/README.txt @@ -2,7 +2,8 @@ README ^^^^^^ This README discusses issues unique to NuttX configurations for the Atmel -SAM3U-EK development board featuring the ATAM3U +SAM3U-EK development board featuring the ATAM3U. This board features the +AT91SAM3U4E MCU running at 96MHz. Contents ^^^^^^^^ diff --git a/configs/sam3u-ek/include/board.h b/configs/sam3u-ek/include/board.h index 98b3e74b6a..1c0d7230ad 100644 --- a/configs/sam3u-ek/include/board.h +++ b/configs/sam3u-ek/include/board.h @@ -55,21 +55,38 @@ /* Clocking *************************************************************************/ /* After power-on reset, the sam3u device is running on a 4MHz internal RC. These - * definitions will configure clocking with MCK = 48MHz, PLLA = 96, and CPU=48MHz. + * definitions will configure clocking + * + * MAINOSC: Frequency = 12MHz (crysta) + * PLLA: PLL Divider = 1, Multiplier = 16 to generate PLLACK = 192MHz + * Master Clock (MCK): Source = PLLACK, Prescalar = 1 to generate MCK = 96MHz + * CPU clock: 96MHz */ -/* Main oscillator register settings */ +/* Main oscillator register settings. + * + * The start up time should be should be: + * Start Up Time = 8 * MOSCXTST / SLCK = 56 Slow Clock Cycles. + */ -#define BOARD_CKGR_MOR_MOSCXTST (63 << PMC_CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */ +#define BOARD_CKGR_MOR_MOSCXTST (62 << PMC_CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */ -/* PLLA configuration */ +/* PLLA configuration. + * + * Divider = 1 + * Multipler = 16 + */ -#define BOARD_CKGR_PLLAR_MUL (7 << PMC_CKGR_PLLAR_MUL_SHIFT) +#define BOARD_CKGR_PLLAR_MUL (15 << PMC_CKGR_PLLAR_MUL_SHIFT) #define BOARD_CKGR_PLLAR_STMODE PMC_CKGR_PLLAR_STMODE_FAST #define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) #define BOARD_CKGR_PLLAR_DIV PMC_CKGR_PLLAR_DIV_BYPASS -/* PMC master clock register settings */ +/* PMC master clock register settings. + * + * Source = PLLA + * Divider = 2 + */ #define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLA #define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV2 @@ -80,10 +97,10 @@ /* Resulting frequencies */ -#define BOARD_MAINOSC_FREQUENCY (12000000) -#define BOARD_MCK_FREQUENCY (48000000) -#define BOARD_PLLA_FREQUENCY (96000000) -#define BOARD_CPU_FREQUENCY (48000000) +#define BOARD_MAINOSC_FREQUENCY (12000000) /* MAINOSC: 12MHz crystal on-board */ +#define BOARD_PLLA_FREQUENCY (192000000) /* PLLACK: 16 * 12Mhz / 1 */ +#define BOARD_MCK_FREQUENCY (96000000) /* MCK: PLLACK / 2 */ +#define BOARD_CPU_FREQUENCY (96000000) /* CPU: MCK */ /* HSMCI clocking * @@ -92,24 +109,35 @@ * * MCI_SPEED = MCK / (2*(CLKDIV+1)) * CLKDIV = MCI / MCI_SPEED / 2 - 1 + * + * Where CLKDIV has a range of 0-255. */ -/* MCK = 48MHz, CLKDIV = 59, MCI_SPEED = 48MHz / 2 * (59+1) = 400 KHz */ +/* MCK = 96MHz, CLKDIV = 119, MCI_SPEED = 96MHz / 2 * (119+1) = 400 KHz */ -#define HSMCI_INIT_CLKDIV (59 << HSMCI_MR_CLKDIV_SHIFT) +#define HSMCI_INIT_CLKDIV (119 << HSMCI_MR_CLKDIV_SHIFT) -/* MCK = 48MHz, CLKDIV = 1, MCI_SPEED = 48MHz / 2 * (1+1) = 12 MHz */ +/* MCK = 96MHz, CLKDIV = 3, MCI_SPEED = 96MHz / 2 * (3+1) = 12 MHz */ #define HSMCI_MMCXFR_CLKDIV (3 << HSMCI_MR_CLKDIV_SHIFT) -/* MCK = 48MHz, CLKDIV = 0, MCI_SPEED = 48MHz / 2 * (0+1) = 24 MHz */ +/* MCK = 96MHz, CLKDIV = 1, MCI_SPEED = 96MHz / 2 * (1+1) = 24 MHz */ -#define HSMCI_SDXFR_CLKDIV (0 << HSMCI_MR_CLKDIV_SHIFT) +#define HSMCI_SDXFR_CLKDIV (3 << HSMCI_MR_CLKDIV_SHIFT) #define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV -/* FLASH wait states */ +/* FLASH wait states + * + * FWS Max frequency + * 1.62V 1.8V + * --- ----- ------ + * 0 24MHz 27MHz + * 1 40MHz 47MHz + * 2 72MHz 84MHz + * 3 84MHz 96MHz + */ -#define BOARD_FWS 2 +#define BOARD_FWS 3 /* LED definitions ******************************************************************/ diff --git a/configs/sam3u-ek/knsh/defconfig b/configs/sam3u-ek/knsh/defconfig index e410ef0e74..1681e4d3e9 100644 --- a/configs/sam3u-ek/knsh/defconfig +++ b/configs/sam3u-ek/knsh/defconfig @@ -193,7 +193,7 @@ CONFIG_ARCH_HAVE_RAMVECTORS=y # # Board Settings # -CONFIG_BOARD_LOOPSPERMSEC=4768 +CONFIG_BOARD_LOOPSPERMSEC=8720 # CONFIG_ARCH_CALIBRATION is not set CONFIG_DRAM_START=0x20000000 CONFIG_DRAM_SIZE=32768 diff --git a/configs/sam3u-ek/nsh/defconfig b/configs/sam3u-ek/nsh/defconfig index e5181e0281..2193fbed53 100644 --- a/configs/sam3u-ek/nsh/defconfig +++ b/configs/sam3u-ek/nsh/defconfig @@ -185,7 +185,7 @@ CONFIG_ARCH_HAVE_RAMVECTORS=y # # Board Settings # -CONFIG_BOARD_LOOPSPERMSEC=4768 +CONFIG_BOARD_LOOPSPERMSEC=8720 # CONFIG_ARCH_CALIBRATION is not set CONFIG_DRAM_START=0x20000000 CONFIG_DRAM_SIZE=32768 diff --git a/configs/sam3u-ek/nx/defconfig b/configs/sam3u-ek/nx/defconfig index 9b11817be7..c78bfe7840 100644 --- a/configs/sam3u-ek/nx/defconfig +++ b/configs/sam3u-ek/nx/defconfig @@ -185,7 +185,7 @@ CONFIG_ARCH_HAVE_RAMVECTORS=y # # Board Settings # -CONFIG_BOARD_LOOPSPERMSEC=4768 +CONFIG_BOARD_LOOPSPERMSEC=8720 # CONFIG_ARCH_CALIBRATION is not set CONFIG_DRAM_START=0x20000000 CONFIG_DRAM_SIZE=32768 diff --git a/configs/sam3u-ek/ostest/defconfig b/configs/sam3u-ek/ostest/defconfig index b760af9839..bbc7e93abb 100644 --- a/configs/sam3u-ek/ostest/defconfig +++ b/configs/sam3u-ek/ostest/defconfig @@ -185,7 +185,7 @@ CONFIG_ARCH_HAVE_RAMVECTORS=y # # Board Settings # -CONFIG_BOARD_LOOPSPERMSEC=4768 +CONFIG_BOARD_LOOPSPERMSEC=8720 # CONFIG_ARCH_CALIBRATION is not set CONFIG_DRAM_START=0x20000000 CONFIG_DRAM_SIZE=32768