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arch/risc-v: Correct handling of QPFPU and DPFPU

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If QPFPU enabled we will never enter the expected QPFPU branch since
option QPFPU depend on DPFPU.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit is contained in:
Huang Qi 2022-03-09 09:10:44 +08:00 committed by Petro Karashchenko
parent b690262aac
commit 8dedf1d9af
2 changed files with 7 additions and 7 deletions
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6
arch/risc-v/include/irq.h
View File

@ -183,10 +183,10 @@
#define INT_XCPT_SIZE (INT_REG_SIZE * INT_XCPT_REGS)
#ifdef CONFIG_ARCH_RV32
# if defined(CONFIG_ARCH_DPFPU)
# define FPU_REG_SIZE 2
# elif defined(CONFIG_ARCH_QPFPU)
# if defined(CONFIG_ARCH_QPFPU)
# define FPU_REG_SIZE 4
# elif defined(CONFIG_ARCH_DPFPU)
# define FPU_REG_SIZE 2
# elif defined(CONFIG_ARCH_FPU)
# define FPU_REG_SIZE 1
# endif

8
arch/risc-v/src/common/riscv_fpu.S
View File

@ -48,12 +48,12 @@
#define FS_CLEAN 0x4000
#define FS_DIRTY 0x6000
#if defined(CONFIG_ARCH_DPFPU)
# define FLOAD fld
# define FSTORE fsd
#elif defined(CONFIG_ARCH_QPFPU)
#if defined(CONFIG_ARCH_QPFPU)
# define FLOAD flq
# define FSTORE fsq
#elif defined(CONFIG_ARCH_DPFPU)
# define FLOAD fld
# define FSTORE fsd
#else
# define FLOAD flw
# define FSTORE fsw