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Add a OS test kernel build configuration for the STM32F4Discovery board

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5775 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2013-03-22 16:19:59 +00:00
parent 24be89c3ce
commit 8df28685be
7 changed files with 17 additions and 55 deletions
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8
arch/arm/src/armv7-m/exc_return.h
View File

@ -112,14 +112,6 @@
EXC_RETURN_THREAD_MODE | EXC_RETURN_PROCESS_STACK)
#endif
/* In the kernel build is not selected, then all threads run in privileged thread
* mode.
*/
#ifdef CONFIG_NUTTX_KERNEL
# define EXC_RETURN 0xfffffff9
#endif
/************************Th************************************************************
* Inline Functions
************************************************************************************/

11
arch/arm/src/kinetis/kinetis_vectors.S
View File

@ -41,6 +41,8 @@
#include <nuttx/config.h>
#include <arch/irq.h>
#include "exc_return.h"
/************************************************************************************************
* Preprocessor Definitions
************************************************************************************************/
@ -59,13 +61,6 @@
#define IDLE_STACK (_ebss+CONFIG_IDLETHREAD_STACKSIZE)
#define HEAP_BASE (_ebss+CONFIG_IDLETHREAD_STACKSIZE)
/* The Cortex-M4 return from interrupt is unusual. We provide the following special
* address to the BX instruction. The particular value also forces a return to
* thread mode and covers state from the main stack point, the MSP (vs. the MSP).
*/
#define EXC_RETURN 0xfffffff9
/************************************************************************************************
* Global Symbols
************************************************************************************************/
@ -690,7 +685,7 @@ kinetis_common:
* actually occurs with interrupts still disabled).
*/
ldr r14, =EXC_RETURN /* Load the special value */
ldr r14, =EXC_RETURN_PRIVTHR /* Load the special value */
#endif
/* Restore the interrupt state */

9
arch/arm/src/lm/lm_vectors.S
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@ -60,13 +60,6 @@
#define IDLE_STACK (_ebss+CONFIG_IDLETHREAD_STACKSIZE-4)
#define HEAP_BASE (_ebss+CONFIG_IDLETHREAD_STACKSIZE-4)
/* The Cortex-M3 return from interrupt is unusual. We provide the following special
* address to the BX instruction. The particular value also forces a return to
* thread mode and covers state from the main stack point, the MSP (vs. the MSP).
*/
#define EXC_RETURN 0xfffffff9
/************************************************************************************
* Global Symbols
************************************************************************************/
@ -288,7 +281,7 @@ lm_irqcommon:
* actually occurs with interrupts still disabled).
*/
ldr r14, =EXC_RETURN /* Load the special value */
ldr r14, =EXC_RETURN_PRIVTHR /* Load the special value */
#endif
/* Restore the interrupt state */

9
arch/arm/src/lpc17xx/lpc17_vectors.S
View File

@ -64,13 +64,6 @@
#define IDLE_STACK (_ebss+CONFIG_IDLETHREAD_STACKSIZE-4)
#define HEAP_BASE (_ebss+CONFIG_IDLETHREAD_STACKSIZE)
/* The Cortex-M3 return from interrupt is unusual. We provide the following special
* address to the BX instruction. The particular value also forces a return to
* thread mode and covers state from the main stack point, the MSP (vs. the MSP).
*/
#define EXC_RETURN 0xfffffff9
/************************************************************************************************
* Global Symbols
************************************************************************************************/
@ -378,7 +371,7 @@ lpc17_common:
* actually occurs with interrupts still disabled).
*/
ldr r14, =EXC_RETURN /* Load the special value */
ldr r14, =EXC_RETURN_PRIVTHR /* Load the special value */
#endif
/* Restore the interrupt state */

9
arch/arm/src/sam3u/sam3u_vectors.S
View File

@ -65,13 +65,6 @@
#define IDLE_STACK (_ebss+CONFIG_IDLETHREAD_STACKSIZE)
#define HEAP_BASE (_ebss+CONFIG_IDLETHREAD_STACKSIZE)
/* The Cortex-M3 return from interrupt is unusual. We provide the following special
* address to the BX instruction. The particular value also forces a return to
* thread mode and covers state from the main stack point, the MSP (vs. the MSP).
*/
#define EXC_RETURN 0xfffffff9
/************************************************************************************************
* Global Symbols
************************************************************************************************/
@ -406,7 +399,7 @@ sam3u_common:
* actually occurs with interrupts still disabled).
*/
ldr r14, =EXC_RETURN /* Load the special value */
ldr r14, =EXC_RETURN_PRIVTHR /* Load the special value */
#endif
/* Restore the interrupt state */

2
arch/arm/src/stm32/stm32_allocateheap.c
View File

@ -48,8 +48,10 @@
#include <arch/board/board.h>
#include "chip.h"
#include "mpu.h"
#include "up_arch.h"
#include "up_internal.h"
#include "stm32_mpuinit.h"
/****************************************************************************
* Private Definitions

10
arch/arm/src/stm32/stm32_vectors.S
View File

@ -43,6 +43,7 @@
#include <arch/irq.h>
#include "chip.h"
#include "exc_return.h"
/************************************************************************************
* Configuration
@ -72,13 +73,6 @@
#define IDLE_STACK (_ebss+CONFIG_IDLETHREAD_STACKSIZE-4)
#define HEAP_BASE (_ebss+CONFIG_IDLETHREAD_STACKSIZE)
/* The Cortex-M3 return from interrupt is unusual. We provide the following special
* address to the BX instruction. The particular value also forces a return to
* thread mode and covers state from the main stack point, the MSP (vs. the MSP).
*/
#define EXC_RETURN 0xfffffff9
/************************************************************************************
* Global Symbols
************************************************************************************/
@ -387,7 +381,7 @@ stm32_common:
* actually occurs with interrupts still disabled).
*/
ldr r14, =EXC_RETURN /* Load the special value */
ldr r14, =EXC_RETURN_PRIVTHR /* Load the special value */
#endif
/* Restore the interrupt state */