Change naming from cp_XYZ_cache() to arch_XYP_cache() so that all cache operations will pick up L2 support if it is enabled
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@ -187,8 +187,8 @@ int nor_main(int argc, char *argv)
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/* Invalidate caches and TLBs */
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cp15_invalidate_icache();
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cp15_invalidate_dcache_all();
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arch_invalidate_icache();
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arch_invalidate_dcache_all();
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cp15_invalidate_tlbs();
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/* Then jump into NOR flash */
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@ -134,7 +134,7 @@ int dram_main(int argc, char *argv)
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* we disable caching.
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*/
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cp15_clean_dcache((uintptr_t)SAM_DDRCS_VSECTION,
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arch_clean_dcache((uintptr_t)SAM_DDRCS_VSECTION,
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(uintptr_t)(SAM_DDRCS_VSECTION + CONFIG_SAMA5_DDRCS_SIZE));
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/* Interrupts must be disabled through the following. In this configuration,
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@ -155,8 +155,8 @@ int dram_main(int argc, char *argv)
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/* Invalidate caches and TLBs */
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cp15_invalidate_icache();
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cp15_invalidate_dcache_all();
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arch_invalidate_icache();
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arch_invalidate_dcache_all();
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cp15_invalidate_tlbs();
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/* Then jump into NOR flash */
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