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xtensa:dcache_clean: use DCACHE_LINZESIZE instead of DCACHE_SIZE

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Clean_dcache use DCACHE_LINZESIZE instead of DCACHE_SIZE in addr loop

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
This commit is contained in:
zhuyanlin 2021-09-13 10:44:15 +08:00 committed by Xiang Xiao
parent 099e9fb4f7
commit 8e6fbe700e
1 changed files with 3 additions and 3 deletions
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6
arch/xtensa/src/common/xtensa_cache.c
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@ -315,9 +315,9 @@ void up_clean_dcache(uintptr_t start, uintptr_t end)
{ {
/* Align to XCHAL_DCACHE_SIZE */ /* Align to XCHAL_DCACHE_SIZE */
uint32_t addr = start - (start & (XCHAL_DCACHE_SIZE - 1)); uint32_t addr = start - (start & (XCHAL_DCACHE_LINESIZE - 1));
for (; addr < end; addr += XCHAL_DCACHE_SIZE) for (; addr < end; addr += XCHAL_DCACHE_LINESIZE)
{ {
__asm__ __volatile__ ("dhwb %0, 0\n" : : "r"(addr)); __asm__ __volatile__ ("dhwb %0, 0\n" : : "r"(addr));
} }
@ -430,7 +430,7 @@ void up_flush_dcache_all(void)
{ {
uint32_t index; uint32_t index;
for (index = 0; index < XCHAL_ICACHE_SIZE; index += XCHAL_DCACHE_LINESIZE) for (index = 0; index < XCHAL_DCACHE_SIZE; index += XCHAL_DCACHE_LINESIZE)
{ {
__asm__ __volatile__ ("diwbi %0, 0\n" : : "r"(index)); __asm__ __volatile__ ("diwbi %0, 0\n" : : "r"(index));
}; };