Update clock logic
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2576 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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5268348bf2
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8eb54ceab1
@ -89,16 +89,6 @@
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# undef CONFIG_HSMCI_XFRDEBUG
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#endif
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/* Mode dependent settings. These depend on clock devisor settings that must
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* be defined in the board-specific board.h header file: HSMCI_INIT_CLKDIV,
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* HSMCI_MMCXFR_CLKDIV, and HSMCI_SDXFR_CLKDIV.
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*/
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#define HSMCI_CLCKCR_INIT (((SAM3U_MCK_FREQUENCY / ( 400000 * 2)) - 1) | (7 << HSMCI_MR_PWSDIV_SHIFT))
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#define HSMCI_CLKCR_MMCXFR (((SAM3U_MCK_FREQUENCY / (20000000 * 2)) - 1) | (7 << HSMCI_MR_PWSDIV_SHIFT))
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#define HSMCI_CLCKR_SDXFR (((SAM3U_MCK_FREQUENCY / (25000000 * 2)) - 1) | (7 << HSMCI_MR_PWSDIV_SHIFT))
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#define HSMCI_CLCKR_SDWIDEXFR (((SAM3U_MCK_FREQUENCY / (25000000 * 2)) - 1) | (7 << HSMCI_MR_PWSDIV_SHIFT))
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/* Timing */
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#define HSMCI_CMDTIMEOUT (100000)
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@ -277,16 +267,16 @@ struct sam3u_sampleregs_s
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static void sam3u_takesem(struct sam3u_dev_s *priv);
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#define sam3u_givesem(priv) (sem_post(&priv->waitsem))
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static inline void sam3u_setclkcr(uint32_t clkcr);
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static void sam3u_enablewaitints(struct sam3u_dev_s *priv, uint32_t waitmask,
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sdio_eventset_t waitevents);
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static void sam3u_disablewaitints(struct sam3u_dev_s *priv, sdio_eventset_t wkupevents);
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static void sam3u_enablexfrints(struct sam3u_dev_s *priv, uint32_t xfrmask);
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static void sam3u_disablexfrints(struct sam3u_dev_s *priv);
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static inline void sam3u_disable(void);
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static inline void sam3u_enable(void);
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/* DMA Helpers **************************************************************/
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#ifdef CONFIG_HSMCI_XFRDEBUG
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static void sam3u_sampleinit(void);
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static void sam3u_sdiosample(struct sam3u_hsmciregs_s *regs);
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@ -447,42 +437,6 @@ static void sam3u_takesem(struct sam3u_dev_s *priv)
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}
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}
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/****************************************************************************
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* Name: sam3u_setclkcr
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*
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* Description:
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* Modify oft-changed bits in the CLKCR register. Only the following bit-
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* fields are changed:
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*
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* CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, and HWFC_EN
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*
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* Input Parameters:
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* clkcr - A new CLKCR setting for the above mentions bits (other bits
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* are ignored.
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static inline void sam3u_setclkcr(uint32_t clkcr)
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{
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uint32_t regval = getreg32(SAM3U_HSMCI_CLKCR);
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/* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
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regval &= ~(HSMCI_CLKCR_CLKDIV_MASK|HSMCI_CLKCR_PWRSAV|HSMCI_CLKCR_BYPASS|
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HSMCI_CLKCR_WIDBUS_MASK|HSMCI_CLKCR_NEGEDGE|HSMCI_CLKCR_HWFC_EN);
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/* Replace with user provided settings */
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clkcr &= (HSMCI_CLKCR_CLKDIV_MASK|HSMCI_CLKCR_PWRSAV|HSMCI_CLKCR_BYPASS|
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HSMCI_CLKCR_WIDBUS_MASK|HSMCI_CLKCR_NEGEDGE|HSMCI_CLKCR_HWFC_EN);
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regval |= clkcr;
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putreg32(regval, SAM3U_HSMCI_CLKCR);
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fvdbg("CLKCR: %08x\n", getreg32(SAM3U_HSMCI_CLKCR));
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}
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/****************************************************************************
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* Name: sam3u_enablewaitints
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*
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@ -594,6 +548,48 @@ static void sam3u_disablexfrints(struct sam3u_dev_s *priv)
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irqrestore(flags);
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}
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/****************************************************************************
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* Name: sam3u_disable
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*
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* Description:
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* Enable/disable the HSMCI
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*
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****************************************************************************/
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static inline void sam3u_disable(void)
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{
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/* Disable the MCI peripheral clock */
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putreg32((1 << SAM3U_PID_HSMCI), SAM3U_PMC_PCDR);
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/* Disable the MCI */
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putreg32(HSMCI_CR_MCIDIS, SAM3U_HSMCI_CR);
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/* Disable all the interrupts */
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putreg32(0xffffffff, SAM3U_HSMCI_IDR);
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}
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/****************************************************************************
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* Name: sam3u_enable
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*
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* Description:
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* Enable the HSMCI
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*
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****************************************************************************/
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static inline void sam3u_enable(void)
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{
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/* Enable the MCI peripheral clock */
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putreg32((1 << SAM3U_PID_HSMCI), SAM3U_PMC_PCER);
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/* Enable the MCI and the Power Saving */
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putreg32(HSMCI_CR_MCIEN, SAM3U_HSMCI_CR);
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}
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/****************************************************************************
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* DMA Helpers
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****************************************************************************/
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@ -1134,10 +1130,10 @@ static void sam3u_reset(FAR struct sdio_dev_s *dev)
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putreg32(HSMCI_DTOR_DTOCYC_MAX | HSMCI_DTOR_DTOMUL_MAX, SAM3U_HSMCI_DTOR);
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/* Set the Mode Register: 400KHz for MCK = 48MHz (clkdiv = 58) */
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/* Set the Mode Register for ID mode frequency (probably 400KHz) */
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sam3u_clock(dev, CLOCK_IDMODE);
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putreg32(HSMCI_CLCKCR_INIT, SAM3U_HSMCI_MR);
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/* Set the SDCard Register */
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putreg32(HSMCI_SDCR_SDCSEL_SLOTA | HSMCI_SDCR_SDCBUS_4BIT, SAM3U_HSMCI_SDCR);
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@ -1237,40 +1233,57 @@ static void sam3u_widebus(FAR struct sdio_dev_s *dev, bool wide)
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static void sam3u_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
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{
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uint32_t clckr;
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uint32_t enable = 1;
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uint32_t regval;
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bool enable = true;
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/* Fetch the current mode register and mask out the clkdiv (and pwsdiv) */
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regval = getreg32(SAM3U_HSMCI_MR);
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regval &= ~(HSMCI_MR_CLKDIV_MASK | HSMCI_MR_PWSDIV_MASK);
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/* These clock devisor values that must be defined in the board-specific
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* board.h header file: HSMCI_INIT_CLKDIV, HSMCI_MMCXFR_CLKDIV,
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* HSMCI_SDXFR_CLKDIV, and HSMCI_SDWIDEXFR_CLKDIV.
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*/
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switch (rate)
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{
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default:
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case CLOCK_HSMCI_DISABLED: /* Clock is disabled */
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clckr = HSMCI_CLCKCR_INIT;
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enable = 0;
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regval |= HSMCI_INIT_CLKDIV | HSMCI_MR_PWSDIV_MAX;
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enable = false;
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return;
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case CLOCK_IDMODE: /* Initial ID mode clocking (<400KHz) */
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clckr = HSMCI_CLCKCR_INIT;
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regval |= HSMCI_INIT_CLKDIV | HSMCI_MR_PWSDIV_MAX;
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break;
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case CLOCK_MMC_TRANSFER: /* MMC normal operation clocking */
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clckr = HSMCI_CLKCR_MMCXFR;
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regval |= HSMCI_MMCXFR_CLKDIV | HSMCI_MR_PWSDIV_MAX;
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break;
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case CLOCK_SD_TRANSFER_1BIT: /* SD normal operation clocking (narrow 1-bit mode) */
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clckr = HSMCI_CLCKR_SDXFR;
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regval |= HSMCI_SDXFR_CLKDIV | HSMCI_MR_PWSDIV_MAX;
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break;
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case CLOCK_SD_TRANSFER_4BIT: /* SD normal operation clocking (wide 4-bit mode) */
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clckr = HSMCI_CLCKR_SDWIDEXFR;
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regval |= HSMCI_SDWIDEXFR_CLKDIV | HSMCI_MR_PWSDIV_MAX;
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break;
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};
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/* Set the new clock frequency and make sure that the clock is enabled or
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* disabled, whatever the case.
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/* Set the new clock diver and make sure that the clock is enabled or
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* disabled, whichever the case.
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*/
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sam3u_setclkcr(clckr);
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putreg32(enable, HSMCI_CLKCR_CLKEN_BB);
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putreg32(regval, SAM3U_HSMCI_MR);
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if (enable)
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{
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sam3u_enable();
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}
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else
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{
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sam3u_disable();
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}
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}
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/****************************************************************************
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@ -121,6 +121,7 @@
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#define HSMCI_MR_CLKDIV_MASK (0xff << HSMCI_MR_CLKDIV_SHIFT)
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#define HSMCI_MR_PWSDIV_SHIFT (8) /* Bits 8-10: Power Saving Divider */
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#define HSMCI_MR_PWSDIV_MASK (7 << HSMCI_MR_PWSDIV_SHIFT)
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# define HSMCI_MR_PWSDIV_MAX (7 << HSMCI_MR_PWSDIV_SHIFT)
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#define HSMCI_MR_RDPROOF (1 << 11) /* Bit 11: Read Proof Enable */
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#define HSMCI_MR_WRPROOF (1 << 12) /* Bit 12: Write Proof Enable */
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#define HSMCI_MR_FBYTE (1 << 13) /* Bit 13: Force Byte Transfer */
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@ -87,6 +87,28 @@
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#define SAM3U_PLLA_FREQUENCY (96000000)
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#define SAM3U_CPU_FREQUENCY (48000000)
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/* HSMCI clocking
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*
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* Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)
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* divided by (2*(CLKDIV+1)).
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*
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* MCI_SPEED = MCK / (2*(CLKDIV+1))
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* CLKDIV = MCI / MCI_SPEED / 2 - 1
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*/
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/* MCK = 48MHz, CLKDIV = 59, MCI_SPEED = 48MHz / 2 * (59+1) = 400 KHz */
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#define HSMCI_INIT_CLKDIV (59 << HSMCI_MR_CLKDIV_SHIFT)
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/* MCK = 48MHz, CLKDIV = 1, MCI_SPEED = 48MHz / 2 * (1+1) = 12 MHz */
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#define HSMCI_MMCXFR_CLKDIV (3 << HSMCI_MR_CLKDIV_SHIFT)
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/* MCK = 48MHz, CLKDIV = 0, MCI_SPEED = 48MHz / 2 * (0+1) = 24 MHz */
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#define HSMCI_SDXFR_CLKDIV (0 << HSMCI_MR_CLKDIV_SHIFT)
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#define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV
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/* LED definitions ******************************************************************/
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#define LED_STARTED 0 /* LED0=OFF LED1=OFF LED2=OFF */
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