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Bring STM3220G-EVAL board configurations to same level as STM3240G-EVAL

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4779 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2012-05-28 19:48:26 +00:00
parent 1dd72a0277
commit 8eddbd2ebf
4 changed files with 10 additions and 10 deletions
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2
arch/arm/src/stm32/Kconfig
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@ -127,7 +127,7 @@ config STM32_CAN2
config STM32_CCMDATARAM
bool "CMD/DATA RAM"
default n
depends on STM32_STM32F20XX || STM32_STM32F40XX
depends on STM32_STM32F40XX
config STM32_CRYP
bool "CRYP"

2
arch/arm/src/stm32/chip/stm32f20xxx_rcc.h
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@ -311,7 +311,6 @@
#define RCC_AHB1ENR_GPIOIEN (1 << 8) /* Bit 8: IO port I clock enable */
#define RCC_AHB1ENR_CRCEN (1 << 12) /* Bit 12: CRC clock enable */
#define RCC_AHB1ENR_BKPSRAMEN (1 << 18) /* Bit 18: Backup SRAM interface clock enable */
#define RCC_AHB1ENR_CCMDATARAMEN (1 << 20) /* Bit 20: CCM data RAM clock enable */
#define RCC_AHB1ENR_DMA1EN (1 << 21) /* Bit 21: DMA1 clock enable */
#define RCC_AHB1ENR_DMA2EN (1 << 22) /* Bit 22: DMA2 clock enable */
#define RCC_AHB1ENR_ETHMACEN (1 << 25) /* Bit 25: Ethernet MAC clock enable */
@ -392,7 +391,6 @@
#define RCC_AHB1LPENR_SRAM1LPEN (1 << 16) /* Bit 16: SRAM 1 interface clock enable during Sleep mode */
#define RCC_AHB1LPENR_SRAM2LPEN (1 << 17) /* Bit 17: SRAM 2 interface clock enable during Sleep mode */
#define RCC_AHB1LPENR_BKPSRAMLPEN (1 << 18) /* Bit 18: Backup SRAM interface clock enable during Sleep mode */
#define RCC_AHB1LPENR_CCMDATARAMLPEN (1 << 20) /* Bit 20: CCM data RAM clock enable during Sleep mode */
#define RCC_AHB1LPENR_DMA1LPEN (1 << 21) /* Bit 21: DMA1 clock enable during Sleep mode */
#define RCC_AHB1LPENR_DMA2LPEN (1 << 22) /* Bit 22: DMA2 clock enable during Sleep mode */
#define RCC_AHB1LPENR_ETHMACLPEN (1 << 25) /* Bit 25: Ethernet MAC clock enable during Sleep mode */

10
arch/arm/src/stm32/stm32_allocateheap.c
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@ -112,7 +112,7 @@
# error "CONFIG_MM_REGIONS > 1 but I don't know what the other region(s) are"
# endif
/* The STM32 F1 has not CCM SRAM */
/* The STM32 F1 has no CCM SRAM */
# undef CONFIG_STM32_CCMEXCLUDE
# define CONFIG_STM32_CCMEXCLUDE 1
@ -136,6 +136,14 @@
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
/* The STM32 F2 has no CCM SRAM */
# ifdef CONFIG_STM32_STM32F20XX
# undef CONFIG_STM32_CCMEXCLUDE
# define CONFIG_STM32_CCMEXCLUDE 1
# endif
/* Set the end of system SRAM */
# define SRAM1_END 0x20020000

6
arch/arm/src/stm32/stm32f20xxx_rcc.c
View File

@ -167,12 +167,6 @@ static inline void rcc_enableahb1(void)
regval |= RCC_AHB1ENR_BKPSRAMEN;
#endif
#ifdef CONFIG_STM32_CCMDATARAM
/* CCM data RAM clock enable */
regval |= RCC_AHB1ENR_CCMDATARAMEN;
#endif
#ifdef CONFIG_STM32_DMA1
/* DMA 1 clock enable */