Backport the new LPC17xx I2C driver to the LPC11xx in order to get the I2C_TRANSFER method
This commit is contained in:
Gregory Nutt
parent
8a37072e87
commit
8f1b9886a9
@ -90,7 +90,7 @@
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#define LPC11_IRQ_PIO1_0 (28) /* Vector 28: PIO1_0 */
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#define LPC11_IRQ_CCAN (29) /* Vector 29: C_CAN controller for LPC11Cxx */
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#define LPC11_IRQ_SSP1 (30) /* Vector 30: SPI1/SSP1 */
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#define LPC11_IRQ_I2C (31) /* Vector 31: I2C */
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#define LPC11_IRQ_I2C0 (31) /* Vector 31: I2C0 */
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#define LPC11_IRQ_CT16B0 (32) /* Vector 32: Clock/Timer0 16 bits */
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#define LPC11_IRQ_CT16B1 (33) /* Vector 33: Clock/Timer1 16 bits */
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#define LPC11_IRQ_CT32B0 (34) /* Vector 34: Clock/Timer0 32 bits */
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@ -245,17 +245,17 @@ config GPIO_IRQ
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menu "I2C driver options"
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depends on LPC11_I2C0 || LPC11_I2C1 || LPC11_I2C2
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config I2C0_FREQ
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config LPC11_I2C0_FREQUENCY
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int "I2C0 frequency"
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depends on LPC11_I2C0
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default 100000
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config I2C1_FREQ
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config LPC11_I2C1_FREQUENCY
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int "I2C1 frequency"
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depends on LPC11_I2C1
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default 100000
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config I2C2_FREQ
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config LPC11_I2C2_FREQUENCY
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int "I2C2 frequency"
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depends on LPC11_I2C2
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default 100000
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@ -62,8 +62,8 @@
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#define GPIO_CT32B0_MAT2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN1)
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#define GPIO_SPI0_SSEL (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN2)
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#define GPIO_CT16B0_CAP0 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN2)
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#define GPIO_I2C_SCL (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN4)
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#define GPIO_I2C_SDA (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5)
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#define GPIO_I2C0_SCL (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN4)
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#define GPIO_I2C0_SDA (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5)
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#define GPIO_SPI0_SCK_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN6)
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#define GPIO_UART0_CTS (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN7)
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#define GPIO_SPI0_MISO (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8)
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@ -182,7 +182,7 @@
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/* Bits 2-31: Reserved */
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#define SYSCON_PRESETCTRL_SSP0_RST_N (1 << 0) /* SPI0 reset control */
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#define SYSCON_PRESETCTRL_I2C_RST_N (1 << 1) /* I2C reset control */
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#define SYSCON_PRESETCTRL_I2C0_RST_N (1 << 1) /* I2C0 reset control */
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#define SYSCON_PRESETCTRL_SSP1_RST_N (1 << 2) /* SPI1 reset control */
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#define SYSCON_PRESETCTRL_CAN_RST_N (1 << 3) /* C_CAN reset control */
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/* Bits 4-31: Reserved */
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@ -266,7 +266,7 @@
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#define SYSCON_SYSAHBCLKCTRL_RAM (1 << 2) /* Bit 2: Enables clock for RAM */
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#define SYSCON_SYSAHBCLKCTRL_FLASHREG (1 << 3) /* Bit 3: Enables clock for flash register interface */
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#define SYSCON_SYSAHBCLKCTRL_FLASHARRAY (1 << 4) /* Bit 4: Enables clock for flash array access */
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#define SYSCON_SYSAHBCLKCTRL_I2C (1 << 5) /* Bit 5: Enables clock for I2C */
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#define SYSCON_SYSAHBCLKCTRL_I2C0 (1 << 5) /* Bit 5: Enables clock for I2C0 */
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#define SYSCON_SYSAHBCLKCTRL_GPIO (1 << 6) /* Bit 6: Enables clock for GPIO */
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#define SYSCON_SYSAHBCLKCTRL_CT16B0 (1 << 7) /* Bit 7: Enables clock for 16-bit counter/timer 0 */
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#define SYSCON_SYSAHBCLKCTRL_CT16B1 (1 << 8) /* Bit 8: Enables clock for 16-bit counter/timer 1 */
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@ -33,8 +33,8 @@
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_GPIO_H
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#define __ARCH_ARM_SRC_LPC17XX_LPC17_GPIO_H
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#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_GPIO_H
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#define __ARCH_ARM_SRC_LPC11XX_LPC11_GPIO_H
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/************************************************************************************
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* Included Files
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@ -191,4 +191,4 @@ int lpc11_dumpgpio(lpc11_pinset_t pinset, const char *msg);
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_GPIO_H */
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#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_GPIO_H */
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@ -151,7 +151,7 @@ int lpc11_dumpgpio(lpc11_pinset_t pinset, const char *msg)
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pinsel = lpc11_pinsel(port, pin);
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pinmode = lpc11_pinmode(port, pin);
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#elif defined(LPC178x)
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iocon = LPC17_IOCON_P(port, pin);
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iocon = LPC11_IOCON_P(port, pin);
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#endif /* LPC176x */
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/* The following requires exclusive access to the GPIO registers */
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@ -171,18 +171,18 @@ int lpc11_dumpgpio(lpc11_pinset_t pinset, const char *msg)
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base = g_fiobase[port];
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lldbg(" FIODIR[%08x]: %08x FIOMASK[%08x]: %08x FIOPIN[%08x]: %08x\n",
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base+LPC17_FIO_DIR_OFFSET, getreg32(base+LPC17_FIO_DIR_OFFSET),
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base+LPC17_FIO_MASK_OFFSET, getreg32(base+LPC17_FIO_MASK_OFFSET),
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base+LPC17_FIO_PIN_OFFSET, getreg32(base+LPC17_FIO_PIN_OFFSET));
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base+LPC11_FIO_DIR_OFFSET, getreg32(base+LPC11_FIO_DIR_OFFSET),
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base+LPC11_FIO_MASK_OFFSET, getreg32(base+LPC11_FIO_MASK_OFFSET),
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base+LPC11_FIO_PIN_OFFSET, getreg32(base+LPC11_FIO_PIN_OFFSET));
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base = g_intbase[port];
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lldbg(" IOINTSTATUS[%08x]: %08x INTSTATR[%08x]: %08x INSTATF[%08x]: %08x\n",
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LPC17_GPIOINT_IOINTSTATUS, getreg32(LPC17_GPIOINT_IOINTSTATUS),
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base+LPC17_GPIOINT_INTSTATR_OFFSET, getreg32(base+LPC17_GPIOINT_INTSTATR_OFFSET),
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base+LPC17_GPIOINT_INTSTATF_OFFSET, getreg32(base+LPC17_GPIOINT_INTSTATF_OFFSET));
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LPC11_GPIOINT_IOINTSTATUS, getreg32(LPC11_GPIOINT_IOINTSTATUS),
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base+LPC11_GPIOINT_INTSTATR_OFFSET, getreg32(base+LPC11_GPIOINT_INTSTATR_OFFSET),
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base+LPC11_GPIOINT_INTSTATF_OFFSET, getreg32(base+LPC11_GPIOINT_INTSTATF_OFFSET));
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lldbg(" INTENR[%08x]: %08x INTENF[%08x]: %08x\n",
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base+LPC17_GPIOINT_INTENR_OFFSET, getreg32(base+LPC17_GPIOINT_INTENR_OFFSET),
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base+LPC17_GPIOINT_INTENF_OFFSET, getreg32(base+LPC17_GPIOINT_INTENF_OFFSET));
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base+LPC11_GPIOINT_INTENR_OFFSET, getreg32(base+LPC11_GPIOINT_INTENR_OFFSET),
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base+LPC11_GPIOINT_INTENF_OFFSET, getreg32(base+LPC11_GPIOINT_INTENF_OFFSET));
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irqrestore(flags);
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return OK;
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}
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@ -125,7 +125,7 @@ static void lpc11_setintedge(uint32_t intbase, unsigned int pin,
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/* Set/clear the rising edge enable bit */
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regval = getreg32(intbase + LPC17_GPIOINT_INTENR_OFFSET);
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regval = getreg32(intbase + LPC11_GPIOINT_INTENR_OFFSET);
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if ((edges & 2) != 0)
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{
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regval |= GPIOINT(pin);
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@ -135,11 +135,11 @@ static void lpc11_setintedge(uint32_t intbase, unsigned int pin,
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regval &= ~GPIOINT(pin);
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}
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putreg32(regval, intbase + LPC17_GPIOINT_INTENR_OFFSET);
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putreg32(regval, intbase + LPC11_GPIOINT_INTENR_OFFSET);
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/* Set/clear the falling edge enable bit */
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regval = getreg32(intbase + LPC17_GPIOINT_INTENF_OFFSET);
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regval = getreg32(intbase + LPC11_GPIOINT_INTENF_OFFSET);
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if ((edges & 1) != 0)
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{
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regval |= GPIOINT(pin);
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@ -149,7 +149,7 @@ static void lpc11_setintedge(uint32_t intbase, unsigned int pin,
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regval &= ~GPIOINT(pin);
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}
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putreg32(regval, intbase + LPC17_GPIOINT_INTENF_OFFSET);
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putreg32(regval, intbase + LPC11_GPIOINT_INTENF_OFFSET);
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irqrestore(flags);
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}
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@ -168,8 +168,8 @@ static int lpc11_irq2port(int irq)
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* LPC178x: 16 interrupts p0.0-p0.15
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*/
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if (irq >= LPC17_VALID_FIRST0L &&
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irq < (LPC17_VALID_FIRST0L + LPC17_VALID_NIRQS0L))
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if (irq >= LPC11_VALID_FIRST0L &&
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irq < (LPC11_VALID_FIRST0L + LPC11_VALID_NIRQS0L))
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{
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return 0;
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}
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@ -179,8 +179,8 @@ static int lpc11_irq2port(int irq)
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* LPC178x: 16 interrupts p0.16-p0.31
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*/
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else if (irq >= LPC17_VALID_FIRST0H &&
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irq < (LPC17_VALID_FIRST0H + LPC17_VALID_NIRQS0H))
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else if (irq >= LPC11_VALID_FIRST0H &&
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irq < (LPC11_VALID_FIRST0H + LPC11_VALID_NIRQS0H))
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{
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return 0;
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}
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@ -190,8 +190,8 @@ static int lpc11_irq2port(int irq)
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* LPC17x: 14 interrupts p2.0-p2.13
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*/
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else if (irq >= LPC17_VALID_FIRST2 &&
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irq < (LPC17_VALID_FIRST2 + LPC17_VALID_NIRQS2))
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else if (irq >= LPC11_VALID_FIRST2 &&
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irq < (LPC11_VALID_FIRST2 + LPC11_VALID_NIRQS2))
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{
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return 2;
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}
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@ -201,8 +201,8 @@ static int lpc11_irq2port(int irq)
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* LPC18x: 16 interrupts p2.0-p2.15
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*/
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else if (irq >= LPC17_VALID_FIRST2L &&
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irq < (LPC17_VALID_FIRST2L + LPC17_VALID_NIRQS2L))
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else if (irq >= LPC11_VALID_FIRST2L &&
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irq < (LPC11_VALID_FIRST2L + LPC11_VALID_NIRQS2L))
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{
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return 2;
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}
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@ -211,8 +211,8 @@ static int lpc11_irq2port(int irq)
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* LPC178x: 16 interrupts p2.16-p2.31
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*/
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else if (irq >= LPC17_VALID_FIRST2H &&
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irq < (LPC17_VALID_FIRST2H + LPC17_VALID_NIRQS2H))
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else if (irq >= LPC11_VALID_FIRST2H &&
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irq < (LPC11_VALID_FIRST2H + LPC11_VALID_NIRQS2H))
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{
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return 2;
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}
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@ -237,48 +237,48 @@ static int lpc11_irq2pin(int irq)
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* LPC18x: 16 interrupts p0.0-p0.15
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*
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* See arch/arm/include/lpc11xx/irq.h:
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* LPC17_VALID_SHIFT0L 0 - Bit 0 is thre first bit in the group of
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* LPC11_VALID_SHIFT0L 0 - Bit 0 is thre first bit in the group of
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* 12/16 interrupts
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* LPC17_VALID_FIRST0L irq - IRQ number associated with p0.0
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* LPC17_VALID_NIRQS0L 12/16 - Number of interrupt bits in the group
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* LPC11_VALID_FIRST0L irq - IRQ number associated with p0.0
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* LPC11_VALID_NIRQS0L 12/16 - Number of interrupt bits in the group
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*/
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if (irq >= LPC17_VALID_FIRST0L &&
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irq < (LPC17_VALID_FIRST0L + LPC17_VALID_NIRQS0L))
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if (irq >= LPC11_VALID_FIRST0L &&
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irq < (LPC11_VALID_FIRST0L + LPC11_VALID_NIRQS0L))
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{
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return irq - LPC17_VALID_FIRST0L + LPC17_VALID_SHIFT0L;
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return irq - LPC11_VALID_FIRST0L + LPC11_VALID_SHIFT0L;
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}
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/* Set 2:
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* LPC176x: 16 interrupts p0.15-p0.30
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* LPC178x: 16 interrupts p0.16-p0.31
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*
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* LPC17_VALID_SHIFT0H 15/16 - Bit number of the first bit in a group
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* LPC11_VALID_SHIFT0H 15/16 - Bit number of the first bit in a group
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* of 16 interrupts
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* LPC17_VALID_FIRST0L irq - IRQ number associated with p0.15/16
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* LPC17_VALID_NIRQS0L 16 - 16 interrupt bits in the group
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* LPC11_VALID_FIRST0L irq - IRQ number associated with p0.15/16
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* LPC11_VALID_NIRQS0L 16 - 16 interrupt bits in the group
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*/
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else if (irq >= LPC17_VALID_FIRST0H &&
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irq < (LPC17_VALID_FIRST0H + LPC17_VALID_NIRQS0H))
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else if (irq >= LPC11_VALID_FIRST0H &&
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irq < (LPC11_VALID_FIRST0H + LPC11_VALID_NIRQS0H))
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{
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return irq - LPC17_VALID_FIRST0H + LPC17_VALID_SHIFT0H;
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return irq - LPC11_VALID_FIRST0H + LPC11_VALID_SHIFT0H;
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}
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#if defined(LPC176x)
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/* Set 3:
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* LPC17x: 14 interrupts p2.0-p2.13
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*
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* LPC17_VALID_SHIFT2 0 - Bit 0 is the first bit in a group of 14
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* LPC11_VALID_SHIFT2 0 - Bit 0 is the first bit in a group of 14
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* interrupts
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* LPC17_VALID_FIRST2 irq - IRQ number associated with p2.0
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* LPC17_VALID_NIRQS2 14 - 14 interrupt bits in the group
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* LPC11_VALID_FIRST2 irq - IRQ number associated with p2.0
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* LPC11_VALID_NIRQS2 14 - 14 interrupt bits in the group
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*/
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else if (irq >= LPC17_VALID_FIRST2 &&
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irq < (LPC17_VALID_FIRST2 + LPC17_VALID_NIRQS2))
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else if (irq >= LPC11_VALID_FIRST2 &&
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irq < (LPC11_VALID_FIRST2 + LPC11_VALID_NIRQS2))
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{
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return irq - LPC17_VALID_FIRST2 + LPC17_VALID_SHIFT2;
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return irq - LPC11_VALID_FIRST2 + LPC11_VALID_SHIFT2;
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}
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#elif defined(LPC178x)
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@ -286,31 +286,31 @@ static int lpc11_irq2pin(int irq)
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/* Set 3:
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* LPC18x: 16 interrupts p2.0-p2.15
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*
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* LPC17_VALID_SHIFT2L 0 - Bit 0 is the first bit in a group of 16
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* LPC11_VALID_SHIFT2L 0 - Bit 0 is the first bit in a group of 16
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* interrupts
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* LPC17_VALID_FIRST2L irq - IRQ number associated with p2.0
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* LPC17_VALID_NIRQS2L 16 - 16 interrupt bits in the group
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* LPC11_VALID_FIRST2L irq - IRQ number associated with p2.0
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* LPC11_VALID_NIRQS2L 16 - 16 interrupt bits in the group
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*/
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else if (irq >= LPC17_VALID_FIRST2L &&
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irq < (LPC17_VALID_FIRST2L + LPC17_VALID_NIRQS2L))
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else if (irq >= LPC11_VALID_FIRST2L &&
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irq < (LPC11_VALID_FIRST2L + LPC11_VALID_NIRQS2L))
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{
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return irq - LPC17_VALID_FIRST2L + LPC17_VALID_SHIFT2L;
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return irq - LPC11_VALID_FIRST2L + LPC11_VALID_SHIFT2L;
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}
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/* Set 3:
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* LPC18x: 16 interrupts p2.16-p2.31
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*
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* LPC17_VALID_SHIFT2L 16 - Bit 16 is the first bit in a group of 16
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* LPC11_VALID_SHIFT2L 16 - Bit 16 is the first bit in a group of 16
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* interrupts
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* LPC17_VALID_FIRST2L irq - IRQ number associated with p2.0
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* LPC17_VALID_NIRQS2L 16 - 16 interrupt bits in the group
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* LPC11_VALID_FIRST2L irq - IRQ number associated with p2.0
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* LPC11_VALID_NIRQS2L 16 - 16 interrupt bits in the group
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*/
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else if (irq >= LPC17_VALID_FIRST2H &&
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irq < (LPC17_VALID_FIRST2H + LPC17_VALID_NIRQS2H))
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else if (irq >= LPC11_VALID_FIRST2H &&
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irq < (LPC11_VALID_FIRST2H + LPC11_VALID_NIRQS2H))
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{
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return irq - LPC17_VALID_FIRST2H + LPC17_VALID_SHIFT2H;
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return irq - LPC11_VALID_FIRST2H + LPC11_VALID_SHIFT2H;
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}
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#endif
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@ -339,11 +339,11 @@ static void lpc11_gpiodemux(uint32_t intbase, uint32_t intmask,
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* interrupts that are enabled.
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*/
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intstatr = getreg32(intbase + LPC17_GPIOINT_INTSTATR_OFFSET);
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intstatr &= getreg32(intbase + LPC17_GPIOINT_INTENR_OFFSET);
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intstatr = getreg32(intbase + LPC11_GPIOINT_INTSTATR_OFFSET);
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intstatr &= getreg32(intbase + LPC11_GPIOINT_INTENR_OFFSET);
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intstatf = getreg32(intbase + LPC17_GPIOINT_INTSTATF_OFFSET);
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intstatf &= getreg32(intbase + LPC17_GPIOINT_INTENF_OFFSET);
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intstatf = getreg32(intbase + LPC11_GPIOINT_INTSTATF_OFFSET);
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intstatf &= getreg32(intbase + LPC11_GPIOINT_INTENF_OFFSET);
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/* And get the OR of the enabled interrupt sources. We do not make any
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* distinction between rising and falling edges (but the hardware does support
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@ -372,7 +372,7 @@ static void lpc11_gpiodemux(uint32_t intbase, uint32_t intmask,
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{
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/* Clear the interrupt status */
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putreg32(bit, intbase + LPC17_GPIOINT_INTCLR_OFFSET);
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putreg32(bit, intbase + LPC11_GPIOINT_INTCLR_OFFSET);
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/* And dispatch the interrupt */
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@ -406,14 +406,14 @@ static int lpc11_gpiointerrupt(int irq, void *context)
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{
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/* Get the GPIO interrupt status */
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|
||||
uint32_t intstatus = getreg32(LPC17_GPIOINT_IOINTSTATUS);
|
||||
uint32_t intstatus = getreg32(LPC11_GPIOINT_IOINTSTATUS);
|
||||
|
||||
/* Check for an interrupt on GPIO0 */
|
||||
|
||||
if ((intstatus & GPIOINT_IOINTSTATUS_P0INT) != 0)
|
||||
{
|
||||
lpc11_gpiodemux(LPC17_GPIOINT0_BASE, LPC17_VALID_GPIOINT0,
|
||||
LPC17_VALID_FIRST0L, context);
|
||||
lpc11_gpiodemux(LPC11_GPIOINT0_BASE, LPC11_VALID_GPIOINT0,
|
||||
LPC11_VALID_FIRST0L, context);
|
||||
}
|
||||
|
||||
#if defined(LPC176x)
|
||||
@ -421,8 +421,8 @@ static int lpc11_gpiointerrupt(int irq, void *context)
|
||||
|
||||
if ((intstatus & GPIOINT_IOINTSTATUS_P2INT) != 0)
|
||||
{
|
||||
lpc11_gpiodemux(LPC17_GPIOINT2_BASE, LPC17_VALID_GPIOINT2,
|
||||
LPC17_VALID_FIRST2, context);
|
||||
lpc11_gpiodemux(LPC11_GPIOINT2_BASE, LPC11_VALID_GPIOINT2,
|
||||
LPC11_VALID_FIRST2, context);
|
||||
}
|
||||
|
||||
#elif defined(LPC178x)
|
||||
@ -430,8 +430,8 @@ static int lpc11_gpiointerrupt(int irq, void *context)
|
||||
|
||||
if ((intstatus & GPIOINT_IOINTSTATUS_P2INT) != 0)
|
||||
{
|
||||
lpc11_gpiodemux(LPC17_GPIOINT2_BASE, LPC17_VALID_GPIOINT2,
|
||||
LPC17_VALID_FIRST2L, context);
|
||||
lpc11_gpiodemux(LPC11_GPIOINT2_BASE, LPC11_VALID_GPIOINT2,
|
||||
LPC11_VALID_FIRST2L, context);
|
||||
}
|
||||
|
||||
#endif
|
||||
@ -456,10 +456,10 @@ void lpc11_gpioirqinitialize(void)
|
||||
{
|
||||
/* Disable all GPIO interrupts */
|
||||
|
||||
putreg32(0, LPC17_GPIOINT0_INTENR);
|
||||
putreg32(0, LPC17_GPIOINT0_INTENF);
|
||||
putreg32(0, LPC17_GPIOINT2_INTENR);
|
||||
putreg32(0, LPC17_GPIOINT2_INTENF);
|
||||
putreg32(0, LPC11_GPIOINT0_INTENR);
|
||||
putreg32(0, LPC11_GPIOINT0_INTENF);
|
||||
putreg32(0, LPC11_GPIOINT2_INTENR);
|
||||
putreg32(0, LPC11_GPIOINT2_INTENF);
|
||||
|
||||
/* Attach and enable the GPIO IRQ. */
|
||||
|
||||
@ -468,16 +468,16 @@ void lpc11_gpioirqinitialize(void)
|
||||
* position in the NVIC with External Interrupt 3
|
||||
*/
|
||||
|
||||
(void)irq_attach(LPC17_IRQ_EINT3, lpc11_gpiointerrupt);
|
||||
up_enable_irq(LPC17_IRQ_EINT3);
|
||||
(void)irq_attach(LPC11_IRQ_EINT3, lpc11_gpiointerrupt);
|
||||
up_enable_irq(LPC11_IRQ_EINT3);
|
||||
|
||||
#elif defined(LPC178x)
|
||||
/* the LPC178x family has a single, dedicated interrupt for GPIO0 and
|
||||
* GPIO2.
|
||||
*/
|
||||
|
||||
(void)irq_attach(LPC17_IRQ_GPIO, lpc11_gpiointerrupt);
|
||||
up_enable_irq(LPC17_IRQ_GPIO);
|
||||
(void)irq_attach(LPC11_IRQ_GPIO, lpc11_gpiointerrupt);
|
||||
up_enable_irq(LPC11_IRQ_GPIO);
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -1,15 +1,16 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/lpc11xx/lpc11_i2c.c
|
||||
*
|
||||
* Copyright (C) 2012, 2014-2016 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2011 Li Zhuoyi. All rights reserved.
|
||||
* Author: Li Zhuoyi <lzyy.cn@gmail.com>
|
||||
* History: 0.1 2011-08-20 initial version
|
||||
* Author: Li Zhuoyi <lzyy.cn@gmail.com> (Original author)
|
||||
* Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Derived from arch/arm/src/lpc31xx/lpc31_i2c.c
|
||||
*
|
||||
* Author: David Hewson
|
||||
*
|
||||
* Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2010-2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -62,6 +63,7 @@
|
||||
#include <arch/irq.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "up_arch.h"
|
||||
#include "up_internal.h"
|
||||
|
||||
@ -81,19 +83,20 @@
|
||||
# define GPIO_I2C1_SDA GPIO_I2C1_SDA_1
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_I2C0_FREQ
|
||||
# define CONFIG_I2C0_FREQ 100000
|
||||
#ifndef CONFIG_LPC11_I2C0_FREQUENCY
|
||||
# define CONFIG_LPC11_I2C0_FREQUENCY 100000
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_I2C1_FREQ
|
||||
# define CONFIG_I2C1_FREQ 100000
|
||||
#ifndef CONFIG_LPC11_I2C1_FREQUENCY
|
||||
# define CONFIG_LPC11_I2C1_FREQUENCY 100000
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_I2C2_FREQ
|
||||
# define CONFIG_I2C2_FREQ 100000
|
||||
#ifndef CONFIG_LPC11_I2C2_FREQUENCY
|
||||
# define CONFIG_LPC11_I2C2_FREQUENCY 100000
|
||||
#endif
|
||||
|
||||
#define I2C_TIMEOUT ((20 * CLK_TCK) / 1000) /* 20 mS */
|
||||
#define I2C_TIMEOUT (20 * 1000/CONFIG_USEC_PER_TICK) /* 20 mS */
|
||||
#define LPC11_I2C1_FREQUENCY 400000
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
@ -101,51 +104,70 @@
|
||||
|
||||
struct lpc11_i2cdev_s
|
||||
{
|
||||
struct i2c_master_s dev; /* Generic I2C device */
|
||||
struct i2c_msg_s msg; /* a single message for legacy read/write */
|
||||
unsigned int base; /* Base address of registers */
|
||||
uint16_t irqid; /* IRQ for this device */
|
||||
struct i2c_master_s dev; /* Generic I2C device */
|
||||
struct i2c_msg_s msg; /* a single message for legacy read/write */
|
||||
unsigned int base; /* Base address of registers */
|
||||
uint16_t irqid; /* IRQ for this device */
|
||||
|
||||
sem_t mutex; /* Only one thread can access at a time */
|
||||
sem_t wait; /* Place to wait for state machine completion */
|
||||
volatile uint8_t state; /* State of state machine */
|
||||
WDOG_ID timeout; /* watchdog to timeout when bus hung */
|
||||
sem_t mutex; /* Only one thread can access at a time */
|
||||
sem_t wait; /* Place to wait for state machine completion */
|
||||
volatile uint8_t state; /* State of state machine */
|
||||
WDOG_ID timeout; /* watchdog to timeout when bus hung */
|
||||
|
||||
uint16_t wrcnt; /* number of bytes sent to tx fifo */
|
||||
uint16_t rdcnt; /* number of bytes read from rx fifo */
|
||||
struct i2c_msg_s *msgs; /* remaining transfers - first one is in progress */
|
||||
unsigned int nmsg; /* number of transfer remaining */
|
||||
|
||||
uint16_t wrcnt; /* number of bytes sent to tx fifo */
|
||||
uint16_t rdcnt; /* number of bytes read from rx fifo */
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Private Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
static int i2c_start(struct lpc11_i2cdev_s *priv);
|
||||
static void i2c_stop(struct lpc11_i2cdev_s *priv);
|
||||
static int i2c_interrupt(int irq, FAR void *context);
|
||||
static void i2c_timeout(int argc, uint32_t arg, ...);
|
||||
static int lpc11_i2c_start(struct lpc11_i2cdev_s *priv);
|
||||
static void lpc11_i2c_stop(struct lpc11_i2cdev_s *priv);
|
||||
static int lpc11_i2c_interrupt(int irq, FAR void *context);
|
||||
static void lpc11_i2c_timeout(int argc, uint32_t arg, ...);
|
||||
|
||||
/* I2C device operations */
|
||||
|
||||
static uint32_t i2c_setfrequency(FAR struct i2c_master_s *dev, uint32_t frequency);
|
||||
static int i2c_setaddress(FAR struct i2c_master_s *dev, int addr, int nbits);
|
||||
static int i2c_write(FAR struct i2c_master_s *dev, const uint8_t *buffer, int buflen);
|
||||
static int i2c_read(FAR struct i2c_master_s *dev, uint8_t *buffer, int buflen);
|
||||
static int i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs, int count);
|
||||
static uint32_t lpc11_i2c_setfrequency(FAR struct i2c_master_s *dev,
|
||||
uint32_t frequency);
|
||||
static int lpc11_i2c_setaddress(FAR struct i2c_master_s *dev, int addr,
|
||||
int nbits);
|
||||
static int lpc11_i2c_write(FAR struct i2c_master_s *dev,
|
||||
const uint8_t *buffer, int buflen);
|
||||
static int lpc11_i2c_read(FAR struct i2c_master_s *dev, uint8_t *buffer,
|
||||
int buflen);
|
||||
#ifdef CONFIG_I2C_TRANSFER
|
||||
static int lpc11_i2c_transfer(FAR struct i2c_master_s *dev,
|
||||
FAR struct i2c_msg_s *msgs, int count);
|
||||
#endif
|
||||
static void lpc11_stopnext(struct lpc11_i2cdev_s *priv);
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
static struct lpc11_i2cdev_s i2cdevices[3];
|
||||
#ifdef CONFIG_LPC11_I2C0
|
||||
static struct lpc11_i2cdev_s g_i2c0dev;
|
||||
#endif
|
||||
#ifdef CONFIG_LPC11_I2C1
|
||||
static struct lpc11_i2cdev_s g_i2c1dev;
|
||||
#endif
|
||||
#ifdef CONFIG_LPC11_I2C2
|
||||
static struct lpc11_i2cdev_s g_i2c2dev;
|
||||
#endif
|
||||
|
||||
struct i2c_ops_s lpc11_i2c_ops =
|
||||
{
|
||||
.setfrequency = i2c_setfrequency,
|
||||
.setaddress = i2c_setaddress,
|
||||
.write = i2c_write,
|
||||
.read = i2c_read,
|
||||
.setfrequency = lpc11_i2c_setfrequency,
|
||||
.setaddress = lpc11_i2c_setaddress,
|
||||
.write = lpc11_i2c_write,
|
||||
.read = lpc11_i2c_read,
|
||||
#ifdef CONFIG_I2C_TRANSFER
|
||||
.transfer = i2c_transfer
|
||||
.transfer = lpc11_i2c_transfer
|
||||
#endif
|
||||
};
|
||||
|
||||
@ -153,11 +175,12 @@ struct i2c_ops_s lpc11_i2c_ops =
|
||||
* Name: lpc11_i2c_setfrequency
|
||||
*
|
||||
* Description:
|
||||
* Set the frequency for the next transfer
|
||||
* Set the frequence for the next transfer
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static uint32_t i2c_setfrequency(FAR struct i2c_master_s *dev, uint32_t frequency)
|
||||
static uint32_t lpc11_i2c_setfrequency(FAR struct i2c_master_s *dev,
|
||||
uint32_t frequency)
|
||||
{
|
||||
struct lpc11_i2cdev_s *priv = (struct lpc11_i2cdev_s *) dev;
|
||||
|
||||
@ -165,18 +188,18 @@ static uint32_t i2c_setfrequency(FAR struct i2c_master_s *dev, uint32_t frequenc
|
||||
{
|
||||
/* Asymetric per 400Khz I2C spec */
|
||||
|
||||
putreg32(LPC11_CCLK / (83 + 47) * 47 / frequency,
|
||||
putreg32(LPC11_MCLK / (83 + 47) * 47 / frequency,
|
||||
priv->base + LPC11_I2C_SCLH_OFFSET);
|
||||
putreg32(LPC11_CCLK / (83 + 47) * 83 / frequency,
|
||||
putreg32(LPC11_MCLK / (83 + 47) * 83 / frequency,
|
||||
priv->base + LPC11_I2C_SCLL_OFFSET);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* 50/50 mark space ratio */
|
||||
|
||||
putreg32(LPC11_CCLK / 100 * 50 / frequency,
|
||||
putreg32(LPC11_MCLK / 100 * 50 / frequency,
|
||||
priv->base + LPC11_I2C_SCLH_OFFSET);
|
||||
putreg32(LPC11_CCLK / 100 * 50 / frequency,
|
||||
putreg32(LPC11_MCLK / 100 * 50 / frequency,
|
||||
priv->base + LPC11_I2C_SCLL_OFFSET);
|
||||
}
|
||||
|
||||
@ -193,15 +216,15 @@ static uint32_t i2c_setfrequency(FAR struct i2c_master_s *dev, uint32_t frequenc
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int i2c_setaddress(FAR struct i2c_master_s *dev, int addr, int nbits)
|
||||
static int lpc11_i2c_setaddress(FAR struct i2c_master_s *dev, int addr,
|
||||
int nbits)
|
||||
{
|
||||
struct lpc11_i2cdev_s *priv = (struct lpc11_i2cdev_s *) dev;
|
||||
struct lpc11_i2cdev_s *priv = (struct lpc11_i2cdev_s *)dev;
|
||||
|
||||
DEBUGASSERT(dev != NULL);
|
||||
DEBUGASSERT(nbits == 7);
|
||||
|
||||
priv->msg.addr = addr << 1;
|
||||
priv->msg.flags = 0 ;
|
||||
priv->msg.addr = addr;
|
||||
|
||||
return OK;
|
||||
}
|
||||
@ -215,23 +238,29 @@ static int i2c_setaddress(FAR struct i2c_master_s *dev, int addr, int nbits)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int i2c_write(FAR struct i2c_master_s *dev, const uint8_t *buffer,
|
||||
int buflen)
|
||||
static int lpc11_i2c_write(FAR struct i2c_master_s *dev, const uint8_t *buffer,
|
||||
int buflen)
|
||||
{
|
||||
struct lpc11_i2cdev_s *priv = (struct lpc11_i2cdev_s *) dev;
|
||||
int ret;
|
||||
struct lpc11_i2cdev_s *priv = (struct lpc11_i2cdev_s *)dev;
|
||||
int ret = 0;
|
||||
|
||||
DEBUGASSERT(dev != NULL);
|
||||
|
||||
priv->wrcnt = 0;
|
||||
priv->rdcnt = 0;
|
||||
priv->msg.addr &= ~0x01;
|
||||
priv->msg.flags = 0;
|
||||
priv->msg.buffer = (uint8_t *)buffer;
|
||||
priv->msg.length = buflen;
|
||||
|
||||
ret = i2c_start(priv);
|
||||
priv->nmsg = 1;
|
||||
priv->msgs = &(priv->msg);
|
||||
|
||||
return ret > 0 ? OK : -ETIMEDOUT;
|
||||
if (buflen > 0)
|
||||
{
|
||||
ret = lpc11_i2c_start(priv);
|
||||
}
|
||||
|
||||
return (ret == 0 ? 0 : -ETIMEDOUT);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -243,87 +272,91 @@ static int i2c_write(FAR struct i2c_master_s *dev, const uint8_t *buffer,
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int i2c_read(FAR struct i2c_master_s *dev, uint8_t *buffer, int buflen)
|
||||
static int lpc11_i2c_read(FAR struct i2c_master_s *dev, uint8_t *buffer,
|
||||
int buflen)
|
||||
{
|
||||
struct lpc11_i2cdev_s *priv = (struct lpc11_i2cdev_s *) dev;
|
||||
int ret;
|
||||
struct lpc11_i2cdev_s *priv = (struct lpc11_i2cdev_s *)dev;
|
||||
int ret = 0;
|
||||
|
||||
DEBUGASSERT(dev != NULL);
|
||||
|
||||
priv->wrcnt = 0;
|
||||
priv->rdcnt = 0;
|
||||
priv->msg.addr |= 0x01;
|
||||
priv->msg.flags = I2C_M_READ;
|
||||
priv->msg.buffer = buffer;
|
||||
priv->msg.length = buflen;
|
||||
|
||||
ret = i2c_start(priv);
|
||||
priv->nmsg = 1;
|
||||
priv->msgs = &(priv->msg);
|
||||
|
||||
return ret > 0 ? OK : -ETIMEDOUT;
|
||||
if (buflen > 0)
|
||||
{
|
||||
ret = lpc11_i2c_start(priv);
|
||||
}
|
||||
|
||||
return (ret == 0 ? 0 : -ETIMEDOUT);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: i2c_start
|
||||
* Name: lpc11_i2c_start
|
||||
*
|
||||
* Description:
|
||||
* Perform a I2C transfer start
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int i2c_start(struct lpc11_i2cdev_s *priv)
|
||||
static int lpc11_i2c_start(struct lpc11_i2cdev_s *priv)
|
||||
{
|
||||
int ret = -1;
|
||||
|
||||
sem_wait(&priv->mutex);
|
||||
|
||||
putreg32(I2C_CONCLR_STAC | I2C_CONCLR_SIC, priv->base + LPC11_I2C_CONCLR_OFFSET);
|
||||
putreg32(I2C_CONCLR_STAC | I2C_CONCLR_SIC,
|
||||
priv->base + LPC11_I2C_CONCLR_OFFSET);
|
||||
putreg32(I2C_CONSET_STA, priv->base + LPC11_I2C_CONSET_OFFSET);
|
||||
|
||||
wd_start(priv->timeout, I2C_TIMEOUT, i2c_timeout, 1, (uint32_t)priv);
|
||||
wd_start(priv->timeout, I2C_TIMEOUT, lpc11_i2c_timeout, 1, (uint32_t)priv);
|
||||
sem_wait(&priv->wait);
|
||||
wd_cancel(priv->timeout);
|
||||
sem_post(&priv->mutex);
|
||||
|
||||
if (priv-> state == 0x18 || priv->state == 0x28)
|
||||
{
|
||||
ret = priv->wrcnt;
|
||||
}
|
||||
else if (priv-> state == 0x50 || priv->state == 0x58)
|
||||
{
|
||||
ret = priv->rdcnt;
|
||||
}
|
||||
wd_cancel(priv->timeout);
|
||||
|
||||
ret = priv->nmsg;
|
||||
|
||||
sem_post(&priv->mutex);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: i2c_stop
|
||||
* Name: lpc11_i2c_stop
|
||||
*
|
||||
* Description:
|
||||
* Perform a I2C transfer stop
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void i2c_stop(struct lpc11_i2cdev_s *priv)
|
||||
static void lpc11_i2c_stop(struct lpc11_i2cdev_s *priv)
|
||||
{
|
||||
if (priv->state != 0x38)
|
||||
{
|
||||
putreg32(I2C_CONSET_STO | I2C_CONSET_AA, priv->base + LPC11_I2C_CONSET_OFFSET);
|
||||
putreg32(I2C_CONSET_STO | I2C_CONSET_AA,
|
||||
priv->base + LPC11_I2C_CONSET_OFFSET);
|
||||
}
|
||||
|
||||
sem_post(&priv->wait);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: i2c_timeout
|
||||
* Name: lpc11_i2c_timeout
|
||||
*
|
||||
* Description:
|
||||
* Watchdog timer for timeout of I2C operation
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void i2c_timeout(int argc, uint32_t arg, ...)
|
||||
static void lpc11_i2c_timeout(int argc, uint32_t arg, ...)
|
||||
{
|
||||
struct lpc11_i2cdev_s *priv = (struct lpc11_i2cdev_s *) arg;
|
||||
struct lpc11_i2cdev_s *priv = (struct lpc11_i2cdev_s *)arg;
|
||||
|
||||
irqstate_t flags = irqsave();
|
||||
priv->state = 0xff;
|
||||
@ -332,36 +365,88 @@ static void i2c_timeout(int argc, uint32_t arg, ...)
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: i2c_interrupt
|
||||
* Name: lpc11_i2c_transfer
|
||||
*
|
||||
* Description:
|
||||
* Perform a sequence of I2C transfers
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_I2C_TRANSFER
|
||||
static int lpc11_i2c_transfer(FAR struct i2c_master_s *dev,
|
||||
FAR struct i2c_msg_s *msgs, int count)
|
||||
{
|
||||
struct lpc11_i2cdev_s *priv = (struct lpc11_i2cdev_s *)dev;
|
||||
int ret;
|
||||
|
||||
DEBUGASSERT(dev != NULL);
|
||||
|
||||
priv->wrcnt = 0;
|
||||
priv->rdcnt = 0;
|
||||
priv->msgs = msgs;
|
||||
priv->nmsg = count;
|
||||
|
||||
ret = lpc11_i2c_start(priv);
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc11_i2c_interrupt
|
||||
*
|
||||
* Description:
|
||||
* Check if we need to issue STOP at the next message
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void lpc11_stopnext(struct lpc11_i2cdev_s *priv)
|
||||
{
|
||||
priv->nmsg--;
|
||||
|
||||
if (priv->nmsg > 0)
|
||||
{
|
||||
priv->msgs++;
|
||||
putreg32(I2C_CONSET_STA, priv->base + LPC11_I2C_CONSET_OFFSET);
|
||||
}
|
||||
else
|
||||
{
|
||||
lpc11_i2c_stop(priv);
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc11_i2c_interrupt
|
||||
*
|
||||
* Description:
|
||||
* The I2C Interrupt Handler
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int i2c_interrupt(int irq, FAR void *context)
|
||||
static int lpc11_i2c_interrupt(int irq, FAR void *context)
|
||||
{
|
||||
struct lpc11_i2cdev_s *priv;
|
||||
struct i2c_msg_s *msg;
|
||||
uint32_t state;
|
||||
|
||||
#ifdef CONFIG_LPC11_I2C0
|
||||
if (irq == LPC11_IRQ_I2C0)
|
||||
{
|
||||
priv = &i2cdevices[0];
|
||||
priv = &g_i2c0dev;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
#ifdef CONFIG_LPC11_I2C1
|
||||
if (irq == LPC11_IRQ_I2C1)
|
||||
{
|
||||
priv = &i2cdevices[1];
|
||||
priv = &g_i2c1dev;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
#ifdef CONFIG_LPC11_I2C2
|
||||
if (irq == LPC11_IRQ_I2C2)
|
||||
{
|
||||
priv = &i2cdevices[2];
|
||||
priv = &g_i2c2dev;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
@ -372,70 +457,82 @@ static int i2c_interrupt(int irq, FAR void *context)
|
||||
/* Reference UM10360 19.10.5 */
|
||||
|
||||
state = getreg32(priv->base + LPC11_I2C_STAT_OFFSET);
|
||||
putreg32(I2C_CONCLR_SIC, priv->base + LPC11_I2C_CONCLR_OFFSET);
|
||||
priv->state = state;
|
||||
state &= 0xf8;
|
||||
msg = priv->msgs;
|
||||
|
||||
priv->state = state;
|
||||
state &= 0xf8; /* state mask, only 0xX8 is possible */
|
||||
switch (state)
|
||||
{
|
||||
case 0x00: /* Bus Error */
|
||||
case 0x20:
|
||||
case 0x30:
|
||||
case 0x38:
|
||||
case 0x48:
|
||||
i2c_stop(priv);
|
||||
break;
|
||||
|
||||
case 0x08: /* START */
|
||||
case 0x10: /* Repeat START */
|
||||
putreg32(priv->msg.addr, priv->base + LPC11_I2C_DAT_OFFSET);
|
||||
case 0x08: /* A START condition has been transmitted. */
|
||||
case 0x10: /* A Repeated START condition has been transmitted. */
|
||||
/* Set address */
|
||||
|
||||
putreg32(((I2C_M_READ & msg->flags) == I2C_M_READ) ?
|
||||
I2C_READADDR8(msg->addr) :
|
||||
I2C_WRITEADDR8(msg->addr), priv->base + LPC11_I2C_DAT_OFFSET);
|
||||
|
||||
/* Clear start bit */
|
||||
|
||||
putreg32(I2C_CONCLR_STAC, priv->base + LPC11_I2C_CONCLR_OFFSET);
|
||||
break;
|
||||
|
||||
case 0x18:
|
||||
/* Write cases */
|
||||
|
||||
case 0x18: /* SLA+W has been transmitted; ACK has been received */
|
||||
priv->wrcnt = 0;
|
||||
putreg32(priv->msg.buffer[0], priv->base + LPC11_I2C_DAT_OFFSET);
|
||||
putreg32(msg->buffer[0], priv->base + LPC11_I2C_DAT_OFFSET); /* put first byte */
|
||||
break;
|
||||
|
||||
case 0x28:
|
||||
case 0x28: /* Data byte in DAT has been transmitted; ACK has been received. */
|
||||
priv->wrcnt++;
|
||||
if (priv->wrcnt < priv->msg.length)
|
||||
|
||||
if (priv->wrcnt < msg->length)
|
||||
{
|
||||
putreg32(priv->msg.buffer[priv->wrcnt], priv->base + LPC11_I2C_DAT_OFFSET);
|
||||
putreg32(msg->buffer[priv->wrcnt], priv->base + LPC11_I2C_DAT_OFFSET); /* Put next byte */
|
||||
}
|
||||
else
|
||||
{
|
||||
i2c_stop(priv);
|
||||
lpc11_stopnext(priv);
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x40:
|
||||
/* Read cases */
|
||||
|
||||
case 0x40: /* SLA+R has been transmitted; ACK has been received */
|
||||
priv->rdcnt = 0;
|
||||
putreg32(I2C_CONSET_AA, priv->base + LPC11_I2C_CONSET_OFFSET);
|
||||
break;
|
||||
|
||||
case 0x50:
|
||||
if (priv->rdcnt < priv->msg.length)
|
||||
if (msg->length > 1)
|
||||
{
|
||||
priv->msg.buffer[priv->rdcnt] = getreg32(priv->base + LPC11_I2C_BUFR_OFFSET);
|
||||
priv->rdcnt++;
|
||||
putreg32(I2C_CONSET_AA, priv->base + LPC11_I2C_CONSET_OFFSET); /* Set ACK next read */
|
||||
}
|
||||
|
||||
if (priv->rdcnt >= priv->msg.length)
|
||||
else
|
||||
{
|
||||
putreg32(I2C_CONCLR_AAC | I2C_CONCLR_SIC, priv->base + LPC11_I2C_CONCLR_OFFSET);
|
||||
putreg32(I2C_CONCLR_AAC, priv->base + LPC11_I2C_CONCLR_OFFSET); /* Do not ACK because only one byte */
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x58:
|
||||
i2c_stop(priv);
|
||||
case 0x50: /* Data byte has been received; ACK has been returned. */
|
||||
priv->rdcnt++;
|
||||
msg->buffer[priv->rdcnt - 1] = getreg32(priv->base + LPC11_I2C_BUFR_OFFSET);
|
||||
|
||||
if (priv->rdcnt >= (msg->length - 1))
|
||||
{
|
||||
putreg32(I2C_CONCLR_AAC, priv->base + LPC11_I2C_CONCLR_OFFSET); /* Do not ACK any more */
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x58: /* Data byte has been received; NACK has been returned. */
|
||||
msg->buffer[priv->rdcnt] = getreg32(priv->base + LPC11_I2C_BUFR_OFFSET);
|
||||
lpc11_stopnext(priv);
|
||||
break;
|
||||
|
||||
default:
|
||||
i2c_stop(priv);
|
||||
lpc11_i2c_stop(priv);
|
||||
break;
|
||||
}
|
||||
|
||||
putreg32(I2C_CONCLR_SIC, priv->base + LPC11_I2C_CONCLR_OFFSET); /* clear interrupt */
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
@ -454,95 +551,109 @@ static int i2c_interrupt(int irq, FAR void *context)
|
||||
struct i2c_master_s *up_i2cinitialize(int port)
|
||||
{
|
||||
struct lpc11_i2cdev_s *priv;
|
||||
irqstate_t flags;
|
||||
uint32_t regval;
|
||||
|
||||
if (port > 2)
|
||||
if (port > 1)
|
||||
{
|
||||
dbg("lpc I2C Only support 0,1,2\n");
|
||||
dbg("lpc I2C Only support 0,1\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
irqstate_t flags;
|
||||
uint32_t regval;
|
||||
|
||||
flags = irqsave();
|
||||
|
||||
priv = &i2cdevices[port];
|
||||
#ifdef CONFIG_LPC11_I2C0
|
||||
if (port == 0)
|
||||
{
|
||||
priv = (FAR struct lpc11_i2cdev_s *)&i2cdevices[0];
|
||||
priv = &g_i2c0dev;
|
||||
priv->base = LPC11_I2C0_BASE;
|
||||
priv->irqid = LPC11_IRQ_I2C0;
|
||||
|
||||
regval = getreg32(LPC11_SYSCON_PCONP);
|
||||
regval |= SYSCON_PCONP_PCI2C0;
|
||||
putreg32(regval, LPC11_SYSCON_PCONP);
|
||||
/* Enable clocking */
|
||||
|
||||
regval = getreg32(LPC11_SYSCON_PCLKSEL0);
|
||||
regval &= ~SYSCON_PCLKSEL0_I2C0_MASK;
|
||||
regval |= (SYSCON_PCLKSEL_CCLK << SYSCON_PCLKSEL0_I2C0_SHIFT);
|
||||
putreg32(regval, LPC11_SYSCON_PCLKSEL0);
|
||||
regval = getreg32(LPC11_SYSCON_SYSAHBCLKCTRL);
|
||||
regval |= SYSCON_SYSAHBCLKCTRL_I2C0;
|
||||
putreg32(regval, LPC11_SYSCON_SYSAHBCLKCTRL);
|
||||
|
||||
/* Pin configuration */
|
||||
|
||||
lpc11_configgpio(GPIO_I2C0_SCL);
|
||||
lpc11_configgpio(GPIO_I2C0_SDA);
|
||||
|
||||
putreg32(LPC11_CCLK/CONFIG_I2C0_FREQ/2, priv->base + LPC11_I2C_SCLH_OFFSET);
|
||||
putreg32(LPC11_CCLK/CONFIG_I2C0_FREQ/2, priv->base + LPC11_I2C_SCLL_OFFSET);
|
||||
/* Set default frequency */
|
||||
|
||||
lpc11_i2c_setfrequency((struct i2c_master_s *)priv,
|
||||
CONFIG_LPC11_I2C0_FREQUENCY);
|
||||
}
|
||||
else
|
||||
#endif
|
||||
#ifdef CONFIG_LPC11_I2C1
|
||||
if (port == 1)
|
||||
{
|
||||
priv = (FAR struct lpc11_i2cdev_s *)&i2cdevices[1];
|
||||
priv = &g_i2c1dev;
|
||||
priv->base = LPC11_I2C1_BASE;
|
||||
priv->irqid = LPC11_IRQ_I2C1;
|
||||
|
||||
regval = getreg32(LPC11_SYSCON_PCONP);
|
||||
regval |= SYSCON_PCONP_PCI2C1;
|
||||
putreg32(regval, LPC11_SYSCON_PCONP);
|
||||
/* Enable clocking */
|
||||
|
||||
regval = getreg32(LPC11_SYSCON_SYSAHBCLKCTRL);
|
||||
regval |= SYSCON_SYSAHBCLKCTRL_I2C1;
|
||||
putreg32(regval, LPC11_SYSCON_SYSAHBCLKCTRL);
|
||||
|
||||
regval = getreg32(LPC11_SYSCON_PCLKSEL1);
|
||||
regval &= ~SYSCON_PCLKSEL1_I2C1_MASK;
|
||||
regval |= (SYSCON_PCLKSEL_CCLK << SYSCON_PCLKSEL1_I2C1_SHIFT);
|
||||
putreg32(regval, LPC11_SYSCON_PCLKSEL1);
|
||||
|
||||
/* Pin configuration */
|
||||
|
||||
lpc11_configgpio(GPIO_I2C1_SCL);
|
||||
lpc11_configgpio(GPIO_I2C1_SDA);
|
||||
|
||||
putreg32(LPC11_CCLK/CONFIG_I2C1_FREQ/2, priv->base + LPC11_I2C_SCLH_OFFSET);
|
||||
putreg32(LPC11_CCLK/CONFIG_I2C1_FREQ/2, priv->base + LPC11_I2C_SCLL_OFFSET);
|
||||
/* Set default frequency */
|
||||
|
||||
lpc11_i2c_setfrequency((struct i2c_master_s *)priv,
|
||||
CONFIG_LPC11_I2C1_FREQUENCY);
|
||||
}
|
||||
else
|
||||
#endif
|
||||
#ifdef CONFIG_LPC11_I2C2
|
||||
if (port == 2)
|
||||
{
|
||||
priv = (FAR struct lpc11_i2cdev_s *)&i2cdevices[2];
|
||||
priv = &g_i2c2dev;
|
||||
priv->base = LPC11_I2C2_BASE;
|
||||
priv->irqid = LPC11_IRQ_I2C2;
|
||||
|
||||
regval = getreg32(LPC11_SYSCON_PCONP);
|
||||
regval |= SYSCON_PCONP_PCI2C2;
|
||||
putreg32(regval, LPC11_SYSCON_PCONP);
|
||||
/* Enable clocking */
|
||||
|
||||
regval = getreg32(LPC11_SYSCON_SYSAHBCLKCTRL);
|
||||
regval |= SYSCON_SYSAHBCLKCTRL_I2C2;
|
||||
putreg32(regval, LPC11_SYSCON_SYSAHBCLKCTRL);
|
||||
|
||||
regval = getreg32(LPC11_SYSCON_PCLKSEL1);
|
||||
regval &= ~SYSCON_PCLKSEL1_I2C2_MASK;
|
||||
regval |= (SYSCON_PCLKSEL_CCLK << SYSCON_PCLKSEL1_I2C2_SHIFT);
|
||||
putreg32(regval, LPC11_SYSCON_PCLKSEL1);
|
||||
|
||||
/* Pin configuration */
|
||||
|
||||
lpc11_configgpio(GPIO_I2C2_SCL);
|
||||
lpc11_configgpio(GPIO_I2C2_SDA);
|
||||
|
||||
putreg32(LPC11_CCLK/CONFIG_I2C2_FREQ/2, priv->base + LPC11_I2C_SCLH_OFFSET);
|
||||
putreg32(LPC11_CCLK/CONFIG_I2C2_FREQ/2, priv->base + LPC11_I2C_SCLL_OFFSET);
|
||||
/* Set default frequency */
|
||||
|
||||
lpc11_i2c_setfrequency((struct i2c_master_s *)priv,
|
||||
CONFIG_LPC11_I2C2_FREQUENCY);
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
irqrestore(flags);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
irqrestore(flags);
|
||||
|
||||
putreg32(I2C_CONSET_I2EN, priv->base + LPC11_I2C_CONSET_OFFSET);
|
||||
|
||||
sem_init(&priv->mutex, 0, 1);
|
||||
@ -555,7 +666,7 @@ struct i2c_master_s *up_i2cinitialize(int port)
|
||||
|
||||
/* Attach Interrupt Handler */
|
||||
|
||||
irq_attach(priv->irqid, i2c_interrupt);
|
||||
irq_attach(priv->irqid, lpc11_i2c_interrupt);
|
||||
|
||||
/* Enable Interrupt Handler */
|
||||
|
||||
@ -564,8 +675,6 @@ struct i2c_master_s *up_i2cinitialize(int port)
|
||||
/* Install our operations */
|
||||
|
||||
priv->dev.ops = &lpc11_i2c_ops;
|
||||
|
||||
irqrestore(flags);
|
||||
return &priv->dev;
|
||||
}
|
||||
|
||||
@ -605,4 +714,19 @@ int up_i2cuninitialize(FAR struct i2c_master_s * dev)
|
||||
return OK;
|
||||
}
|
||||
|
||||
#endif
|
||||
/****************************************************************************
|
||||
* Name: up_i2creset
|
||||
*
|
||||
* Description:
|
||||
* Reset an I2C bus
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_I2C_RESET
|
||||
int up_i2creset(FAR struct i2c_master_s * dev)
|
||||
{
|
||||
return OK;
|
||||
}
|
||||
#endif /* CONFIG_I2C_RESET */
|
||||
|
||||
#endif /* CONFIG_LPC11_I2C0 || CONFIG_LPC11_I2C1 || CONFIG_LPC11_I2C2 */
|
||||
|
||||
@ -104,7 +104,7 @@ void up_idle(void)
|
||||
* disabled in order to save power."
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_LPC17_GPDMA
|
||||
#ifdef CONFIG_LPC11_GPDMA
|
||||
if (g_dma_inprogress == 0)
|
||||
#endif
|
||||
{
|
||||
|
||||
@ -63,7 +63,7 @@
|
||||
* intended for use with the TIMER upper half driver.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_LPC17_TMR0)
|
||||
#if defined(CONFIG_LPC11_TMR0)
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
@ -169,14 +169,14 @@ static const struct pwm_ops_s g_pwmops =
|
||||
.ioctl = timer_ioctl,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_LPC17_TMR0
|
||||
#ifdef CONFIG_LPC11_TMR0
|
||||
static struct lpc11_timer_s g_pwm1dev =
|
||||
{
|
||||
.ops = &g_pwmops,
|
||||
.timid = 1,
|
||||
.channel = CONFIG_LPC17_MAT0_PIN,
|
||||
.channel = CONFIG_LPC11_MAT0_PIN,
|
||||
.timtype = TIMTYPE_TIM1,
|
||||
.base = LPC17_TMR1_BASE,
|
||||
.base = LPC11_TMR1_BASE,
|
||||
.pincfg = GPIO_MAT0p1_2,
|
||||
.pclk = (0x1 << 12),
|
||||
};
|
||||
@ -246,25 +246,25 @@ static void timer_dumpregs(struct lpc11_timer_s *priv, FAR const char *msg)
|
||||
{
|
||||
pwmdbg("%s:\n", msg);
|
||||
pwmdbg(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
|
||||
timer_getreg(priv, LPC17_PWM_MR0_OFFSET),
|
||||
timer_getreg(priv, LPC17_PWM_MR1_OFFSET),
|
||||
timer_getreg(priv, LPC17_PWM_MR2_OFFSET),
|
||||
timer_getreg(priv, LPC17_PWM_MR3_OFFSET));
|
||||
#if defined(CONFIG_LPC17_TMR0)
|
||||
timer_getreg(priv, LPC11_PWM_MR0_OFFSET),
|
||||
timer_getreg(priv, LPC11_PWM_MR1_OFFSET),
|
||||
timer_getreg(priv, LPC11_PWM_MR2_OFFSET),
|
||||
timer_getreg(priv, LPC11_PWM_MR3_OFFSET));
|
||||
#if defined(CONFIG_LPC11_TMR0)
|
||||
if (priv->timtype == TIMTYPE_ADVANCED)
|
||||
{
|
||||
pwmdbg(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
|
||||
timer_getreg(priv, LPC17_PWM_MR0_OFFSET),
|
||||
timer_getreg(priv, LPC17_PWM_MR1_OFFSET),
|
||||
timer_getreg(priv, LPC17_PWM_MR2_OFFSET),
|
||||
timer_getreg(priv, LPC17_PWM_MR3_OFFSET));
|
||||
timer_getreg(priv, LPC11_PWM_MR0_OFFSET),
|
||||
timer_getreg(priv, LPC11_PWM_MR1_OFFSET),
|
||||
timer_getreg(priv, LPC11_PWM_MR2_OFFSET),
|
||||
timer_getreg(priv, LPC11_PWM_MR3_OFFSET));
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
pwmdbg(" DCR: %04x DMAR: %04x\n",
|
||||
timer_getreg(priv, LPC17_PWM_MR2_OFFSET),
|
||||
timer_getreg(priv, LPC17_PWM_MR3_OFFSET));
|
||||
timer_getreg(priv, LPC11_PWM_MR2_OFFSET),
|
||||
timer_getreg(priv, LPC11_PWM_MR3_OFFSET));
|
||||
}
|
||||
}
|
||||
#endif
|
||||
@ -292,11 +292,11 @@ static int timer_timer(FAR struct lpc11_timer_s *priv,
|
||||
|
||||
flags = irqsave();
|
||||
|
||||
putreg32(info->frequency, LPC17_TMR0_MR1); /* Set TIMER0 MR1 = number of counts */
|
||||
putreg32(info->frequency, LPC17_TMR1_MR0); /* Set TIMER1 MR0 = number of counts */
|
||||
putreg32(info->frequency, LPC11_TMR0_MR1); /* Set TIMER0 MR1 = number of counts */
|
||||
putreg32(info->frequency, LPC11_TMR1_MR0); /* Set TIMER1 MR0 = number of counts */
|
||||
|
||||
putreg32(1, LPC17_TMR0_TCR); /* Start timer0 */
|
||||
putreg32(1, LPC17_TMR1_TCR); /* Start timer1 */
|
||||
putreg32(1, LPC11_TMR0_TCR); /* Start timer0 */
|
||||
putreg32(1, LPC11_TMR1_TCR); /* Start timer1 */
|
||||
|
||||
irqrestore(flags);
|
||||
timer_dumpregs(priv, "After starting");
|
||||
@ -389,55 +389,55 @@ static int timer_setup(FAR struct pwm_lowerhalf_s *dev)
|
||||
|
||||
/* Power on the timer peripherals */
|
||||
|
||||
regval = getreg32(LPC17_SYSCON_PCONP);
|
||||
regval = getreg32(LPC11_SYSCON_PCONP);
|
||||
regval |= SYSCON_PCONP_PCTIM0;
|
||||
regval |= SYSCON_PCONP_PCTIM1;
|
||||
regval |= SYSCON_PCONP_PCTIM2;
|
||||
regval |= SYSCON_PCONP_PCTIM3;
|
||||
putreg32(regval, LPC17_SYSCON_PCONP);
|
||||
putreg32(regval, LPC11_SYSCON_PCONP);
|
||||
|
||||
/* Select clock for the timer peripheral */
|
||||
|
||||
regval = getreg32(LPC17_SYSCON_PCLKSEL0);
|
||||
regval = getreg32(LPC11_SYSCON_PCLKSEL0);
|
||||
regval &= ~(0x3 << 2);
|
||||
regval |= (0x1 << 2); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */
|
||||
regval &= ~(0x3 << 4);
|
||||
regval |= (0x1 << 4); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */
|
||||
putreg32(regval, LPC17_SYSCON_PCLKSEL0);
|
||||
regval = getreg32(LPC17_SYSCON_PCLKSEL1);
|
||||
putreg32(regval, LPC11_SYSCON_PCLKSEL0);
|
||||
regval = getreg32(LPC11_SYSCON_PCLKSEL1);
|
||||
regval &= ~(0x3 << 12);
|
||||
regval |= (0x1 << 12); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */
|
||||
regval &= ~(0x3 << 14);
|
||||
regval |= (0x1 << 14); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */
|
||||
putreg32(regval, LPC17_SYSCON_PCLKSEL1);
|
||||
putreg32(regval, LPC11_SYSCON_PCLKSEL1);
|
||||
priv->pclk = (0x1 << 12) | (0x1 << 4);
|
||||
|
||||
putreg32(1000, LPC17_TMR0_MR1); /* Set TIMER0 MR1 = number of counts */
|
||||
putreg32(1000, LPC11_TMR0_MR1); /* Set TIMER0 MR1 = number of counts */
|
||||
|
||||
putreg32(1, LPC17_TMR0_PR); /* Prescaler count frequency: Fpclk/1 */
|
||||
putreg32(~(0x3 << 0), LPC17_TMR0_CCR); /* Prescaler count frequency: Fpclk/1 */
|
||||
putreg32(~(0x3 << 0), LPC17_TMR0_CTCR); /* Prescaler count frequency: Fpclk/1 */
|
||||
putreg32((2 << 3), LPC17_TMR0_MCR); /* Reset on match register MR1 */
|
||||
putreg32(1, LPC11_TMR0_PR); /* Prescaler count frequency: Fpclk/1 */
|
||||
putreg32(~(0x3 << 0), LPC11_TMR0_CCR); /* Prescaler count frequency: Fpclk/1 */
|
||||
putreg32(~(0x3 << 0), LPC11_TMR0_CTCR); /* Prescaler count frequency: Fpclk/1 */
|
||||
putreg32((2 << 3), LPC11_TMR0_MCR); /* Reset on match register MR1 */
|
||||
|
||||
/* Output bit toggle on external match event External match on MR1, Toggle
|
||||
* external bit
|
||||
*/
|
||||
|
||||
putreg32(((1 << 1) | (3 << 6)), LPC17_TMR0_EMR);
|
||||
putreg32((1 << 0), LPC17_TMR0_TCR); /* Start timer0 */
|
||||
putreg32(((1 << 1) | (3 << 6)), LPC11_TMR0_EMR);
|
||||
putreg32((1 << 0), LPC11_TMR0_TCR); /* Start timer0 */
|
||||
|
||||
/* Configure the output pins GPIO3.26 */
|
||||
|
||||
lpc11_configgpio(GPIO_MAT0p1_2);
|
||||
|
||||
putreg32(500, LPC17_TMR1_MR0); /* Set TIMER1 MR0 = number of counts */
|
||||
putreg32(500, LPC11_TMR1_MR0); /* Set TIMER1 MR0 = number of counts */
|
||||
|
||||
putreg32(1, LPC17_TMR1_PR); /* Prescaler count frequency:Fpclk/1 */
|
||||
putreg32(~(0x3 << 0), LPC17_TMR1_CCR); /* Prescaler count frequency:Fpclk/1 */
|
||||
putreg32(~(0x3 << 0), LPC17_TMR1_CTCR); /* Prescaler count frequency:Fpclk/1 */
|
||||
putreg32((2 << 0), LPC17_TMR1_MCR); /* Reset on match register MR0 */
|
||||
// putreg32(((1 << 0) | (3 << 4)), LPC17_TMR1_EMR); /* Output bit toggle on external match event MAT0 */
|
||||
putreg32((1 << 0), LPC17_TMR1_TCR); /* Start timer1 */
|
||||
putreg32(1, LPC11_TMR1_PR); /* Prescaler count frequency:Fpclk/1 */
|
||||
putreg32(~(0x3 << 0), LPC11_TMR1_CCR); /* Prescaler count frequency:Fpclk/1 */
|
||||
putreg32(~(0x3 << 0), LPC11_TMR1_CTCR); /* Prescaler count frequency:Fpclk/1 */
|
||||
putreg32((2 << 0), LPC11_TMR1_MCR); /* Reset on match register MR0 */
|
||||
// putreg32(((1 << 0) | (3 << 4)), LPC11_TMR1_EMR); /* Output bit toggle on external match event MAT0 */
|
||||
putreg32((1 << 0), LPC11_TMR1_TCR); /* Start timer1 */
|
||||
|
||||
/* configure the output pins GPIO3.26 */
|
||||
// lpc11_configgpio(GPIO_MAT0p1_2);
|
||||
@ -538,7 +538,7 @@ static int timer_stop(FAR struct pwm_lowerhalf_s *dev)
|
||||
|
||||
switch (priv->timid)
|
||||
{
|
||||
#ifdef CONFIG_LPC17_TMR0
|
||||
#ifdef CONFIG_LPC11_TMR0
|
||||
case 1:
|
||||
break;
|
||||
#endif
|
||||
@ -613,7 +613,7 @@ FAR struct pwm_lowerhalf_s *lpc11_timerinitialize(int timer)
|
||||
|
||||
switch (timer)
|
||||
{
|
||||
#ifdef CONFIG_LPC17_TMR0
|
||||
#ifdef CONFIG_LPC11_TMR0
|
||||
case 0:
|
||||
lower = &g_pwm1dev;
|
||||
|
||||
@ -630,4 +630,4 @@ FAR struct pwm_lowerhalf_s *lpc11_timerinitialize(int timer)
|
||||
return (FAR struct pwm_lowerhalf_s *)lower;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_LPC17_TIMn_TIMER, n = 1,...,14 */
|
||||
#endif /* CONFIG_LPC11_TIMn_TIMER, n = 1,...,14 */
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc17xx/lpc17_timer.h
|
||||
* arch/arm/src/lpc17xx/lpc11_timer.h
|
||||
*
|
||||
* Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
@ -33,15 +33,15 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_TIMER_H
|
||||
#define __ARCH_ARM_SRC_LPC17XX_LPC17_TIMER_H
|
||||
#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_TIMER_H
|
||||
#define __ARCH_ARM_SRC_LPC11XX_LPC11_TIMER_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip/lpc17_timer.h"
|
||||
#include "chip/lpc11_timer.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
@ -59,4 +59,4 @@
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_TIMER_H */
|
||||
#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_TIMER_H */
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc17xx/lpc17_userspace.h
|
||||
* arch/arm/src/lpc17xx/lpc11_userspace.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
@ -33,8 +33,8 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_USERSPACE_H
|
||||
#define __ARCH_ARM_SRC_LPC17XX_LPC17_USERSPACE_H
|
||||
#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_USERSPACE_H
|
||||
#define __ARCH_ARM_SRC_LPC11XX_LPC11_USERSPACE_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
@ -59,7 +59,7 @@
|
||||
************************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc17_userspace
|
||||
* Name: lpc11_userspace
|
||||
*
|
||||
* Description:
|
||||
* For the case of the separate user-/kernel-space build, perform whatever
|
||||
@ -70,7 +70,7 @@
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
void lpc17_userspace(void);
|
||||
void lpc11_userspace(void);
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_USERSPACE_H */
|
||||
#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_USERSPACE_H */
|
||||
|
||||
@ -33,8 +33,8 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_WDT_H
|
||||
#define __ARCH_ARM_SRC_LPC17XX_LPC17_WDT_H
|
||||
#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_WDT_H
|
||||
#define __ARCH_ARM_SRC_LPC11XX_LPC11_WDT_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
@ -59,4 +59,4 @@
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_WDT_H */
|
||||
#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_WDT_H */
|
||||
|
||||
@ -612,17 +612,17 @@ config GPIO_IRQ
|
||||
menu "I2C driver options"
|
||||
depends on LPC17_I2C0 || LPC17_I2C1 || LPC17_I2C2
|
||||
|
||||
config I2C0_DEFAULT_FREQUENCY
|
||||
config LPC17_I2C0_FREQUENCY
|
||||
int "I2C0 frequency"
|
||||
depends on LPC17_I2C0
|
||||
default 100000
|
||||
|
||||
config I2C1_DEFAULT_FREQUENCY
|
||||
config LPC17_I2C1_FREQUENCY
|
||||
int "I2C1 frequency"
|
||||
depends on LPC17_I2C1
|
||||
default 100000
|
||||
|
||||
config I2C2_DEFAULT_FREQUENCY
|
||||
config LPC17_I2C2_FREQUENCY
|
||||
int "I2C2 frequency"
|
||||
depends on LPC17_I2C2
|
||||
default 100000
|
||||
|
||||
@ -83,20 +83,20 @@
|
||||
# define GPIO_I2C1_SDA GPIO_I2C1_SDA_1
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_I2C0_DEFAULT_FREQUENCY
|
||||
# define CONFIG_I2C0_DEFAULT_FREQUENCY 100000
|
||||
#ifndef CONFIG_LPC17_I2C0_FREQUENCY
|
||||
# define CONFIG_LPC17_I2C0_FREQUENCY 100000
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_I2C1_DEFAULT_FREQUENCY
|
||||
# define CONFIG_I2C1_DEFAULT_FREQUENCY 100000
|
||||
#ifndef CONFIG_LPC17_I2C1_FREQUENCY
|
||||
# define CONFIG_LPC17_I2C1_FREQUENCY 100000
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_I2C2_DEFAULT_FREQUENCY
|
||||
# define CONFIG_I2C2_DEFAULT_FREQUENCY 100000
|
||||
#ifndef CONFIG_LPC17_I2C2_FREQUENCY
|
||||
# define CONFIG_LPC17_I2C2_FREQUENCY 100000
|
||||
#endif
|
||||
|
||||
#define I2C_TIMEOUT (20 * 1000/CONFIG_USEC_PER_TICK) /* 20 mS */
|
||||
#define I2C1_DEFAULT_FREQUENCY 400000
|
||||
#define LPC17_I2C1_FREQUENCY 400000
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
@ -589,7 +589,7 @@ struct i2c_master_s *up_i2cinitialize(int port)
|
||||
/* Set default frequency */
|
||||
|
||||
lpc17_i2c_setfrequency((struct i2c_master_s *)priv,
|
||||
CONFIG_I2C0_DEFAULT_FREQUENCY);
|
||||
CONFIG_LPC17_I2C0_FREQUENCY);
|
||||
}
|
||||
else
|
||||
#endif
|
||||
@ -619,7 +619,7 @@ struct i2c_master_s *up_i2cinitialize(int port)
|
||||
/* Set default frequency */
|
||||
|
||||
lpc17_i2c_setfrequency((struct i2c_master_s *)priv,
|
||||
CONFIG_I2C1_DEFAULT_FREQUENCY);
|
||||
CONFIG_LPC17_I2C1_FREQUENCY);
|
||||
}
|
||||
else
|
||||
#endif
|
||||
@ -649,7 +649,7 @@ struct i2c_master_s *up_i2cinitialize(int port)
|
||||
/* Set default frequency */
|
||||
|
||||
lpc17_i2c_setfrequency((struct i2c_master_s *)priv,
|
||||
CONFIG_I2C2_DEFAULT_FREQUENCY);
|
||||
CONFIG_LPC17_I2C2_FREQUENCY);
|
||||
}
|
||||
else
|
||||
#endif
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user