SAMV7: Quick'n'dirty port of the SAMA5 HSMCI driver to the SAMV7
This commit is contained in:
Gregory Nutt
parent
0d79e315fd
commit
8f59fc8f64
@ -68,7 +68,7 @@
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#define SAM_PID_USART2 (15) /* USART 2 */
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#define SAM_PID_PIOD (16) /* Parallel I/O Controller D */
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#define SAM_PID_PIOE (17) /* Parallel I/O Controller E */
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#define SAM_PID_HSMCI (18) /* High Speed Multimedia Card Interface */
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#define SAM_PID_HSMCI0 (18) /* High Speed Multimedia Card Interface */
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#define SAM_PID_TWIHS0 (19) /* Two-Wire Interface 0 */
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#define SAM_PID_TWIHS1 (20) /* Two-Wire Interface 1 */
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#define SAM_PID_SPI0 (21) /* Serial Peripheral Interface 0 */
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@ -138,11 +138,11 @@
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#define SAM_IRQ_USART2 (SAM_IRQ_EXTINT+SAM_PID_USART2) /* USART 2 */
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#define SAM_IRQ_PIOD (SAM_IRQ_EXTINT+SAM_PID_PIOD) /* Parallel I/O Controller D */
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#define SAM_IRQ_PIOE (SAM_IRQ_EXTINT+SAM_PID_PIOE) /* Parallel I/O Controller E */
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#define SAM_IRQ_HSMCI (SAM_IRQ_EXTINT+SAM_PID_HSMCI) /* High Speed Multimedia Card Interface */
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#define SAM_IRQ_HSMCI0 (SAM_IRQ_EXTINT+SAM_PID_HSMCI0) /* High Speed Multimedia Card Interface */
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#define SAM_IRQ_TWIHS0 (SAM_IRQ_EXTINT+SAM_PID_TWIHS0) /* Two-Wire Interface 0 */
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#define SAM_IRQ_TWIHS1 (SAM_IRQ_EXTINT+SAM_PID_TWIHS1) /* Two-Wire Interface 1 */
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#define SAM_IRQ_SPI0 (SAM_IRQ_EXTINT+SAM_PID_SPI0) /* Serial Peripheral Interface 0 */
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#define SAM_IRQ_SSC0 (SAM_IRQ_EXTINT+SAM_PID_SSC) /* Synchronous Serial Controller */
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#define SAM_IRQ_SSC0 (SAM_IRQ_EXTINT+SAM_PID_SSC0) /* Synchronous Serial Controller */
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#define SAM_IRQ_TC0 (SAM_IRQ_EXTINT+SAM_PID_TC0) /* Timer Counter 0 */
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#define SAM_IRQ_TC1 (SAM_IRQ_EXTINT+SAM_PID_TC1) /* Timer Counter 1 */
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#define SAM_IRQ_TC2 (SAM_IRQ_EXTINT+SAM_PID_TC2) /* Timer Counter 2 */
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@ -68,7 +68,7 @@ config ARCH_CHIP_SAMV71Q
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select SAMV7_HAVE_CAN1
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select SAMV7_HAVE_DAC1
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select SAMV7_HAVE_EBI
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select SAMV7_HAVE_HSMCI
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select SAMV7_HAVE_HSMCI0
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select SAMV7_HAVE_SDRAMC
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select SAMV7_HAVE_SPI0
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select SAMV7_HAVE_SPI1
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@ -84,7 +84,7 @@ config ARCH_CHIP_SAMV71N
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select ARCH_CHIP_SAMV71
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select SAMV7_HAVE_CAN1
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select SAMV7_HAVE_DAC1
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select SAMV7_HAVE_HSMCI
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select SAMV7_HAVE_HSMCI0
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select SAMV7_HAVE_SPI0
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select SAMV7_HAVE_TWIHS2
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select SAMV7_HAVE_USBHS
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@ -114,7 +114,11 @@ config SAMV7_HAVE_EBI
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bool
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default n
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config SAMV7_HAVE_HSMCI
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config SAMV7_HSMCI
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bool
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default n
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config SAMV7_HAVE_HSMCI0
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bool
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default n
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@ -224,10 +228,11 @@ config SAMV7_XDMAC
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default n
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select ARCH_DMA
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config SAMV7_HSMCI
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config SAMV7_HSMCI0
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bool "High Speed Multimedia Card Interface (HSMCI)"
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default n
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depends on SAMV7_HAVE_HSMCI
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depends on SAMV7_HAVE_HSMCI0
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select SAMV7_HSMCI
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select ARCH_HAVE_SDIO
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select MMCSD
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@ -936,3 +941,57 @@ config SAMV7_SSC_DUMPBUFFERS
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endmenu # SSC Configuration
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endif # SAMV7_SSC
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if SAMA5_HSMCI
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menu "HSMCI device driver options"
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config SAMA5_HSMCI_RDPROOF
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bool "Read Proof Enable"
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default n
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---help---
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Enabling Read Proof allows to stop the HSMCI Clock during read
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access if the internal FIFO is full. This will guarantee data
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integrity, not bandwidth.
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config SAMA5_HSMCI_WRPROOF
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bool "Write Proof Enable"
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default n
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---help---
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Enabling Write Proof allows to stop the HSMCI Clock during write
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access if the internal FIFO is full. This will guarantee data
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integrity, not bandwidth.
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config SAMA5_HSMCI_XFRDEBUG
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bool "HSMCI transfer debug"
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depends on DEBUG_FS && DEBUG_VERBOSE
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default n
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---help---
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Enable special debug instrumentation analyze HSMCI data transfers.
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This logic is as non-invasive as possible: It samples HSMCI
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registers at key points in the data transfer and then dumps all of
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the registers at the end of the transfer. If DEBUG_DMA is also
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enabled, then DMA register will be collected as well. Requires also
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DEBUG_FS and DEBUG_VERBOSE.
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config SAMA5_HSMCI_CMDDEBUG
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bool "HSMCI command debug"
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depends on DEBUG_FS && DEBUG_VERBOSE
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default n
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---help---
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Enable special debug instrumentation analyze HSMCI commands. This
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logic is as non-invasive as possible: It samples HSMCI registers at
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key points in the data transfer and then dumps all of the registers
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at the end of the transfer. If DEBUG_DMA is also enabled, then DMA
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register will be collected as well. Requires also DEBUG_FS and
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DEBUG_VERBOSE.
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config SAMA5_HSMCI_REGDEBUG
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bool "HSMCI Register level debug"
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depends on DEBUG
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default n
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---help---
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Output detailed register-level HSCMI device debug information.
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Very invasive! Requires also DEBUG.
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endmenu # HSMCI device driver options
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endif # SAMA5_HSMCI
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@ -136,3 +136,7 @@ endif
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ifeq ($(CONFIG_SAMV7_SSC),y)
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CHIP_CSRCS += sam_ssc.c
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endif
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ifeq ($(CONFIG_SAMV7_HSMCI),y)
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CHIP_CSRCS += sam_hsmci.c sam_hsmci_clkdiv.c
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endif
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366
arch/arm/src/samv7/chip/sam_hsmci.h
Normal file
366
arch/arm/src/samv7/chip/sam_hsmci.h
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@ -0,0 +1,366 @@
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/****************************************************************************************
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* arch/arm/src/samv7/chip/sam_hsmci.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_HSMCI_H
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#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_HSMCI_H
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/****************************************************************************************
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* Included Files
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****************************************************************************************/
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#include <nuttx/config.h>
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#include <arch/samv7/chip.h>
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#include "chip/sam_memorymap.h"
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#if SAMV7_NHSMCI4 > 0
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/****************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************/
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/* HSMCI register offsets ***************************************************************/
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#define SAM_HSMCI_CR_OFFSET 0x0000 /* Control Register */
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#define SAM_HSMCI_MR_OFFSET 0x0004 /* Mode Register */
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#define SAM_HSMCI_DTOR_OFFSET 0x0008 /* Data Timeout Register */
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#define SAM_HSMCI_SDCR_OFFSET 0x000c /* SD/SDIO Card Register */
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#define SAM_HSMCI_ARGR_OFFSET 0x0010 /* Argument Register */
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#define SAM_HSMCI_CMDR_OFFSET 0x0014 /* Command Register */
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#define SAM_HSMCI_BLKR_OFFSET 0x0018 /* Block Register */
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#define SAM_HSMCI_CSTOR_OFFSET 0x001c /* Completion Signal Timeout Register */
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#define SAM_HSMCI_RSPR0_OFFSET 0x0020 /* Response Register 0 */
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#define SAM_HSMCI_RSPR1_OFFSET 0x0024 /* Response Register 1 */
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#define SAM_HSMCI_RSPR2_OFFSET 0x0028 /* Response Register 2 */
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#define SAM_HSMCI_RSPR3_OFFSET 0x002c /* Response Register 3 */
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#define SAM_HSMCI_RDR_OFFSET 0x0030 /* Receive Data Register */
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#define SAM_HSMCI_TDR_OFFSET 0x0034 /* Transmit Data Register */
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/* 0x0038-0x003c: Reserved */
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#define SAM_HSMCI_SR_OFFSET 0x0040 /* Status Register */
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#define SAM_HSMCI_IER_OFFSET 0x0044 /* Interrupt Enable Register */
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#define SAM_HSMCI_IDR_OFFSET 0x0048 /* Interrupt Disable Register */
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#define SAM_HSMCI_IMR_OFFSET 0x004c /* Interrupt Mask Register */
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#define SAM_HSMCI_DMA_OFFSET 0x0050 /* DMA Configuration Register */
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#define SAM_HSMCI_CFG_OFFSET 0x0054 /* Configuration Register */
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/* 0x0058-0x00e0: Reserved */
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#define SAM_HSMCI_WPMR_OFFSET 0x00e4 /* Write Protection Mode Register */
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#define SAM_HSMCI_WPSR_OFFSET 0x00e8 /* Write Protection Status Register */
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/* 0x00ec-0x00fc: Reserved */
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/* 0x0100-0x0124: Reserved for PCD registers */
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#define SAM_HSMCI_FIFO_OFFSET 0x0200 /* 0x0200-0x05fc FIFO Memory Aperture */
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/* HSMCI register addresses *************************************************************/
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#define SAM_HSMCI0_CR (SAM_HSMCI0_BASE+SAM_HSMCI_CR_OFFSET)
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#define SAM_HSMCI0_MR (SAM_HSMCI0_BASE+SAM_HSMCI_MR_OFFSET)
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#define SAM_HSMCI0_DTOR (SAM_HSMCI0_BASE+SAM_HSMCI_DTOR_OFFSET)
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#define SAM_HSMCI0_SDCR (SAM_HSMCI0_BASE+SAM_HSMCI_SDCR_OFFSET)
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#define SAM_HSMCI0_ARGR (SAM_HSMCI0_BASE+SAM_HSMCI_ARGR_OFFSET)
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#define SAM_HSMCI0_CMDR (SAM_HSMCI0_BASE+SAM_HSMCI_CMDR_OFFSET)
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#define SAM_HSMCI0_BLKR (SAM_HSMCI0_BASE+SAM_HSMCI_BLKR_OFFSET)
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#define SAM_HSMCI0_CSTOR (SAM_HSMCI0_BASE+SAM_HSMCI_CSTOR_OFFSET)
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#define SAM_HSMCI0_RSPR0 (SAM_HSMCI0_BASE+SAM_HSMCI_RSPR0_OFFSET)
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#define SAM_HSMCI0_RSPR1 (SAM_HSMCI0_BASE+SAM_HSMCI_RSPR1_OFFSET)
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#define SAM_HSMCI0_RSPR2 (SAM_HSMCI0_BASE+SAM_HSMCI_RSPR2_OFFSET)
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#define SAM_HSMCI0_RSPR3 (SAM_HSMCI0_BASE+SAM_HSMCI_RSPR3_OFFSET)
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#define SAM_HSMCI0_RDR (SAM_HSMCI0_BASE+SAM_HSMCI_RDR_OFFSET)
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#define SAM_HSMCI0_TDR (SAM_HSMCI0_BASE+SAM_HSMCI_TDR_OFFSET)
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#define SAM_HSMCI0_SR (SAM_HSMCI0_BASE+SAM_HSMCI_SR_OFFSET)
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#define SAM_HSMCI0_IER (SAM_HSMCI0_BASE+SAM_HSMCI_IER_OFFSET)
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#define SAM_HSMCI0_IDR (SAM_HSMCI0_BASE+SAM_HSMCI_IDR_OFFSET)
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#define SAM_HSMCI0_IMR (SAM_HSMCI0_BASE+SAM_HSMCI_IMR_OFFSET)
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#define SAM_HSMCI0_DMA (SAM_HSMCI0_BASE+SAM_HSMCI_DMA_OFFSET)
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#define SAM_HSMCI0_CFG (SAM_HSMCI0_BASE+SAM_HSMCI_CFG_OFFSET)
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#define SAM_HSMCI0_WPMR (SAM_HSMCI0_BASE+SAM_HSMCI_WPMR_OFFSET)
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#define SAM_HSMCI0_WPSR (SAM_HSMCI0_BASE+SAM_HSMCI_WPSR_OFFSET)
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#define SAM_HSMCI0_FIFO (SAM_HSMCI0_BASE+SAM_HSMCI_FIFO_OFFSET)
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#if SAMV7_NHSMCI4 > 1
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# define SAM_HSMCI1_CR (SAM_HSMCI1_BASE+SAM_HSMCI_CR_OFFSET)
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# define SAM_HSMCI1_MR (SAM_HSMCI1_BASE+SAM_HSMCI_MR_OFFSET)
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# define SAM_HSMCI1_DTOR (SAM_HSMCI1_BASE+SAM_HSMCI_DTOR_OFFSET)
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# define SAM_HSMCI1_SDCR (SAM_HSMCI1_BASE+SAM_HSMCI_SDCR_OFFSET)
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# define SAM_HSMCI1_ARGR (SAM_HSMCI1_BASE+SAM_HSMCI_ARGR_OFFSET)
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# define SAM_HSMCI1_CMDR (SAM_HSMCI1_BASE+SAM_HSMCI_CMDR_OFFSET)
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# define SAM_HSMCI1_BLKR (SAM_HSMCI1_BASE+SAM_HSMCI_BLKR_OFFSET)
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# define SAM_HSMCI1_CSTOR (SAM_HSMCI1_BASE+SAM_HSMCI_CSTOR_OFFSET)
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# define SAM_HSMCI1_RSPR0 (SAM_HSMCI1_BASE+SAM_HSMCI_RSPR0_OFFSET)
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# define SAM_HSMCI1_RSPR1 (SAM_HSMCI1_BASE+SAM_HSMCI_RSPR1_OFFSET)
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# define SAM_HSMCI1_RSPR2 (SAM_HSMCI1_BASE+SAM_HSMCI_RSPR2_OFFSET)
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# define SAM_HSMCI1_RSPR3 (SAM_HSMCI1_BASE+SAM_HSMCI_RSPR3_OFFSET)
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# define SAM_HSMCI1_RDR (SAM_HSMCI1_BASE+SAM_HSMCI_RDR_OFFSET)
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# define SAM_HSMCI1_TDR (SAM_HSMCI1_BASE+SAM_HSMCI_TDR_OFFSET)
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# define SAM_HSMCI1_SR (SAM_HSMCI1_BASE+SAM_HSMCI_SR_OFFSET)
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# define SAM_HSMCI1_IER (SAM_HSMCI1_BASE+SAM_HSMCI_IER_OFFSET)
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# define SAM_HSMCI1_IDR (SAM_HSMCI1_BASE+SAM_HSMCI_IDR_OFFSET)
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# define SAM_HSMCI1_IMR (SAM_HSMCI1_BASE+SAM_HSMCI_IMR_OFFSET)
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# define SAM_HSMCI1_DMA (SAM_HSMCI1_BASE+SAM_HSMCI_DMA_OFFSET)
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# define SAM_HSMCI1_CFG (SAM_HSMCI1_BASE+SAM_HSMCI_CFG_OFFSET)
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# define SAM_HSMCI1_WPMR (SAM_HSMCI1_BASE+SAM_HSMCI_WPMR_OFFSET)
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# define SAM_HSMCI1_WPSR (SAM_HSMCI1_BASE+SAM_HSMCI_WPSR_OFFSET)
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# define SAM_HSMCI1_FIFO (SAM_HSMCI1_BASE+SAM_HSMCI_FIFO_OFFSET)
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#endif
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#if SAMV7_NHSMCI4 > 2
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# define SAM_HSMCI2_CR (SAM_HSMCI2_BASE+SAM_HSMCI_CR_OFFSET)
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# define SAM_HSMCI2_MR (SAM_HSMCI2_BASE+SAM_HSMCI_MR_OFFSET)
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# define SAM_HSMCI2_DTOR (SAM_HSMCI2_BASE+SAM_HSMCI_DTOR_OFFSET)
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# define SAM_HSMCI2_SDCR (SAM_HSMCI2_BASE+SAM_HSMCI_SDCR_OFFSET)
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# define SAM_HSMCI2_ARGR (SAM_HSMCI2_BASE+SAM_HSMCI_ARGR_OFFSET)
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# define SAM_HSMCI2_CMDR (SAM_HSMCI2_BASE+SAM_HSMCI_CMDR_OFFSET)
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# define SAM_HSMCI2_BLKR (SAM_HSMCI2_BASE+SAM_HSMCI_BLKR_OFFSET)
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# define SAM_HSMCI2_CSTOR (SAM_HSMCI2_BASE+SAM_HSMCI_CSTOR_OFFSET)
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# define SAM_HSMCI2_RSPR0 (SAM_HSMCI2_BASE+SAM_HSMCI_RSPR0_OFFSET)
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# define SAM_HSMCI2_RSPR1 (SAM_HSMCI2_BASE+SAM_HSMCI_RSPR1_OFFSET)
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# define SAM_HSMCI2_RSPR2 (SAM_HSMCI2_BASE+SAM_HSMCI_RSPR2_OFFSET)
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# define SAM_HSMCI2_RSPR3 (SAM_HSMCI2_BASE+SAM_HSMCI_RSPR3_OFFSET)
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# define SAM_HSMCI2_RDR (SAM_HSMCI2_BASE+SAM_HSMCI_RDR_OFFSET)
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# define SAM_HSMCI2_TDR (SAM_HSMCI2_BASE+SAM_HSMCI_TDR_OFFSET)
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# define SAM_HSMCI2_SR (SAM_HSMCI2_BASE+SAM_HSMCI_SR_OFFSET)
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# define SAM_HSMCI2_IER (SAM_HSMCI2_BASE+SAM_HSMCI_IER_OFFSET)
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# define SAM_HSMCI2_IDR (SAM_HSMCI2_BASE+SAM_HSMCI_IDR_OFFSET)
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# define SAM_HSMCI2_IMR (SAM_HSMCI2_BASE+SAM_HSMCI_IMR_OFFSET)
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# define SAM_HSMCI2_DMA (SAM_HSMCI2_BASE+SAM_HSMCI_DMA_OFFSET)
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# define SAM_HSMCI2_CFG (SAM_HSMCI2_BASE+SAM_HSMCI_CFG_OFFSET)
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# define SAM_HSMCI2_WPMR (SAM_HSMCI2_BASE+SAM_HSMCI_WPMR_OFFSET)
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# define SAM_HSMCI2_WPSR (SAM_HSMCI2_BASE+SAM_HSMCI_WPSR_OFFSET)
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# define SAM_HSMCI2_FIFO (SAM_HSMCI2_BASE+SAM_HSMCI_FIFO_OFFSET)
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#endif
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/* HSMCI register bit definitions *******************************************************/
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/* HSMCI Control Register */
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#define HSMCI_CR_MCIEN (1 << 0) /* Bit 0: Multi-Media Interface Enable */
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#define HSMCI_CR_MCIDIS (1 << 1) /* Bit 1: Multi-Media Interface Disable */
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#define HSMCI_CR_PWSEN (1 << 2) /* Bit 2: Power Save Mode Enable */
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#define HSMCI_CR_PWSDIS (1 << 3) /* Bit 3: Power Save Mode Disable */
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#define HSMCI_CR_SWRST (1 << 7) /* Bit 7: Software Reset */
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/* HSMCI Mode Register */
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#define HSMCI_MR_CLKDIV_SHIFT (0) /* Bits 0-7: Clock Divider */
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#define HSMCI_MR_CLKDIV_MASK (0xff << HSMCI_MR_CLKDIV_SHIFT)
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# define HSMCI_MR_CLKDIV(n) ((uint32_t)(n) << HSMCI_MR_CLKDIV_SHIFT)
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#define HSMCI_MR_PWSDIV_SHIFT (8) /* Bits 8-10: Power Saving Divider */
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#define HSMCI_MR_PWSDIV_MASK (7 << HSMCI_MR_PWSDIV_SHIFT)
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# define HSMCI_MR_PWSDIV_MAX (7 << HSMCI_MR_PWSDIV_SHIFT)
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#define HSMCI_MR_RDPROOF (1 << 11) /* Bit 11: Read Proof Enable */
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#define HSMCI_MR_WRPROOF (1 << 12) /* Bit 12: Write Proof Enable */
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#define HSMCI_MR_FBYTE (1 << 13) /* Bit 13: Force Byte Transfer */
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#define HSMCI_MR_PADV (1 << 14) /* Bit 14: Padding Value */
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#define HSMCI_MR_CLKODD (1 << 16) /* Bit 15: Clock divider is odd */
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/* HSMCI Data Timeout Register */
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||||
|
||||
#define HSMCI_DTOR_DTOCYC_SHIFT (0) /* Bits 0-3: Data Timeout Cycle Number */
|
||||
#define HSMCI_DTOR_DTOCYC_MASK (15 << HSMCI_DTOR_DTOCYC_SHIFT)
|
||||
# define HSMCI_DTOR_DTOCYC_MAX (15 << HSMCI_DTOR_DTOCYC_SHIFT)
|
||||
#define HSMCI_DTOR_DTOMUL_SHIFT (4) /* Bits 4-6: Data Timeout Multiplier */
|
||||
#define HSMCI_DTOR_DTOMUL_MASK (7 << HSMCI_DTOR_DTOMUL_SHIFT)
|
||||
# define HSMCI_DTOR_DTOMUL_1 (0 << HSMCI_DTOR_DTOMUL_SHIFT)
|
||||
# define HSMCI_DTOR_DTOMUL_16 (1 << HSMCI_DTOR_DTOMUL_SHIFT)
|
||||
# define HSMCI_DTOR_DTOMUL_128 (2 << HSMCI_DTOR_DTOMUL_SHIFT)
|
||||
# define HSMCI_DTOR_DTOMUL_256 (3 << HSMCI_DTOR_DTOMUL_SHIFT)
|
||||
# define HSMCI_DTOR_DTOMUL_1024 (4 << HSMCI_DTOR_DTOMUL_SHIFT)
|
||||
# define HSMCI_DTOR_DTOMUL_4096 (5 << HSMCI_DTOR_DTOMUL_SHIFT)
|
||||
# define HSMCI_DTOR_DTOMUL_65536 (6 << HSMCI_DTOR_DTOMUL_SHIFT)
|
||||
# define HSMCI_DTOR_DTOMUL_1048576 (7 << HSMCI_DTOR_DTOMUL_SHIFT)
|
||||
# define HSMCI_DTOR_DTOMUL_MAX (7 << HSMCI_DTOR_DTOMUL_SHIFT)
|
||||
|
||||
/* HSMCI SDCard/SDIO Register */
|
||||
|
||||
#define HSMCI_SDCR_SDCSEL_SHIFT (0) /* Bits 0-1: SDCard/SDIO Slot */
|
||||
#define HSMCI_SDCR_SDCSEL_MASK (3 << HSMCI_SDCR_SDCSEL_SHIFT) /* Slot A is selected */
|
||||
# define HSMCI_SDCR_SDCSEL_SLOTA (0 << HSMCI_SDCR_SDCSEL_SHIFT) /* Reserved */
|
||||
# define HSMCI_SDCR_SDCSEL_SLOTB (1 << HSMCI_SDCR_SDCSEL_SHIFT) /* Reserved */
|
||||
# define HSMCI_SDCR_SDCSEL_SLOTC (2 << HSMCI_SDCR_SDCSEL_SHIFT) /* Reserved */
|
||||
# define HSMCI_SDCR_SDCSEL_SLOTD (3 << HSMCI_SDCR_SDCSEL_SHIFT) /* Reserved */
|
||||
#define HSMCI_SDCR_SDCBUS_SHIFT (6) /* Bits 6-7: SDCard/SDIO Bus Width */
|
||||
#define HSMCI_SDCR_SDCBUS_MASK (3 << HSMCI_SDCR_SDCBUS_SHIFT)
|
||||
# define HSMCI_SDCR_SDCBUS_1BIT (0 << HSMCI_SDCR_SDCBUS_SHIFT)
|
||||
# define HSMCI_SDCR_SDCBUS_4BIT (2 << HSMCI_SDCR_SDCBUS_SHIFT)
|
||||
# define HSMCI_SDCR_SDCBUS_8BIT (3 << HSMCI_SDCR_SDCBUS_SHIFT)
|
||||
|
||||
/* HSMCI Argument Register (32-bit value) */
|
||||
|
||||
/* HSMCI Command Register */
|
||||
|
||||
#define HSMCI_CMDR_CMDNB_SHIFT (0) /* Bits 0-5: Command Number */
|
||||
#define HSMCI_CMDR_CMDNB_MASK (63 << HSMCI_CMDR_CMDNB_SHIFT)
|
||||
#define HSMCI_CMDR_RSPTYP_SHIFT (6) /* Bits 6-7: Response Type */
|
||||
#define HSMCI_CMDR_RSPTYP_MASK (3 << HSMCI_CMDR_RSPTYP_SHIFT)
|
||||
# define HSMCI_CMDR_RSPTYP_NONE (0 << HSMCI_CMDR_RSPTYP_SHIFT) /* No response */
|
||||
# define HSMCI_CMDR_RSPTYP_48BIT (1 << HSMCI_CMDR_RSPTYP_SHIFT) /* 48-bit response */
|
||||
# define HSMCI_CMDR_RSPTYP_136BIT (2 << HSMCI_CMDR_RSPTYP_SHIFT) /* 136-bit response */
|
||||
# define HSMCI_CMDR_RSPTYP_R1B (3 << HSMCI_CMDR_RSPTYP_SHIFT) /* R1b response type */
|
||||
#define HSMCI_CMDR_SPCMD_SHIFT (8) /* Bits 8-10: Special Command */
|
||||
#define HSMCI_CMDR_SPCMD_MASK (7 << HSMCI_CMDR_SPCMD_SHIFT)
|
||||
# define HSMCI_CMDR_SPCMD_STD (0 << HSMCI_CMDR_SPCMD_SHIFT) /* Not a special CMD */
|
||||
# define HSMCI_CMDR_SPCMD_INIT (1 << HSMCI_CMDR_SPCMD_SHIFT) /* Initialization CMD */
|
||||
# define HSMCI_CMDR_SPCMD_SYNC (2 << HSMCI_CMDR_SPCMD_SHIFT) /* Synchronized CMD */
|
||||
# define HSMCI_CMDR_SPCMD_CEATA (3 << HSMCI_CMDR_SPCMD_SHIFT) /* CE-ATA Completion Signal disable CMD */
|
||||
# define HSMCI_CMDR_SPCMD_ITCMD (4 << HSMCI_CMDR_SPCMD_SHIFT) /* Interrupt command */
|
||||
# define HSMCI_CMDR_SPCMD_ITRESP (5 << HSMCI_CMDR_SPCMD_SHIFT) /* Interrupt response */
|
||||
# define HSMCI_CMDR_SPCMD_BOR (6 << HSMCI_CMDR_SPCMD_SHIFT) /* Boot Operation Request */
|
||||
# define HSMCI_CMDR_SPCMD_EBO (7 << HSMCI_CMDR_SPCMD_SHIFT) /* End Boot Operation */
|
||||
#define HSMCI_CMDR_OPDCMD (1 << 11) /* Bit 11: Open Drain Command */
|
||||
#define HSMCI_CMDR_MAXLAT (1 << 12) /* Bit 12: Max Latency for Command to Response */
|
||||
#define HSMCI_CMDR_TRCMD_SHIFT (16) /* Bits 16-17: Transfer Command */
|
||||
#define HSMCI_CMDR_TRCMD_MASK (3 << HSMCI_CMDR_TRCMD_SHIFT)
|
||||
# define HSMCI_CMDR_TRCMD_NONE (0 << HSMCI_CMDR_TRCMD_SHIFT) /* No data transfer */
|
||||
# define HSMCI_CMDR_TRCMD_START (1 << HSMCI_CMDR_TRCMD_SHIFT) /* Start data transfer */
|
||||
# define HSMCI_CMDR_TRCMD_STOP (2 << HSMCI_CMDR_TRCMD_SHIFT) /* Stop data transfer */
|
||||
#define HSMCI_CMDR_TRDIR (1 << 18) /* Bit 18: Transfer Direction */
|
||||
# define HSMCI_CMDR_TRDIR_WRITE (0 << 18)
|
||||
# define HSMCI_CMDR_TRDIR_READ (1 << 18)
|
||||
#define HSMCI_CMDR_TRTYP_SHIFT (19) /* Bits 19-21: Transfer Type */
|
||||
#define HSMCI_CMDR_TRTYP_MASK (7 << HSMCI_CMDR_TRTYP_SHIFT)
|
||||
# define HSMCI_CMDR_TRTYP_SINGLE (0 << HSMCI_CMDR_TRTYP_SHIFT) /* MMC/SDCard Single Block */
|
||||
# define HSMCI_CMDR_TRTYP_MULTIPLE (1 << HSMCI_CMDR_TRTYP_SHIFT) /* MMC/SDCard Multiple Block */
|
||||
# define HSMCI_CMDR_TRTYP_STREAM (2 << HSMCI_CMDR_TRTYP_SHIFT) /* MMC Stream */
|
||||
# define HSMCI_CMDR_TRTYP_SDIOBYTE (4 << HSMCI_CMDR_TRTYP_SHIFT) /* SDIO Byte */
|
||||
# define HSMCI_CMDR_TRTYP_SDIOBLK (5 << HSMCI_CMDR_TRTYP_SHIFT) /* SDIO Block */
|
||||
#define HSMCI_CMDR_IOSPCMD_SHIFT (24) /* Bits 24-25: SDIO Special Command */
|
||||
#define HSMCI_CMDR_IOSPCMD_MASK (3 << HSMCI_CMDR_IOSPCMD_SHIFT)
|
||||
# define HSMCI_CMDR_IOSPCMD_STD (0 << HSMCI_CMDR_IOSPCMD_SHIFT) /* Not an SDIO Special Command */
|
||||
# define HSMCI_CMDR_IOSPCMD_SUSPEND (1 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Suspend Command */
|
||||
# define HSMCI_CMDR_IOSPCMD_RESUME (2 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Resume Command */
|
||||
#define HSMCI_CMDR_ATACS (1 << 26) /* Bit 26: ATA with Command Completion Signal */
|
||||
#define HSMCI_CMDR_BOOTACK (1 << 27) /* Bit 27: Boot Operation Acknowledge */
|
||||
|
||||
/* HSMCI Block Register */
|
||||
|
||||
#define HSMCI_BLKR_BCNT_SHIFT (0) /* Bits 0-15: MMC/SDIO Block Count - SDIO Byte Count */
|
||||
#define HSMCI_BLKR_BCNT_MASK (0xffff << HSMCI_BLKR_BCNT_SHIFT)
|
||||
# define HSMCI_BLKR_BCNT(n) ((uint32_t)(n) << HSMCI_BLKR_BCNT_SHIFT)
|
||||
#define HSMCI_BLKR_BLKLEN_SHIFT (16) /* Bits 16-31: Data Block Length */
|
||||
#define HSMCI_BLKR_BLKLEN_MASK (0xffff << HSMCI_BLKR_BLKLEN_SHIFT)
|
||||
# define HSMCI_BLKR_BLKLEN(n) ((uint32_t)(n) << HSMCI_BLKR_BLKLEN_SHIFT)
|
||||
|
||||
/* HSMCI Completion Signal Timeout Register */
|
||||
|
||||
#define HSMCI_CSTOR_CSTOCYC_SHIFT (0) /* Bits 0-3: Completion Signal Timeout Cycle Number */
|
||||
#define HSMCI_CSTOR_CSTOCYC_MASK (15 << HSMCI_CSTOR_CSTOCYC_SHIFT)
|
||||
# define HSMCI_CSTOR_CSTOCYC(n) ((uint32_t)(n) << HSMCI_CSTOR_CSTOCYC_SHIFT)
|
||||
#define HSMCI_CSTOR_CSTOMUL_SHIFT (4) /* Bits 4-6: Completion Signal Timeout Multiplier */
|
||||
#define HSMCI_CSTOR_CSTOMUL_MASK (7 << HSMCI_CSTOR_CSTOMUL_SHIFT)
|
||||
# define HSMCI_CSTOR_CSTOMUL_1 (0 << HSMCI_CSTOR_CSTOMUL_SHIFT)
|
||||
# define HSMCI_CSTOR_CSTOMUL_16 (1 << HSMCI_CSTOR_CSTOMUL_SHIFT)
|
||||
# define HSMCI_CSTOR_CSTOMUL_128 (2 << HSMCI_CSTOR_CSTOMUL_SHIFT)
|
||||
# define HSMCI_CSTOR_CSTOMUL_256 (3 << HSMCI_CSTOR_CSTOMUL_SHIFT)
|
||||
# define HSMCI_CSTOR_CSTOMUL_1024 (4 << HSMCI_CSTOR_CSTOMUL_SHIFT)
|
||||
# define HSMCI_CSTOR_CSTOMUL_4096 (5 << HSMCI_CSTOR_CSTOMUL_SHIFT)
|
||||
# define HSMCI_CSTOR_CSTOMUL_65536 (6 << HSMCI_CSTOR_CSTOMUL_SHIFT)
|
||||
# define HSMCI_CSTOR_CSTOMUL_1048576 (7 << HSMCI_CSTOR_CSTOMUL_SHIFT)
|
||||
|
||||
/* HSMCI Response Registers (32-bit data) */
|
||||
/* HSMCI Receive Data Registers (32-bit data) */
|
||||
/* HSMCI Transmit Data Registers (32-bit data) */
|
||||
|
||||
/* HSMCI Status Register, HSMCI Interrupt Enable Register, HSMCI Interrupt Disable
|
||||
* Register, and HSMCI Interrupt Mask Register common bit-field definitions
|
||||
*/
|
||||
|
||||
#define HSMCI_INT_CMDRDY (1 << 0) /* Bit 0: Command Ready */
|
||||
#define HSMCI_INT_RXRDY (1 << 1) /* Bit 1: Receiver Ready */
|
||||
#define HSMCI_INT_TXRDY (1 << 2) /* Bit 2: Transmit Ready */
|
||||
#define HSMCI_INT_BLKE (1 << 3) /* Bit 3: Data Block Ended */
|
||||
#define HSMCI_INT_DTIP (1 << 4) /* Bit 4: Data Transfer in Progress */
|
||||
#define HSMCI_INT_NOTBUSY (1 << 5) /* Bit 6: HSMCI Not Busy */
|
||||
#define HSMCI_INT_SDIOIRQA (1 << 8) /* Bit 8: SDIO Interrupt for Slot A */
|
||||
#define HSMCI_INT_SDIOWAIT (1 << 12) /* Bit 12: SDIO Read Wait Operation Status */
|
||||
#define HSMCI_INT_CSRCV (1 << 13) /* Bit 13: CE-ATA Completion Signal Received */
|
||||
#define HSMCI_INT_RINDE (1 << 16) /* Bit 16: Response Index Error */
|
||||
#define HSMCI_INT_RDIRE (1 << 17) /* Bit 17: Response Direction Error */
|
||||
#define HSMCI_INT_RCRCE (1 << 18) /* Bit 18: Response CRC Error */
|
||||
#define HSMCI_INT_RENDE (1 << 19) /* Bit 19: Response End Bit Error */
|
||||
#define HSMCI_INT_RTOE (1 << 20) /* Bit 20: Response Time-out */
|
||||
#define HSMCI_INT_DCRCE (1 << 21) /* Bit 21: Data CRC Error */
|
||||
#define HSMCI_INT_DTOE (1 << 22) /* Bit 22: Data Time-out Error */
|
||||
#define HSMCI_INT_CSTOE (1 << 23) /* Bit 23: Completion Signal Time-out Error */
|
||||
#define HSMCI_INT_BLKOVRE (1 << 24) /* Bit 24: DMA Block Overrun Error */
|
||||
#define HSMCI_INT_FIFOEMPTY (1 << 26) /* Bit 26: FIFO empty flag */
|
||||
#define HSMCI_INT_XFRDONE (1 << 27) /* Bit 27: Transfer Done flag */
|
||||
#define HSMCI_INT_ACKRCV (1 << 28) /* Bit 28: Boot Operation Acknowledge Received */
|
||||
#define HSMCI_INT_ACKRCVE (1 << 29) /* Bit 29: Boot Operation Acknowledge Error */
|
||||
#define HSMCI_INT_OVRE (1 << 30) /* Bit 30: Overrun */
|
||||
#define HSMCI_INT_UNRE (1 << 31) /* Bit 31: Underrun */
|
||||
|
||||
/* HSMCI DMA Configuration Register */
|
||||
|
||||
#define HSMCI_DMA_CHKSIZE_SHIFT (4) /* Bits 4-6: DMA Channel Read and Write Chunk Size */
|
||||
#define HSMCI_DMA_CHKSIZE_MASK (7 << HSMCI_DMA_CHKSIZE_SHIFT)
|
||||
# define HSMCI_DMA_CHKSIZE_1 (0 << HSMCI_DMA_CHKSIZE_SHIFT) /* 1 data available */
|
||||
# define HSMCI_DMA_CHKSIZE_4 (1 << HSMCI_DMA_CHKSIZE_SHIFT) /* 4 data available */
|
||||
# define HSMCI_DMA_CHKSIZE_8 (2 << HSMCI_DMA_CHKSIZE_SHIFT) /* 8 data available */
|
||||
# define HSMCI_DMA_CHKSIZE_16 (3 << HSMCI_DMA_CHKSIZE_SHIFT) /* 16 data available */
|
||||
# define HSMCI_DMA_CHKSIZE_32 (4 << HSMCI_DMA_CHKSIZE_SHIFT) /* 32 data available */
|
||||
#define HSMCI_DMA_DMAEN (1 << 8) /* Bit 8: DMA Hardware Handshaking Enable */
|
||||
|
||||
/* HSMCI Configuration Register */
|
||||
|
||||
#define HSMCI_CFG_FIFOMODE (1 << 0) /* Bit 0: HSMCI Internal FIFO control mode */
|
||||
#define HSMCI_CFG_FERRCTRL (1 << 4) /* Bit 4: Flow Error flag reset control mode */
|
||||
#define HSMCI_CFG_HSMODE (1 << 8) /* Bit 8: High Speed Mode */
|
||||
#define HSMCI_CFG_LSYNC (1 << 12) /* Bit 12: Synchronize on the last block */
|
||||
|
||||
/* HSMCI Write Protect Mode Register */
|
||||
|
||||
#define HSMCI_WPMR_WPEN (1 << 0) /* Bit 0: Write Protection Enable */
|
||||
#define HSMCI_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protection Key password */
|
||||
#define HSMCI_WPMR_WPKEY_MASK (0x00ffffff << HSMCI_WPMR_WPKEY_SHIFT)
|
||||
# define HSMCI_WPMR_WPKEY (0x004d4349 << HSMCI_WPMR_WPKEY_SHIFT)
|
||||
|
||||
/* HSMCI Write Protect Status Register */
|
||||
|
||||
#define HSMCI_WPSR_WPVS (1 << 0) /* Bit 0: Write Protection Violation Status */
|
||||
#define HSMCI_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */
|
||||
#define HSMCI_WPSR_WPVSRC_MASK (0xffff << HSMCI_WPSR_WPVSRC_SHIFT)
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************************/
|
||||
|
||||
#endif /* SAMV7_NHSMCI4 > 0 */
|
||||
#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_HSMCI_H */
|
||||
@ -72,7 +72,7 @@
|
||||
/* 0x20c00000-0x3fffffff: Reserved */
|
||||
/* Peripherals address region */
|
||||
|
||||
#define SAM_HSMCI_BASE 0x40000000 /* 0x40000000-0x40003fff: High Speed Multimedia Card Interface */
|
||||
#define SAM_HSMCI0_BASE 0x40000000 /* 0x40000000-0x40003fff: High Speed Multimedia Card Interface */
|
||||
#define SAM_SSC0_BASE 0x40004000 /* 0x40004000-0x40007fff: Serial Synchronous Controller */
|
||||
#define SAM_SPI0_BASE 0x40008000 /* 0x40008000-0x4000bfff: Serial Peripheral Interface 0 */
|
||||
#define SAM_TC012_BASE 0x4000c000 /* 0x4000c000-0x4000ffff: Timer Counters 0-2 */
|
||||
|
||||
@ -210,12 +210,12 @@
|
||||
|
||||
/* High-Speed Multimedia Card Interface (HSMCI) */
|
||||
|
||||
#define GPIO_HSMCI_CK (GPIO_PERIPHD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN25)
|
||||
#define GPIO_HSMCI_DA (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN28)
|
||||
#define GPIO_HSMCI_DA0 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN30)
|
||||
#define GPIO_HSMCI_DA1 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN31)
|
||||
#define GPIO_HSMCI_DA2 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN26)
|
||||
#define GPIO_HSMCI_DA3 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN27)
|
||||
#define GPIO_MCI0_CK (GPIO_PERIPHD | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN25)
|
||||
#define GPIO_MCI0_CDA (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN28)
|
||||
#define GPIO_MCI0_DA0 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN30)
|
||||
#define GPIO_MCI0_DA1 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN31)
|
||||
#define GPIO_MCI0_DA2 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN26)
|
||||
#define GPIO_MCI0_DA3 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN27)
|
||||
|
||||
/* MediaLB Interface (MLB) */
|
||||
|
||||
|
||||
3312
arch/arm/src/samv7/sam_hsmci.c
Normal file
3312
arch/arm/src/samv7/sam_hsmci.c
Normal file
File diff suppressed because it is too large
Load Diff
175
arch/arm/src/samv7/sam_hsmci.h
Normal file
175
arch/arm/src/samv7/sam_hsmci.h
Normal file
@ -0,0 +1,175 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/samv7/sam_hsmci.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAMV7_SAM_HSMCI_H
|
||||
#define __ARCH_ARM_SRC_SAMV7_SAM_HSMCI_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sdio_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize SDIO for operation.
|
||||
*
|
||||
* Input Parameters:
|
||||
* slotno - Not used.
|
||||
*
|
||||
* Returned Values:
|
||||
* A reference to an SDIO interface structure. NULL is returned on failures.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
struct sdio_dev_s; /* See include/nuttx/sdio.h */
|
||||
FAR struct sdio_dev_s *sdio_initialize(int slotno);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_hsmci_clkdiv
|
||||
*
|
||||
* Description:
|
||||
* Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)
|
||||
* divided by (2*(CLKDIV) + CLOCKODD + 2).
|
||||
*
|
||||
* CLKFULLDIV = 2*CLKDIV + CLOCKODD;
|
||||
* MCI_SPEED = MCK / (CLKFULLDIV + 2)
|
||||
* CLKFULLDIV = MCK / MCI_SPEED - 2
|
||||
*
|
||||
* CLKDIV = CLKFULLDIV >> 1
|
||||
* CLOCKODD = CLKFULLDIV & 1
|
||||
*
|
||||
* Where CLKDIV has a range of 0-255.
|
||||
*
|
||||
* NOTE: The primary use of this function is for cases where the clock
|
||||
* frequencies are not known a priori and so HSMCI clock dividers must
|
||||
* be determined dynamically. This is the case, for example, when we
|
||||
* execute out of SDRAM. In that case, the clocking was set up by the
|
||||
* bootloader that brought us into SDRAM and it is that bootloader that
|
||||
* has configured the clocking.
|
||||
*
|
||||
* Input parameters:
|
||||
* target - The target SD frequency
|
||||
*
|
||||
* Returned Value:
|
||||
* A bitset containing the CLKDIV and CLKODD bits as needed to configure
|
||||
* the HSMCI clock output.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t sam_hsmci_clkdiv(uint32_t target);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sdio_mediachange
|
||||
*
|
||||
* Description:
|
||||
* Called by board-specific logic -- possibly from an interrupt handler --
|
||||
* in order to signal to the driver that a card has been inserted or
|
||||
* removed from the slot
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - An instance of the SDIO driver device state structure.
|
||||
* cardinslot - true is a card has been detected in the slot; false if a
|
||||
* card has been removed from the slot. Only transitions
|
||||
* (inserted->removed or removed->inserted should be reported)
|
||||
*
|
||||
* Returned Values:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sdio_wrprotect
|
||||
*
|
||||
* Description:
|
||||
* Called by board-specific logic to report if the card in the slot is
|
||||
* mechanically write protected.
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - An instance of the SDIO driver device state structure.
|
||||
* wrprotect - true is a card is writeprotected.
|
||||
*
|
||||
* Returned Values:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_SAMV7_SAM_HSMCI_H */
|
||||
140
arch/arm/src/samv7/sam_hsmci_clkdiv.c
Executable file
140
arch/arm/src/samv7/sam_hsmci_clkdiv.c
Executable file
@ -0,0 +1,140 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/samv7/sam_pmc.c
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* References:
|
||||
*
|
||||
* SAMV7D3 Series Data Sheet
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may
|
||||
* be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/sam_hsmci.h"
|
||||
#include "sam_hsmci.h"
|
||||
|
||||
#ifdef CONFIG_SAMV7_HSMCI0
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_hsmci_clkdiv
|
||||
*
|
||||
* Description:
|
||||
* Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)
|
||||
* divided by (2*(CLKDIV) + CLOCKODD + 2).
|
||||
*
|
||||
* CLKFULLDIV = 2*CLKDIV + CLOCKODD;
|
||||
* MCI_SPEED = MCK / (CLKFULLDIV + 2)
|
||||
* CLKFULLDIV = MCK / MCI_SPEED - 2
|
||||
*
|
||||
* CLKDIV = CLKFULLDIV >> 1
|
||||
* CLOCKODD = CLKFULLDIV & 1
|
||||
*
|
||||
* Where CLKDIV has a range of 0-255.
|
||||
*
|
||||
* NOTE: The primary use of this function is for cases where the clock
|
||||
* frequencies are not known a priori and so HSMCI clock dividers must
|
||||
* be determined dynamically. This is the case, for example, when we
|
||||
* execute out of SDRAM. In that case, the clocking was set up by the
|
||||
* bootloader that brought us into SDRAM and it is that bootloader that
|
||||
* has configured the clocking.
|
||||
*
|
||||
* Input parameters:
|
||||
* target - The target SD frequency
|
||||
*
|
||||
* Returned Value:
|
||||
* A bitset containing the CLKDIV and CLKODD bits as needed to configure
|
||||
* the HSMCI clock output.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t sam_hsmci_clkdiv(uint32_t target)
|
||||
{
|
||||
uint32_t clkfulldiv;
|
||||
uint32_t ret;
|
||||
|
||||
/* Get the largest divisor does not exceed the target value */
|
||||
|
||||
clkfulldiv = (BOARD_MCK_FREQUENCY + target - 1) / target;
|
||||
|
||||
if (clkfulldiv > 2)
|
||||
{
|
||||
clkfulldiv -= 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
clkfulldiv = 0;
|
||||
}
|
||||
|
||||
if (clkfulldiv > 511)
|
||||
{
|
||||
clkfulldiv = 511;
|
||||
}
|
||||
|
||||
ret = (clkfulldiv >> 1) << HSMCI_MR_CLKDIV_SHIFT;
|
||||
if ((clkfulldiv & 1) != 0)
|
||||
{
|
||||
ret |= HSMCI_MR_CLKODD;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_SAMV7_HSMCI */
|
||||
@ -324,18 +324,12 @@
|
||||
#define SSC_CLKOUT_CONT 1 /* Continuous */
|
||||
#define SSC_CLKOUT_XFER 2 /* Only output clock during transfers */
|
||||
|
||||
/* Bus configuration may differ with chip */
|
||||
|
||||
#warning REVISIT
|
||||
/* System Bus Interfaces
|
||||
*
|
||||
* Both SSC0 and SSC1 are APB1. Both are accessible on MATRIX IF1.
|
||||
*
|
||||
* Memory is available on either port 5 (IF0 for both XDMAC0 and 1) or
|
||||
* port 6 (IF1 for both XDMAC0 and 1).
|
||||
* REVISIT: I believe that the SAMV1 has only a single APB.
|
||||
*/
|
||||
|
||||
#define DMACH_FLAG_PERIPH_IF DMACH_FLAG_PERIPHAHB_AHB_IF1
|
||||
#warning REVISIT
|
||||
#define DMACH_FLAG_PERIPH_IF DMACH_FLAG_PERIPHAHB_AHB_IF0
|
||||
#define DMACH_FLAG_MEM_IF DMACH_FLAG_MEMAHB_AHB_IF0
|
||||
|
||||
/* DMA configuration */
|
||||
@ -372,7 +366,7 @@
|
||||
#define DMA_TIMEOUT_TICKS MSEC2TICK(DMA_TIMEOUT_MS)
|
||||
|
||||
/* Debug *******************************************************************/
|
||||
/* Check if SSC debut is enabled (non-standard.. no support in
|
||||
/* Check if SSC debug is enabled (non-standard.. no support in
|
||||
* include/debug.h
|
||||
*/
|
||||
|
||||
|
||||
@ -159,7 +159,7 @@ static const uint32_t g_chanwidth[3] =
|
||||
|
||||
static const struct sam_pidmap_s g_xdmac_rxchan[] =
|
||||
{
|
||||
{ SAM_PID_HSMCI, XDMACH_HSMCI }, /* HSMCI Receive/Transmit */
|
||||
{ SAM_PID_HSMCI0, XDMACH_HSMCI }, /* HSMCI Receive/Transmit */
|
||||
{ SAM_PID_SPI0, XDMACH_SPI0_RX }, /* SPI0 Receive */
|
||||
{ SAM_PID_SPI1, XDMACH_SPI1_RX }, /* SPI1 Receive */
|
||||
{ SAM_PID_QSPI, XDMACH_QSPI_RX }, /* QSPI Receive */
|
||||
@ -190,7 +190,7 @@ static const struct sam_pidmap_s g_xdmac_rxchan[] =
|
||||
|
||||
static const struct sam_pidmap_s g_xdmac_txchan[] =
|
||||
{
|
||||
{ SAM_PID_HSMCI, XDMACH_HSMCI }, /* HSMCI Receive/Transmit */
|
||||
{ SAM_PID_HSMCI0, XDMACH_HSMCI }, /* HSMCI Receive/Transmit */
|
||||
{ SAM_PID_SPI0, XDMACH_SPI0_TX }, /* SPI0 Transmit */
|
||||
{ SAM_PID_SPI1, XDMACH_SPI1_TX }, /* SPI1 Transmit */
|
||||
{ SAM_PID_QSPI, XDMACH_QSPI_TX }, /* QSPI Transmit */
|
||||
|
||||
@ -74,7 +74,7 @@
|
||||
#define sam_usart2_enableclk() sam_enableperiph0(SAM_PID_USART2)
|
||||
#define sam_piod_enableclk() sam_enableperiph0(SAM_PID_PIOD)
|
||||
#define sam_pioe_enableclk() sam_enableperiph0(SAM_PID_PIOE)
|
||||
#define sam_hsmci_enableclk() sam_enableperiph0(SAM_PID_HSMCI)
|
||||
#define sam_hsmci0_enableclk() sam_enableperiph0(SAM_PID_HSMCI0)
|
||||
#define sam_twihs0_enableclk() sam_enableperiph0(SAM_PID_TWIHS0)
|
||||
#define sam_twihs1_enableclk() sam_enableperiph0(SAM_PID_TWIHS1)
|
||||
#define sam_spi0_enableclk() sam_enableperiph0(SAM_PID_SPI0)
|
||||
@ -142,7 +142,7 @@
|
||||
#define sam_usart2_disableclk() sam_disableperiph0(SAM_PID_USART2)
|
||||
#define sam_piod_disableclk() sam_disableperiph0(SAM_PID_PIOD)
|
||||
#define sam_pioe_disableclk() sam_disableperiph0(SAM_PID_PIOE)
|
||||
#define sam_hsmci_disableclk() sam_disableperiph0(SAM_PID_HSMCI)
|
||||
#define sam_hsmci0_disableclk() sam_disableperiph0(SAM_PID_HSMCI0)
|
||||
#define sam_twihs0_disableclk() sam_disableperiph0(SAM_PID_TWIHS0)
|
||||
#define sam_twihs1_disableclk() sam_disableperiph0(SAM_PID_TWIHS1)
|
||||
#define sam_spi0_disableclk() sam_disableperiph0(SAM_PID_SPI0)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user