diff --git a/arch/arm/src/tiva/cc13xx/cc13x0_trim.c b/arch/arm/src/tiva/cc13xx/cc13x0_trim.c index b7e341694f..702413acbd 100644 --- a/arch/arm/src/tiva/cc13xx/cc13x0_trim.c +++ b/arch/arm/src/tiva/cc13xx/cc13x0_trim.c @@ -49,6 +49,7 @@ #include "hardware/tiva_adi3_refsys.h" #include "hardware/tiva_aon_ioc.h" #include "hardware/tiva_aon_sysctl.h" +#include "hardware/tiva_aon_wuc.h" #include "hardware/tiva_ccfg.h" #include "hardware/tiva_fcfg1.h" #include "hardware/tiva_flash.h" @@ -95,7 +96,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision) { uint32_t ccfg_modeconf; uint32_t mp1rev; - uing32_t regval; + uint32_t regval; /* Force AUX on and enable clocks No need to save the current status of the * power/clock registers. At this point both AUX and AON should have been @@ -113,7 +114,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision) /* Enable the clocks for AUX_DDI0_OSC and AUX_ADI4 */ putreg32(AUX_WUC_MODCLKEN0_AUX_DDI0_OSC | AUX_WUC_MODCLKEN0_AUX_ADI4, - TIVA_AON_WUC_MODCLKEN0); + TIVA_AUX_WUC_MODCLKEN0); /* Check in CCFG for alternative DCDC setting */ @@ -168,9 +169,9 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision) * cc26x0 */ - mp1rev = - ((getreg32(TIVA_FCFG1_TRIM_CAL_REVISION) & - FCFG1_TRIM_CAL_REVISION_MP1_M) >> FCFG1_TRIM_CAL_REVISION_MP1_SHIFT); + mp1rev = ((getreg32(TIVA_FCFG1_TRIM_CAL_REVISION) & + FCFG1_TRIM_CAL_REVISION_MP1_MASK) >> + FCFG1_TRIM_CAL_REVISION_MP1_SHIFT); if (mp1rev < 542) { uint32_t ldoTrimReg = getreg32(TIVA_FCFG1_BAT_RC_LDO_TRIM); @@ -180,12 +181,12 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision) /* bit[27:24] unsigned */ - vtrim_bod = ((ldoTrimReg & FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_M) >> + vtrim_bod = ((ldoTrimReg & FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_MASK) >> FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_SHIFT); /* bit[19:16] signed but treated as unsigned */ - vtrim_udig = ((ldoTrimReg & FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_M) >> + vtrim_udig = ((ldoTrimReg & FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_MASK) >> FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_SHIFT); if (vtrim_bod > 0) @@ -207,7 +208,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision) regval8 = (vtrim_udig << ADI2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_SHIFT) | (vtrim_bod << ADI2_REFSYS_SOCLDOCTL0_VTRIM_BOD_SHIFT); - putreg8(regval, TIVA_ADI2_REFSYS_SOCLDOCTL0); + putreg8(regval8, TIVA_ADI2_REFSYS_SOCLDOCTL0); } /* Third part of trim done after cold reset and wakeup from shutdown: @@ -228,7 +229,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision) * AUX_ADI4 */ - putreg32(AUX_WUC_MODCLKEN0_AUX_DDI0_OSC, TIVA_AON_WUC_MODCLKEN0); + putreg32(AUX_WUC_MODCLKEN0_AUX_DDI0_OSC, TIVA_AUX_WUC_MODCLKEN0); /* Disable EFUSE clock */ diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi2_refsys.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi2_refsys.h index 4ef40be8a3..6aa143d920 100644 --- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi2_refsys.h +++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi2_refsys.h @@ -47,6 +47,7 @@ #include #include "hardware/tiva_memorymap.h" +#include "hardware/tiva_ddi.h" /******************************************************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi3_refsys.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi3_refsys.h index e4fe23b7a4..075f039347 100644 --- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi3_refsys.h +++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi3_refsys.h @@ -47,6 +47,7 @@ #include #include "hardware/tiva_memorymap.h" +#include "hardware/tiva_ddi.h" /******************************************************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi4_aux.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi4_aux.h index 3b9b4291fa..e0a89ee53e 100644 --- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi4_aux.h +++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi4_aux.h @@ -47,6 +47,7 @@ #include #include "hardware/tiva_memorymap.h" +#include "hardware/tiva_ddi.h" /******************************************************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_sysctl.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_sysctl.h index d16fc03c3a..dc1c46c9ad 100644 --- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_sysctl.h +++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_sysctl.h @@ -1,5 +1,5 @@ /******************************************************************************************************************** - * arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi2_refsys.h + * arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_sysctl.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_wuc.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_wuc.h new file mode 100644 index 0000000000..93db51375f --- /dev/null +++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_wuc.h @@ -0,0 +1,221 @@ +/******************************************************************************************************************** + * arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_wuc.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * + * Technical content derives from a TI header file that has a compatible BSD license: + * + * Copyright (c) 2015-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AON_WUC_H +#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AON_WUC_H + +/******************************************************************************************************************** + * Included Files + ********************************************************************************************************************/ + +#include +#include "hardware/tiva_memorymap.h" + +/******************************************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************************************/ + +/* AON SYSCTL Register Offsets **************************************************************************************/ + +#define TIVA_AON_WUC_MCUCLK_OFFSET 0x0000 /* MCU Clock Management */ +#define TIVA_AON_WUC_AUXCLK_OFFSET 0x0004 /* AUX Clock Management */ +#define TIVA_AON_WUC_MCUCFG_OFFSET 0x0008 /* MCU Configuration */ +#define TIVA_AON_WUC_AUXCFG_OFFSET 0x000c /* AUX Configuration */ +#define TIVA_AON_WUC_AUXCTL_OFFSET 0x0010 /* AUX Control */ +#define TIVA_AON_WUC_PWRSTAT_OFFSET 0x0014 /* Power Status */ +#define TIVA_AON_WUC_SHUTDOWN_OFFSET 0x0018 /* Shutdown Control */ +#define TIVA_AON_WUC_CTL0_OFFSET 0x0020 /* Control 0 */ +#define TIVA_AON_WUC_CTL1_OFFSET 0x0024 /* Control 1 */ +#define TIVA_AON_WUC_RECHARGECFG_OFFSET 0x0030 /* Recharge Controller Configuration */ +#define TIVA_AON_WUC_RECHARGESTAT_OFFSET 0x0034 /* Recharge Controller Status */ +#define TIVA_AON_WUC_OSCCFG_OFFSET 0x0038 /* Oscillator Configuration */ +#define TIVA_AON_WUC_JTAGCFG_OFFSET 0x0040 /* JTAG Configuration */ +#define TIVA_AON_WUC_JTAGUSERCODE_OFFSET 0x0044 /* JTAG USERCODE */ + +/* AON SYSCTL Register Addresses ************************************************************************************/ + +#define TIVA_AON_WUC_MCUCLK (TIVA_AON_WUC_BASE + TIVA_AON_WUC_MCUCLK_OFFSET) +#define TIVA_AON_WUC_AUXCLK (TIVA_AON_WUC_BASE + TIVA_AON_WUC_AUXCLK_OFFSET) +#define TIVA_AON_WUC_MCUCFG (TIVA_AON_WUC_BASE + TIVA_AON_WUC_MCUCFG_OFFSET) +#define TIVA_AON_WUC_AUXCFG (TIVA_AON_WUC_BASE + TIVA_AON_WUC_AUXCFG_OFFSET) +#define TIVA_AON_WUC_AUXCTL (TIVA_AON_WUC_BASE + TIVA_AON_WUC_AUXCTL_OFFSET) +#define TIVA_AON_WUC_PWRSTAT (TIVA_AON_WUC_BASE + TIVA_AON_WUC_PWRSTAT_OFFSET) +#define TIVA_AON_WUC_SHUTDOWN (TIVA_AON_WUC_BASE + TIVA_AON_WUC_SHUTDOWN_OFFSET) +#define TIVA_AON_WUC_CTL0 (TIVA_AON_WUC_BASE + TIVA_AON_WUC_CTL0_OFFSET) +#define TIVA_AON_WUC_CTL1 (TIVA_AON_WUC_BASE + TIVA_AON_WUC_CTL1_OFFSET) +#define TIVA_AON_WUC_RECHARGECFG (TIVA_AON_WUC_BASE + TIVA_AON_WUC_RECHARGECFG_OFFSET) +#define TIVA_AON_WUC_RECHARGESTAT (TIVA_AON_WUC_BASE + TIVA_AON_WUC_RECHARGESTAT_OFFSET) +#define TIVA_AON_WUC_OSCCFG (TIVA_AON_WUC_BASE + TIVA_AON_WUC_OSCCFG_OFFSET) +#define TIVA_AON_WUC_JTAGCFG (TIVA_AON_WUC_BASE + TIVA_AON_WUC_JTAGCFG_OFFSET) +#define TIVA_AON_WUC_JTAGUSERCODE (TIVA_AON_WUC_BASE + TIVA_AON_WUC_JTAGUSERCODE_OFFSET) + +/* AON SYSCTL Register Bitfield Definitions *************************************************************************/ + +/* AON_WUC_MCUCLK */ + +#define AON_WUC_MCUCLK_PWR_DWN_SRC_SHIFT (0) /* Bits 0-1: Clock source for MCU domain when request powerdown */ +#define AON_WUC_MCUCLK_PWR_DWN_SRC_MASK (3 << AON_WUC_MCUCLK_PWR_DWN_SRC_SHIFT) +# define AON_WUC_MCUCLK_PWR_DWN_SRC(n) ((uint32_t)(n) << AON_WUC_MCUCLK_PWR_DWN_SRC_SHIFT) +# define AON_WUC_MCUCLK_PWR_DWN_SRC_NONE (0 << AON_WUC_MCUCLK_PWR_DWN_SRC_SHIFT) +# define AON_WUC_MCUCLK_PWR_DWN_SRC_SCLK_LF (1 << AON_WUC_MCUCLK_PWR_DWN_SRC_SHIFT) +#define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE (1 << 2) /* Bit 2: RCOSC_HF is calibrated to 48 MHz */ + +/* AON_WUC_AUXCLK */ + +#define AON_WUC_AUXCLK_SRC_SHIFT (0) /* Bits 0-2: Clock source for AUX */ +#define AON_WUC_AUXCLK_SRC_MASK (7 << AON_WUC_AUXCLK_SRC_SHIFT) +# define AON_WUC_AUXCLK_SRC(n) ((uint32_t)(n) << AON_WUC_AUXCLK_SRC_SHIFT) +# define AON_WUC_AUXCLK_SRC_SCLK_HF (1 << AON_WUC_AUXCLK_SRC_SHIFT) +# define AON_WUC_AUXCLK_SRC_SCLK_LF (4 << AON_WUC_AUXCLK_SRC_SHIFT) +#define AON_WUC_AUXCLK_SCLK_HF_DIV_SHIFT (8) /* Bits 8-10: AUX clock divider for SCLK_HF */ +#define AON_WUC_AUXCLK_SCLK_HF_DIV_MASK (7 << AON_WUC_AUXCLK_SCLK_HF_DIV_SHIFT) +# define AON_WUC_AUXCLK_SCLK_HF_DIV(n) ((uint32_t)(n) << AON_WUC_AUXCLK_SCLK_HF_DIV_SHIFT) +# define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV2 (0 << AON_WUC_AUXCLK_SCLK_HF_DIV_SHIFT) +# define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV4 (1 << AON_WUC_AUXCLK_SCLK_HF_DIV_SHIFT) +# define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV8 (2 << AON_WUC_AUXCLK_SCLK_HF_DIV_SHIFT) +# define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV16 (3 << AON_WUC_AUXCLK_SCLK_HF_DIV_SHIFT) +# define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV32 (4 << AON_WUC_AUXCLK_SCLK_HF_DIV_SHIFT) +# define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV64 (5 << AON_WUC_AUXCLK_SCLK_HF_DIV_SHIFT) +# define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV128 (6 << AON_WUC_AUXCLK_SCLK_HF_DIV_SHIFT) +# define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV256 (7 << AON_WUC_AUXCLK_SCLK_HF_DIV_SHIFT) +#define AON_WUC_AUXCLK_PWR_DWN_SRC_SHIFT (11) /* Bits 11-12: Clock source during AUX power down */ +#define AON_WUC_AUXCLK_PWR_DWN_SRC_MASK (3 << AON_WUC_AUXCLK_PWR_DWN_SRC_SHIFT) +# define AON_WUC_AUXCLK_PWR_DWN_SRC(n) ((uint32_t)(n) << AON_WUC_AUXCLK_PWR_DWN_SRC_SHIFT) +# define AON_WUC_AUXCLK_PWR_DWN_SRC_NONE (0 << AON_WUC_AUXCLK_PWR_DWN_SRC_SHIFT) +# define AON_WUC_AUXCLK_PWR_DWN_SRC_SCLK_LF (1 << AON_WUC_AUXCLK_PWR_DWN_SRC_SHIFT) + +/* AON_WUC_MCUCFG */ + +#define AON_WUC_MCUCFG_SRAM_RET_EN_SHIFT (0) /* Bits 0-3: MCU SRAM banks with retention during MCU power off */ +#define AON_WUC_MCUCFG_SRAM_RET_EN_MASK (15 << AON_WUC_MCUCFG_SRAM_RET_EN_SHIFT) +# define AON_WUC_MCUCFG_SRAM_RET_EN(n) ((uint32_t)(n) << AON_WUC_MCUCFG_SRAM_RET_EN_SHIFT) +# define AON_WUC_MCUCFG_SRAM_RET_EN_RET_NONE (0 << AON_WUC_MCUCFG_SRAM_RET_EN_SHIFT) +# define AON_WUC_MCUCFG_SRAM_RET_EN_RET_LEVEL1 (1 << AON_WUC_MCUCFG_SRAM_RET_EN_SHIFT) +# define AON_WUC_MCUCFG_SRAM_RET_EN_RET_LEVEL2 (3 << AON_WUC_MCUCFG_SRAM_RET_EN_SHIFT) +# define AON_WUC_MCUCFG_SRAM_RET_EN_RET_LEVEL3 (7 << AON_WUC_MCUCFG_SRAM_RET_EN_SHIFT) +# define AON_WUC_MCUCFG_SRAM_RET_EN_RET_FULL (15 << AON_WUC_MCUCFG_SRAM_RET_EN_SHIFT) +#define AON_WUC_MCUCFG_FIXED_WU_EN (1 << 16) /* Bit 16 */ +#define AON_WUC_MCUCFG_VIRT_OFF (1 << 17) /* Bit 17 */ + +/* AON_WUC_AUXCFG */ + +#define AON_WUC_AUXCFG_RAM_RET_EN (1 << 0) /* Bit 0: Enables retention mode for AUX_RAM:BANK0 */ + +/* AON_WUC_AUXCTL */ + +#define AON_WUC_AUXCTL_AUX_FORCE_ON (1 << 0) /* Bit 0: Force the AUX domain into active mode */ +#define AON_WUC_AUXCTL_SWEV (1 << 1) /* Bit 1: Sets software event to AUX domain */ +#define AON_WUC_AUXCTL_SCE_RUN_EN (1 << 2) /* Bit 2: Enable AUX_SCE execution */ +#define AON_WUC_AUXCTL_RESET_REQ (1 << 31) /* Bit 31: Assert reset to AUX */ + +/* AON_WUC_PWRSTAT */ + +#define AON_WUC_SHUTDOWN_EN (1 << 0) /* Bit 0: Force shutdown request */ +#define AON_WUC_PWRSTAT_AUX_RESET_DONE (1 << 1) /* Bit 1: AUX reset done */ +#define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED (1 << 2) /* Bit 2: AUX bus is connected */ +#define AON_WUC_PWRSTAT_MCU_PD_ON (1 << 4) /* Bit 4: MCU power sequence finalized; MCU_AONIF reliable */ +#define AON_WUC_PWRSTAT_AUX_PD_ON (1 << 5) /* Bit 5: AUX powered on and connected to bus */ +#define AON_WUC_PWRSTAT_JTAG_PD_ON (1 << 6) /* Bit 6: JTAG is powered on */ +#define AON_WUC_PWRSTAT_AUX_PWR_DWN (1 << 9) /* Bit 9: AUX powerdown state when AUX domain is powered up */ + +/* AON_WUC_CTL0 */ + +#define AON_WUC_CTL0_MCU_SRAM_ERASE (1 << 2) /* Bit 2 */ +#define AON_WUC_CTL0_AUX_SRAM_ERASE (1 << 3) /* Bit 3 */ +#define AON_WUC_CTL0_PWR_DWN_DIS (1 << 8) /* Bit 8: MCU/AUX power off will enable powerdown */ + +/* AON_WUC_CTL1 */ + +#define AON_WUC_CTL1_MCU_WARM_RESET (1 << 0) /* Bit 0: Last MCU reset was a warm reset */ +#define AON_WUC_CTL1_MCU_RESET_SRC (1 << 1) /* Bit 1: Source of lst MCU Voltage Domain warm reset request */ +# define AON_WUC_CTL1_MCU_RESET_SRC_SWRESET (0) +# define AON_WUC_CTL1_MCU_RESET_SRC_JTAG AON_WUC_CTL1_MCU_RESET_SRC + +/* AON_WUC_RECHARGECFG */ + +#define AON_WUC_RECHARGECFG_PER_E_SHIFT (0) /* Bits 0-2: 32KHz clocks between activation of rechange + * controller (exponent) */ +#define AON_WUC_RECHARGECFG_PER_E_MASK (7 << AON_WUC_RECHARGECFG_PER_E_SHIFT) +# define AON_WUC_RECHARGECFG_PER_E(n) ((uint32_t)(n) << AON_WUC_RECHARGECFG_PER_E_SHIFT) +#define AON_WUC_RECHARGECFG_PER_M_SHIFT (3) /* Bits 3-7: 32KHz clocks between activation of rechange + * controller (mantissa) */ +#define AON_WUC_RECHARGECFG_PER_M_MASK (31 << AON_WUC_RECHARGECFG_PER_M_SHIFT) +# define AON_WUC_RECHARGECFG_PER_M(n) ((uint32_t)(n) << AON_WUC_RECHARGECFG_PER_M_SHIFT) +#define AON_WUC_RECHARGECFG_MAX_PER_E_SHIFT (8) /* Bits 8-10: Maximum recharge period exponent */ +#define AON_WUC_RECHARGECFG_MAX_PER_E_MASK (7 << AON_WUC_RECHARGECFG_MAX_PER_E_SHIFT) +# define AON_WUC_RECHARGECFG_MAX_PER_E(n) ((uint32_t)(n) << AON_WUC_RECHARGECFG_MAX_PER_E_SHIFT) +#define AON_WUC_RECHARGECFG_MAX_PER_M_SHIFT (11) /* Bits 11-15: Maximum recharge period (mantissa) */ +#define AON_WUC_RECHARGECFG_MAX_PER_M_MASK (31 << AON_WUC_RECHARGECFG_MAX_PER_M_SHIFT) +# define AON_WUC_RECHARGECFG_MAX_PER_M(n) ((uint32_t)(n) << AON_WUC_RECHARGECFG_MAX_PER_M_SHIFT) +#define AON_WUC_RECHARGECFG_C1_SHIFT (16) /* Bits 16-19: Gain factor for adaptive recharge algorithm */ +#define AON_WUC_RECHARGECFG_C1_MASK (15 << AON_WUC_RECHARGECFG_C1_SHIFT) +# define AON_WUC_RECHARGECFG_C1(n) ((uint32_t)(n) << AON_WUC_RECHARGECFG_C1_SHIFT) +#define AON_WUC_RECHARGECFG_C2_SHIFT (20) /* Bits 20-23: Gain factor for adaptive recharge algorithm */ +#define AON_WUC_RECHARGECFG_C2_MASK (15 << AON_WUC_RECHARGECFG_C2_SHIFT) +# define AON_WUC_RECHARGECFG_C2(n) ((uint32_t)(n) << AON_WUC_RECHARGECFG_C2_SHIFT) +#define AON_WUC_RECHARGECFG_ADAPTIVE_EN (1 << 31) /* Bit 31: Enable adaptive recharge */ + +/* AON_WUC_RECHARGESTAT */ + +#define AON_WUC_RECHARGESTAT_MAX_USED_PER_SHIFT (0) /* Bits 0-15: Maximum value of recharge period with VDDR > thres */ +#define AON_WUC_RECHARGESTAT_MAX_USED_PER_MASK (0xffff << AON_WUC_RECHARGESTAT_MAX_USED_PER_SHIFT) +# define AON_WUC_RECHARGESTAT_MAX_USED_PER(n) ((uint32_t)(n) << AON_WUC_RECHARGESTAT_MAX_USED_PER_SHIFT) +#define AON_WUC_RECHARGESTAT_VDDR_SMPLS_SHIFT (16) /* Bits 16-19: Last 4 VDDR samples, bit 0 = newest */ +#define AON_WUC_RECHARGESTAT_VDDR_SMPLS_MASK (15 << AON_WUC_RECHARGESTAT_VDDR_SMPLS_SHIFT) +# define AON_WUC_RECHARGESTAT_VDDR_SMPLS(n) ((uint32_t)(n) << AON_WUC_RECHARGESTAT_VDDR_SMPLS_SHIFT) + +/* AON_WUC_OSCCFG */ + +#define AON_WUC_OSCCFG_PER_E_SHIFT (0) /* Bits 0-2: 32KHz clocks between oscillator amplitude + * calibrations (exponent) */ +#define AON_WUC_OSCCFG_PER_E_MASK (7 << AON_WUC_OSCCFG_PER_E_SHIFT) +# define AON_WUC_OSCCFG_PER_E(n) ((uint32_t)(n) << AON_WUC_OSCCFG_PER_E_SHIFT) +#define AON_WUC_OSCCFG_PER_M_SHIFT (3) /* Bits 3-7: 32KHz clocks between oscillator amplitude + * calibrations (mantissa) */ +#define AON_WUC_OSCCFG_PER_M_MASK (31 << AON_WUC_OSCCFG_PER_M_SHIFT) +# define AON_WUC_OSCCFG_PER_M(n) ((uint32_t)(n) << AON_WUC_OSCCFG_PER_M_SHIFT) + +/* AON_WUC_JTAGCFG */ + +#define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON (1 << 8) /* Bit 8: Force JTAG Power Domain on */ + +/* AON_WUC_JTAGUSERCODE (32-bit User code) */ + +#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_HW_AON_WUC_H */ diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_fcfg1.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_fcfg1.h index de1a6e898a..d034769ef6 100644 --- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_fcfg1.h +++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_fcfg1.h @@ -880,7 +880,7 @@ degrees C */ /* TIVA_FCFG1_TRIM_CAL_REVISION */ -#define FCFG1_TRIM_CAL_REVISION_MP1_SHIFT (24) /* Bits 0-15 */ +#define FCFG1_TRIM_CAL_REVISION_MP1_SHIFT (0) /* Bits 0-15 */ #define FCFG1_TRIM_CAL_REVISION_MP1_MASK (0xffff << FCFG1_TRIM_CAL_REVISION_MP1_SHIFT) # define FCFG1_TRIM_CAL_REVISION_MP1(n) ((uint32_t)(n) << FCFG1_TRIM_CAL_REVISION_MP1_SHIFT) #define FCFG1_TRIM_CAL_REVISION_FT1_SHIFT (16) /* Bits 16-31 */ diff --git a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi2_refsys.h b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi2_refsys.h index 7657da6aee..aa1bad9300 100644 --- a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi2_refsys.h +++ b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi2_refsys.h @@ -47,6 +47,7 @@ #include #include "hardware/tiva_memorymap.h" +#include "hardware/tiva_ddi.h" /******************************************************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi3_refsys.h b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi3_refsys.h index c5fcf9b95c..02d2f86cb7 100644 --- a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi3_refsys.h +++ b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi3_refsys.h @@ -47,6 +47,7 @@ #include #include "hardware/tiva_memorymap.h" +#include "hardware/tiva_ddi.h" /******************************************************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi4_aux.h b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi4_aux.h index 0c985000cb..5aff19b0b0 100644 --- a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi4_aux.h +++ b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi4_aux.h @@ -47,6 +47,7 @@ #include #include "hardware/tiva_memorymap.h" +#include "hardware/tiva_ddi.h" /******************************************************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ddi0_osc.h b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ddi0_osc.h index ae04da1273..98c2cf68e5 100644 --- a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ddi0_osc.h +++ b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ddi0_osc.h @@ -46,8 +46,8 @@ ********************************************************************************************************************/ #include -#include "hardware/cc13x2_cc26x2/cc13x2_cc26x2_ddi.h" #include "hardware/tiva_memorymap.h" +#include "hardware/tiva_ddi.h" /******************************************************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/tiva/hardware/tiva_aon_wuc.h b/arch/arm/src/tiva/hardware/tiva_aon_wuc.h new file mode 100644 index 0000000000..bf65eee095 --- /dev/null +++ b/arch/arm/src/tiva/hardware/tiva_aon_wuc.h @@ -0,0 +1,72 @@ +/************************************************************************************ + * arch/arm/src/tiva/hardware/tiva_aon_wuc.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AON_WUC_H +#define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AON_WUC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink chip */ + +#if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C) || \ + defined(CONFIG_ARCH_CHIP_CC13X2) + /* These architectures do not support the AON WUC block */ +#elif defined(CONFIG_ARCH_CHIP_CC13X0) +# include "hardware/cc13x0/cc13x0_aon_wuc.h" +#else +# error "Unsupported Tiva/Stellaris/SimpleLink AON WUC" +#endif + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AON_WUC_H */ diff --git a/arch/arm/src/tiva/hardware/tiva_ddi.h b/arch/arm/src/tiva/hardware/tiva_ddi.h new file mode 100644 index 0000000000..e8b3a218fa --- /dev/null +++ b/arch/arm/src/tiva/hardware/tiva_ddi.h @@ -0,0 +1,73 @@ +/************************************************************************************ + * arch/arm/src/tiva/hardware/tiva_ddi.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_DDI_H +#define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_DDI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink chip */ + +#if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C) + /* These architectures do not support the DDI block */ +#elif defined(CONFIG_ARCH_CHIP_CC13X0) +# include "hardware/cc13x0/cc13x0_ddi.h" +#elif defined(CONFIG_ARCH_CHIP_CC13X2) +# include "hardware/cc13x2_cc26x2/cc13x2_cc26x2_ddi.h" +#else +# error "Unsupported Tiva/Stellaris/SimpleLink DDI" +#endif + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_DDI_H */