Adds a JTAG config and ERASE config to Kconfig to set the CCFG_SYSIO SYSIO Pins
• SYSIO4: PB4 or TDI Assignment 0: TDI function selected. 1: PB4 function selected. • SYSIO5: PB5 or TDO/TRACESWO Assignment 0: TDO/TRACESWO function selected. 1: PB5 function selected. • SYSIO6: PB6 or TMS/SWDIO Assignment 0: TMS/SWDIO function selected. 1: PB6 function selected. • SYSIO7: PB7 or TCK/SWCLK Assignment 0: TCK/SWCLK function selected. 1: PB7 function selected. • SYSIO12: PB12 or ERASE Assignment 0: ERASE function selected. 1: PB12 function selected. The thing I did not add is warning or compilation failure, (to save the next guy the hassle), at ALL the driver points that uses the these pins. I did remove this /* To use the USART1 as an USART, the SYSIO Pin4 must be bound to PB4 * instead of TDI */ uint32_t sysioreg = getreg32(SAM_MATRIX_CCFG_SYSIO); sysioreg |= MATRIX_CCFG_SYSIO_SYSIO4; putreg32(sysioreg, SAM_MATRIX_CCFG_SYSIO); in sam_lowputc.c in favor of an #error - because the default is an input TDI and driving it blindly to an output TXD1, would be a contention.
This commit is contained in:
David Sidrane
Gregory Nutt
parent
7f7d4e664c
commit
8fac871cc9
@ -549,6 +549,75 @@ config SAMV7_RSWDT
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endmenu # SAMV7 Peripheral Selection
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choice
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prompt "JTAG IO Configuration"
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default SAMV7_JTAG_FULL_ENABLE
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---help---
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JTAG Enable settings (by default the IO for JTAG-DP and SW-DP are
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enabled)
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config SAMV7_JTAG_DISABLE
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bool "Disable all JTAG IO"
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---help---
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JTAG Enable settings (by default the IO for JTAG-DP and SW-DP are
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enabled)
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When JTAG is disabled PB4-BP7 is assigned as a GPIO and can be
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configured for use as GPIO or a Peripheral
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config SAMV7_JTAG_FULL_ENABLE
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bool "Enable full JTAG IO to use JTAG-DP + SW-DP"
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---help---
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The JTAG IO is configured for both JTAG-DP + SW-DP"
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PB4 is TDI
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PB5 is TDO/TRACESWO
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PB6 is TMS/SWDIO
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PB7 is TCK/SWCLK
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config SAMV7_JTAG_FULL_SW_ENABLE
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bool "Set JTAG-DP IO disabled and Full SW-DP IO enabled"
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---help---
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JTAG IO is configured for SW-DP with Trace"
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PB5 is TDO/TRACESWO
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PB6 is TMS/SWDIO
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PB7 is TCK/SWCLK
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config SAMV7_JTAG_SW_ENABLE
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bool "Set JTAG-DP IO disabled and SW-DP IO enabled"
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---help---
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JTAG IO is configured for SW-DP without Trace "
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PB6 is TMS/SWDIO
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PB7 is TCK/SWCLK
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endchoice # JTAG IO Configuration
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choice
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prompt "ERASE Pin Configuration"
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default SAMV7_ERASE_ENABLE
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---help---
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ERASE Pin Enable settings (by default ERASE pin is enabled)
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config SAMV7_ERASE_DISABLE
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bool "Disable ERASE Pin"
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---help---
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ERASE Pin Enable settings (by default ERASE pin is enabled)
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When the ERASE pin is disabled PB12 is assigned as a GPIO and can be
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configured for use as GPIO or a Peripheral.
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N.B. a low level must be ensured at startup to prevent Flash erase before
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the user application sets PB12 into PIO mode,
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config SAMV7_ERASE_ENABLE
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bool "Enable ERASE Pin"
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---help---
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The ERASE pin is configured to reinitialize the Flash content.
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endchoice
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menuconfig SAMV7_GPIO_IRQ
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bool "GPIO pin interrupts"
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---help---
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@ -54,14 +54,30 @@
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#include "sam_gpio.h"
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#include "chip/sam_pio.h"
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#include "chip/sam_matrix.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Private Types
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****************************************************************************/
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#if !defined(CONFIG_SAMV7_ERASE_ENABLE) || \
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!defined(CONFIG_SAMV7_JTAG_FULL_ENABLE)
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# if defined(CONFIG_SAMV7_ERASE_DISABLE)
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# define SYSIO_ERASE_BIT MATRIX_CCFG_SYSIO_SYSIO12
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# else
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# define SYSIO_ERASE_BIT 0
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# endif
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# if defined(CONFIG_SAMV7_JTAG_DISABLE)
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# define SYSIO_BITS (MATRIX_CCFG_SYSIO_SYSIO4 | MATRIX_CCFG_SYSIO_SYSIO5 | \
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MATRIX_CCFG_SYSIO_SYSIO6 | MATRIX_CCFG_SYSIO_SYSIO7)
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# endif
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# if defined(CONFIG_SAMV7_JTAG_FULL_SW_ENABLE)
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# define SYSIO_BITS MATRIX_CCFG_SYSIO_SYSIO4
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# endif
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# if defined(CONFIG_SAMV7_JTAG_SW_ENABLE)
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# define SYSIO_BITS (MATRIX_CCFG_SYSIO_SYSIO4 | MATRIX_CCFG_SYSIO_SYSIO5)
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# endif
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#endif
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/****************************************************************************
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* Private Data
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@ -70,7 +86,7 @@
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#ifdef CONFIG_DEBUG_GPIO
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static const char g_portchar[SAMV7_NPIO] =
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{
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'A'
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'A'
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#if SAMV7_NPIO > 1
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, 'B'
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#endif
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@ -402,6 +418,33 @@ static inline int sam_configperiph(uintptr_t base, uint32_t pin,
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Function: sam_gpioinit
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*
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* Description:
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* Based on configuration within the .config file, it does:
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* - Configures the CCFG_SYSIO bits.
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*
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* Typically called from sam_start().
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*
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* Assumptions:
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* This function is called early in the initialization sequence so that
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* no mutual exlusion is necessary.
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*
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****************************************************************************/
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#if !defined(CONFIG_SAMV7_ERASE_ENABLE) || \
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!defined(CONFIG_SAMV7_JTAG_FULL_ENABLE)
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void sam_gpioinit(void)
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{
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uint32_t regval;
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regval = getreg32(SAM_MATRIX_CCFG_SYSIO);
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regval |= (SYSIO_ERASE_BIT | SYSIO_BITS);
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putreg32(regval, SAM_MATRIX_CCFG_SYSIO);
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}
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#endif
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/****************************************************************************
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* Name: sam_configgpio
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*
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@ -265,6 +265,24 @@ static inline int sam_gpio_pinmask(gpio_pinset_t cfgset)
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* Public Function Prototypes
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************************************************************************************/
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/************************************************************************************
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* Function: sam_gpioinit
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*
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* Description:
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* Based on configuration within the .config file, it does:
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* - Remaps positions of alternative functions for GPIO.
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*
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* Typically called from sam_start().
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*
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************************************************************************************/
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#if !defined(CONFIG_SAMV7_ERASE_ENABLE) || \
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!defined(CONFIG_SAMV7_JTAG_FULL_ENABLE)
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void sam_gpioinit(void);
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#else
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# define sam_gpioinit()
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#endif
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/************************************************************************************
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* Name: sam_gpioirqinitialize
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*
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@ -1,7 +1,7 @@
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/****************************************************************************
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* arch/arm/src/samv7/sam_lowputc.c
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -348,19 +348,20 @@ void sam_lowsetup(void)
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#ifdef CONFIG_SAMV7_USART1
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(void)sam_configgpio(GPIO_USART1_RXD);
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(void)sam_configgpio(GPIO_USART1_TXD);
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#ifdef CONFIG_USART1_OFLOWCONTROL
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# ifdef CONFIG_USART1_OFLOWCONTROL
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(void)sam_configgpio(GPIO_USART1_CTS);
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#endif
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#ifdef CONFIG_USART1_IFLOWCONTROL
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# endif
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# ifdef CONFIG_USART1_IFLOWCONTROL
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(void)sam_configgpio(GPIO_USART1_RTS);
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#endif
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# endif
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/* To use the USART1 as an USART, the SYSIO Pin4 must be bound to PB4
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* instead of TDI
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*/
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uint32_t sysioreg = getreg32(SAM_MATRIX_CCFG_SYSIO);
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sysioreg |= MATRIX_CCFG_SYSIO_SYSIO4;
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putreg32(sysioreg, SAM_MATRIX_CCFG_SYSIO);
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# if defined(CONFIG_SAMV7_JTAG_FULL_ENABLE)
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# error CONFIG_SAMV7_JTAG_FULL_ENABLE is set To use the USART1 as an USART, the SYSIO Pin4 must be bound to PB4
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# endif
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#endif
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#ifdef CONFIG_SAMV7_USART2
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@ -357,6 +357,7 @@ void __start(void)
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sam_clockconfig();
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sam_fpuconfig();
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sam_gpioinit();
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sam_lowsetup();
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/* Enable/disable tightly coupled memories */
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