From 8fac871cc9a76c888862809c8732c9277c86971f Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Thu, 19 May 2016 14:33:54 -0600 Subject: [PATCH] Adds a JTAG config and ERASE config to Kconfig to set the CCFG_SYSIO SYSIO Pins MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit • SYSIO4: PB4 or TDI Assignment 0: TDI function selected. 1: PB4 function selected. • SYSIO5: PB5 or TDO/TRACESWO Assignment 0: TDO/TRACESWO function selected. 1: PB5 function selected. • SYSIO6: PB6 or TMS/SWDIO Assignment 0: TMS/SWDIO function selected. 1: PB6 function selected. • SYSIO7: PB7 or TCK/SWCLK Assignment 0: TCK/SWCLK function selected. 1: PB7 function selected. • SYSIO12: PB12 or ERASE Assignment 0: ERASE function selected. 1: PB12 function selected. The thing I did not add is warning or compilation failure, (to save the next guy the hassle), at ALL the driver points that uses the these pins. I did remove this /* To use the USART1 as an USART, the SYSIO Pin4 must be bound to PB4 * instead of TDI */ uint32_t sysioreg = getreg32(SAM_MATRIX_CCFG_SYSIO); sysioreg |= MATRIX_CCFG_SYSIO_SYSIO4; putreg32(sysioreg, SAM_MATRIX_CCFG_SYSIO); in sam_lowputc.c in favor of an #error - because the default is an input TDI and driving it blindly to an output TXD1, would be a contention. --- arch/arm/src/samv7/Kconfig | 69 ++++++++++++++++++++++++++++++++ arch/arm/src/samv7/sam_gpio.c | 51 +++++++++++++++++++++-- arch/arm/src/samv7/sam_gpio.h | 18 +++++++++ arch/arm/src/samv7/sam_lowputc.c | 17 ++++---- arch/arm/src/samv7/sam_start.c | 1 + 5 files changed, 144 insertions(+), 12 deletions(-) diff --git a/arch/arm/src/samv7/Kconfig b/arch/arm/src/samv7/Kconfig index 5a68712427..61186d7b20 100644 --- a/arch/arm/src/samv7/Kconfig +++ b/arch/arm/src/samv7/Kconfig @@ -549,6 +549,75 @@ config SAMV7_RSWDT endmenu # SAMV7 Peripheral Selection +choice + prompt "JTAG IO Configuration" + default SAMV7_JTAG_FULL_ENABLE + ---help--- + JTAG Enable settings (by default the IO for JTAG-DP and SW-DP are + enabled) + +config SAMV7_JTAG_DISABLE + bool "Disable all JTAG IO" + ---help--- + JTAG Enable settings (by default the IO for JTAG-DP and SW-DP are + enabled) + + When JTAG is disabled PB4-BP7 is assigned as a GPIO and can be + configured for use as GPIO or a Peripheral + +config SAMV7_JTAG_FULL_ENABLE + bool "Enable full JTAG IO to use JTAG-DP + SW-DP" + ---help--- + The JTAG IO is configured for both JTAG-DP + SW-DP" + + PB4 is TDI + PB5 is TDO/TRACESWO + PB6 is TMS/SWDIO + PB7 is TCK/SWCLK + +config SAMV7_JTAG_FULL_SW_ENABLE + bool "Set JTAG-DP IO disabled and Full SW-DP IO enabled" + ---help--- + JTAG IO is configured for SW-DP with Trace" + + PB5 is TDO/TRACESWO + PB6 is TMS/SWDIO + PB7 is TCK/SWCLK + +config SAMV7_JTAG_SW_ENABLE + bool "Set JTAG-DP IO disabled and SW-DP IO enabled" + ---help--- + JTAG IO is configured for SW-DP without Trace " + + PB6 is TMS/SWDIO + PB7 is TCK/SWCLK + +endchoice # JTAG IO Configuration + +choice + prompt "ERASE Pin Configuration" + default SAMV7_ERASE_ENABLE + ---help--- + ERASE Pin Enable settings (by default ERASE pin is enabled) + +config SAMV7_ERASE_DISABLE + bool "Disable ERASE Pin" + ---help--- + ERASE Pin Enable settings (by default ERASE pin is enabled) + + When the ERASE pin is disabled PB12 is assigned as a GPIO and can be + configured for use as GPIO or a Peripheral. + + N.B. a low level must be ensured at startup to prevent Flash erase before + the user application sets PB12 into PIO mode, + +config SAMV7_ERASE_ENABLE + bool "Enable ERASE Pin" + ---help--- + The ERASE pin is configured to reinitialize the Flash content. + +endchoice + menuconfig SAMV7_GPIO_IRQ bool "GPIO pin interrupts" ---help--- diff --git a/arch/arm/src/samv7/sam_gpio.c b/arch/arm/src/samv7/sam_gpio.c index 628c1979f8..0cd5596191 100644 --- a/arch/arm/src/samv7/sam_gpio.c +++ b/arch/arm/src/samv7/sam_gpio.c @@ -54,14 +54,30 @@ #include "sam_gpio.h" #include "chip/sam_pio.h" +#include "chip/sam_matrix.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/**************************************************************************** - * Private Types - ****************************************************************************/ +#if !defined(CONFIG_SAMV7_ERASE_ENABLE) || \ + !defined(CONFIG_SAMV7_JTAG_FULL_ENABLE) +# if defined(CONFIG_SAMV7_ERASE_DISABLE) +# define SYSIO_ERASE_BIT MATRIX_CCFG_SYSIO_SYSIO12 +# else +# define SYSIO_ERASE_BIT 0 +# endif +# if defined(CONFIG_SAMV7_JTAG_DISABLE) +# define SYSIO_BITS (MATRIX_CCFG_SYSIO_SYSIO4 | MATRIX_CCFG_SYSIO_SYSIO5 | \ + MATRIX_CCFG_SYSIO_SYSIO6 | MATRIX_CCFG_SYSIO_SYSIO7) +# endif +# if defined(CONFIG_SAMV7_JTAG_FULL_SW_ENABLE) +# define SYSIO_BITS MATRIX_CCFG_SYSIO_SYSIO4 +# endif +# if defined(CONFIG_SAMV7_JTAG_SW_ENABLE) +# define SYSIO_BITS (MATRIX_CCFG_SYSIO_SYSIO4 | MATRIX_CCFG_SYSIO_SYSIO5) +# endif +#endif /**************************************************************************** * Private Data @@ -70,7 +86,7 @@ #ifdef CONFIG_DEBUG_GPIO static const char g_portchar[SAMV7_NPIO] = { - 'A' + 'A' #if SAMV7_NPIO > 1 , 'B' #endif @@ -402,6 +418,33 @@ static inline int sam_configperiph(uintptr_t base, uint32_t pin, * Public Functions ****************************************************************************/ +/**************************************************************************** + * Function: sam_gpioinit + * + * Description: + * Based on configuration within the .config file, it does: + * - Configures the CCFG_SYSIO bits. + * + * Typically called from sam_start(). + * + * Assumptions: + * This function is called early in the initialization sequence so that + * no mutual exlusion is necessary. + * + ****************************************************************************/ + +#if !defined(CONFIG_SAMV7_ERASE_ENABLE) || \ + !defined(CONFIG_SAMV7_JTAG_FULL_ENABLE) +void sam_gpioinit(void) +{ + uint32_t regval; + + regval = getreg32(SAM_MATRIX_CCFG_SYSIO); + regval |= (SYSIO_ERASE_BIT | SYSIO_BITS); + putreg32(regval, SAM_MATRIX_CCFG_SYSIO); +} +#endif + /**************************************************************************** * Name: sam_configgpio * diff --git a/arch/arm/src/samv7/sam_gpio.h b/arch/arm/src/samv7/sam_gpio.h index 4b5b6f5208..2e564ec787 100644 --- a/arch/arm/src/samv7/sam_gpio.h +++ b/arch/arm/src/samv7/sam_gpio.h @@ -265,6 +265,24 @@ static inline int sam_gpio_pinmask(gpio_pinset_t cfgset) * Public Function Prototypes ************************************************************************************/ +/************************************************************************************ + * Function: sam_gpioinit + * + * Description: + * Based on configuration within the .config file, it does: + * - Remaps positions of alternative functions for GPIO. + * + * Typically called from sam_start(). + * + ************************************************************************************/ + +#if !defined(CONFIG_SAMV7_ERASE_ENABLE) || \ + !defined(CONFIG_SAMV7_JTAG_FULL_ENABLE) +void sam_gpioinit(void); +#else +# define sam_gpioinit() +#endif + /************************************************************************************ * Name: sam_gpioirqinitialize * diff --git a/arch/arm/src/samv7/sam_lowputc.c b/arch/arm/src/samv7/sam_lowputc.c index 502884cc0d..72d2f94998 100644 --- a/arch/arm/src/samv7/sam_lowputc.c +++ b/arch/arm/src/samv7/sam_lowputc.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/samv7/sam_lowputc.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -348,19 +348,20 @@ void sam_lowsetup(void) #ifdef CONFIG_SAMV7_USART1 (void)sam_configgpio(GPIO_USART1_RXD); (void)sam_configgpio(GPIO_USART1_TXD); -#ifdef CONFIG_USART1_OFLOWCONTROL +# ifdef CONFIG_USART1_OFLOWCONTROL (void)sam_configgpio(GPIO_USART1_CTS); -#endif -#ifdef CONFIG_USART1_IFLOWCONTROL +# endif +# ifdef CONFIG_USART1_IFLOWCONTROL (void)sam_configgpio(GPIO_USART1_RTS); -#endif +# endif + /* To use the USART1 as an USART, the SYSIO Pin4 must be bound to PB4 * instead of TDI */ - uint32_t sysioreg = getreg32(SAM_MATRIX_CCFG_SYSIO); - sysioreg |= MATRIX_CCFG_SYSIO_SYSIO4; - putreg32(sysioreg, SAM_MATRIX_CCFG_SYSIO); +# if defined(CONFIG_SAMV7_JTAG_FULL_ENABLE) +# error CONFIG_SAMV7_JTAG_FULL_ENABLE is set To use the USART1 as an USART, the SYSIO Pin4 must be bound to PB4 +# endif #endif #ifdef CONFIG_SAMV7_USART2 diff --git a/arch/arm/src/samv7/sam_start.c b/arch/arm/src/samv7/sam_start.c index 9d5331721f..e00a7bc585 100644 --- a/arch/arm/src/samv7/sam_start.c +++ b/arch/arm/src/samv7/sam_start.c @@ -357,6 +357,7 @@ void __start(void) sam_clockconfig(); sam_fpuconfig(); + sam_gpioinit(); sam_lowsetup(); /* Enable/disable tightly coupled memories */