S32K3XX QSPI No need to check TX FIFO buffer when MPU is correctly configured
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@ -374,6 +374,7 @@ config S32K3XX_ENET
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config S32K3XX_QSPI
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bool "QSPI Flash"
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default n
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select ARCH_USE_MPU
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depends on S32K3XX_HAVE_QSPI
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menu "FlexCAN"
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@ -888,6 +888,7 @@ static int qspi_transmit_blocking(struct s32k3xx_qspidev_s *priv,
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uint32_t count = UINT32_MAX;
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uint32_t *data = (uint32_t *)meminfo->buffer;
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uint32_t write_cycle = min(32, ((uint32_t)remaining) >> 2U);
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uint32_t timeout = 1000;
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int ret = 0;
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/* Copy sequence in LUT registers */
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@ -916,31 +917,33 @@ static int qspi_transmit_blocking(struct s32k3xx_qspidev_s *priv,
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putreg32(QSPI_AMBA_BASE + meminfo->addr, S32K3XX_QSPI_SFAR);
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/* Re-attempt filling TX fifo if size doesn't match */
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while ((getreg32(S32K3XX_QSPI_TBSR) & QSPI_TBSR_TRBLF_MASK) != count)
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{
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/* Clear TX fifo */
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regval = getreg32(S32K3XX_QSPI_MCR);
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regval |= QSPI_MCR_CLR_TXF;
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putreg32(regval, S32K3XX_QSPI_MCR);
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do /* Wait for fifo clear otherwise timeout */
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{
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timeout--;
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}
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while ((getreg32(S32K3XX_QSPI_TBSR) & QSPI_TBSR_TRBLF_MASK) != 0
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&& timeout > 0);
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if (timeout == 0)
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{
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return -ETIMEDOUT;
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}
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spiinfo("Transmit: %" PRIu32 " size: %" PRIu32 "\n",
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meminfo->addr, meminfo->buflen);
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for (count = 0U; count < write_cycle; count++)
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{
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while ((getreg32(S32K3XX_QSPI_TBSR)
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& QSPI_TBSR_TRBLF_MASK) != count)
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{
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}
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putreg32(*data, S32K3XX_QSPI_TBDR);
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data++;
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remaining -= 4U;
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}
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}
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/* Trigger IP command with specified sequence and size */
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