sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Misc. trivial changes from review of last PR

Browse Source
This commit is contained in:
Gregory Nutt 2016-03-27 13:16:15 -06:00
parent bd70ad404b
commit 909d264dea
2 changed files with 9 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
configs/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h
View File

@ -131,12 +131,12 @@
/* CLK48 will come from PLLSAI1 (implicitly Q) */ /* CLK48 will come from PLLSAI1 (implicitly Q) */
#define STM32L4_USE_CLK48 #define STM32L4_USE_CLK48 1
#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 #define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
/* enable the LSE oscillator, used automatically trim the MSI, and for RTC */ /* enable the LSE oscillator, used automatically trim the MSI, and for RTC */
#define STM32L4_USE_LSE #define STM32L4_USE_LSE 1
/* AHB clock (HCLK) is SYSCLK (80MHz) */ /* AHB clock (HCLK) is SYSCLK (80MHz) */

12
configs/stm32l476vg-disco/src/stm32_clockconfig.c
View File

@ -141,8 +141,8 @@ void stm32l4_board_clockconfig(void)
/* Set the PLL dividers and multipliers to configure the SAI1 PLL */ /* Set the PLL dividers and multipliers to configure the SAI1 PLL */
regval = (STM32L4_PLLSAI1CFG_PLLN | STM32L4_PLLSAI1CFG_PLLP regval = (STM32L4_PLLSAI1CFG_PLLN | STM32L4_PLLSAI1CFG_PLLP |
| STM32L4_PLLSAI1CFG_PLLQ | STM32L4_PLLSAI1CFG_PLLR); STM32L4_PLLSAI1CFG_PLLQ | STM32L4_PLLSAI1CFG_PLLR);
regval |= RCC_PLLSAI1CFG_PLLQEN; regval |= RCC_PLLSAI1CFG_PLLQEN;
putreg32(regval, STM32L4_RCC_PLLSAI1CFG); putreg32(regval, STM32L4_RCC_PLLSAI1CFG);
@ -165,8 +165,8 @@ void stm32l4_board_clockconfig(void)
/* Enable the SAI2 PLL */ /* Enable the SAI2 PLL */
/* Set the PLL dividers and multipliers to configure the SAI2 PLL */ /* Set the PLL dividers and multipliers to configure the SAI2 PLL */
regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP |
| STM32L4_PLLSAI2CFG_PLLR); STM32L4_PLLSAI2CFG_PLLR);
putreg32(regval, STM32L4_RCC_PLLSAI2CFG); putreg32(regval, STM32L4_RCC_PLLSAI2CFG);
/* Enable the SAI1 PLL */ /* Enable the SAI1 PLL */
@ -184,7 +184,8 @@ void stm32l4_board_clockconfig(void)
/* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */ /* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */
#ifdef CONFIG_STM32L4_FLASH_PREFETCH #ifdef CONFIG_STM32L4_FLASH_PREFETCH
regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN |
FLASH_ACR_PRFTEN);
#else #else
regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN);
#endif #endif
@ -217,6 +218,7 @@ void stm32l4_board_clockconfig(void)
* TODO: There is another case where the LSE needs to * TODO: There is another case where the LSE needs to
* be enabled: if the MCO1 pin selects LSE as source. * be enabled: if the MCO1 pin selects LSE as source.
*/ */
stm32l4_pwr_enableclk(true); stm32l4_pwr_enableclk(true);
stm32l4_rcc_enablelse(); stm32l4_rcc_enablelse();
#endif #endif