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LPC11: Make some spacing comply better with coding standard

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This commit is contained in:
Gregory Nutt 2015-10-06 19:23:32 -06:00
parent d0d62668e7
commit 90b7cdcdaf
7 changed files with 62 additions and 60 deletions
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18
arch/arm/src/lpc11xx/lpc11_i2c.c
View File

@ -226,7 +226,7 @@ static int i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer,
priv->wrcnt = 0;
priv->rdcnt = 0;
priv->msg.addr &= ~0x01;
priv->msg.buffer = (uint8_t*)buffer;
priv->msg.buffer = (uint8_t *)buffer;
priv->msg.length = buflen;
ret = i2c_start(priv);
@ -347,21 +347,21 @@ static int i2c_interrupt(int irq, FAR void *context)
#ifdef CONFIG_LPC11_I2C0
if (irq == LPC11_IRQ_I2C0)
{
priv=&i2cdevices[0];
priv = &i2cdevices[0];
}
else
#endif
#ifdef CONFIG_LPC11_I2C1
if (irq == LPC11_IRQ_I2C1)
{
priv=&i2cdevices[1];
priv = &i2cdevices[1];
}
else
#endif
#ifdef CONFIG_LPC11_I2C2
if (irq == LPC11_IRQ_I2C2)
{
priv=&i2cdevices[2];
priv = &i2cdevices[2];
}
else
#endif
@ -399,7 +399,7 @@ static int i2c_interrupt(int irq, FAR void *context)
case 0x28:
priv->wrcnt++;
if (priv->wrcnt<priv->msg.length)
if (priv->wrcnt < priv->msg.length)
{
putreg32(priv->msg.buffer[priv->wrcnt], priv->base + LPC11_I2C_DAT_OFFSET);
}
@ -465,11 +465,11 @@ struct i2c_dev_s *up_i2cinitialize(int port)
flags = irqsave();
priv= &i2cdevices[port];
priv = &i2cdevices[port];
#ifdef CONFIG_LPC11_I2C0
if (port == 0)
{
priv= (FAR struct lpc11_i2cdev_s *)&i2cdevices[0];
priv = (FAR struct lpc11_i2cdev_s *)&i2cdevices[0];
priv->base = LPC11_I2C0_BASE;
priv->irqid = LPC11_IRQ_I2C0;
@ -493,7 +493,7 @@ struct i2c_dev_s *up_i2cinitialize(int port)
#ifdef CONFIG_LPC11_I2C1
if (port == 1)
{
priv= (FAR struct lpc11_i2cdev_s *)&i2cdevices[1];
priv = (FAR struct lpc11_i2cdev_s *)&i2cdevices[1];
priv->base = LPC11_I2C1_BASE;
priv->irqid = LPC11_IRQ_I2C1;
@ -517,7 +517,7 @@ struct i2c_dev_s *up_i2cinitialize(int port)
#ifdef CONFIG_LPC11_I2C2
if (port == 2)
{
priv= (FAR struct lpc11_i2cdev_s *)&i2cdevices[2];
priv = (FAR struct lpc11_i2cdev_s *)&i2cdevices[2];
priv->base = LPC11_I2C2_BASE;
priv->irqid = LPC11_IRQ_I2C2;

2
arch/arm/src/lpc11xx/lpc11_irq.c
View File

@ -59,7 +59,7 @@
/* Get a 32-bit version of the default priority */
#define DEFPRIORITY32 \
(NVIC_SYSH_PRIORITY_DEFAULT << 24 | NVIC_SYSH_PRIORITY_DEFAULT << 16 |\
(NVIC_SYSH_PRIORITY_DEFAULT << 24 | NVIC_SYSH_PRIORITY_DEFAULT << 16 | \
NVIC_SYSH_PRIORITY_DEFAULT << 8 | NVIC_SYSH_PRIORITY_DEFAULT)
/****************************************************************************

53
arch/arm/src/lpc11xx/lpc11_serial.c
View File

@ -407,17 +407,17 @@ static inline uint32_t lpc11_uartdl(uint32_t baud)
static int up_setup(struct uart_dev_s *dev)
{
#ifndef CONFIG_SUPPRESS_UART_CONFIG
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
uint16_t dl;
uint32_t lcr;
/* Clear fifos */
up_serialout(priv, LPC11_UART_FCR_OFFSET, (UART_FCR_RXRST|UART_FCR_TXRST));
up_serialout(priv, LPC11_UART_FCR_OFFSET, (UART_FCR_RXRST | UART_FCR_TXRST));
/* Set trigger */
up_serialout(priv, LPC11_UART_FCR_OFFSET, (UART_FCR_FIFOEN|UART_FCR_RXTRIGGER_8));
up_serialout(priv, LPC11_UART_FCR_OFFSET, (UART_FCR_FIFOEN | UART_FCR_RXTRIGGER_8));
/* Set up the IER */
@ -443,11 +443,11 @@ static int up_setup(struct uart_dev_s *dev)
if (priv->parity == 1)
{
lcr |= (UART_LCR_PE|UART_LCR_PS_ODD);
lcr |= (UART_LCR_PE | UART_LCR_PS_ODD);
}
else if (priv->parity == 2)
{
lcr |= (UART_LCR_PE|UART_LCR_PS_EVEN);
lcr |= (UART_LCR_PE | UART_LCR_PS_EVEN);
}
/* Enter DLAB=1 */
@ -471,7 +471,8 @@ static int up_setup(struct uart_dev_s *dev)
/* Configure the FIFOs */
up_serialout(priv, LPC11_UART_FCR_OFFSET,
(UART_FCR_RXTRIGGER_8|UART_FCR_TXRST|UART_FCR_RXRST|UART_FCR_FIFOEN));
(UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST | UART_FCR_RXRST |
UART_FCR_FIFOEN));
#endif
@ -488,7 +489,7 @@ static int up_setup(struct uart_dev_s *dev)
static void up_shutdown(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
up_disableuartint(priv, NULL);
}
@ -510,7 +511,7 @@ static void up_shutdown(struct uart_dev_s *dev)
static int up_attach(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
int ret;
/* Attach and enable the IRQ */
@ -518,11 +519,11 @@ static int up_attach(struct uart_dev_s *dev)
ret = irq_attach(priv->irq, up_interrupt);
if (ret == OK)
{
/* Enable the interrupt (RX and TX interrupts are still disabled
* in the UART
*/
/* Enable the interrupt (RX and TX interrupts are still disabled
* in the UART
*/
up_enable_irq(priv->irq);
up_enable_irq(priv->irq);
}
return ret;
@ -540,7 +541,7 @@ static int up_attach(struct uart_dev_s *dev)
static void up_detach(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
up_disable_irq(priv->irq);
irq_detach(priv->irq);
}
@ -575,7 +576,7 @@ static int up_interrupt(int irq, void *context)
PANIC();
}
priv = (struct up_dev_s*)dev->priv;
priv = (struct up_dev_s *)dev->priv;
/* Loop until there are no characters to be transferred or,
* until we have been looping for a long time.
@ -658,7 +659,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
{
struct inode *inode = filep->f_inode;
struct uart_dev_s *dev = inode->i_private;
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
int ret = OK;
switch (cmd)
@ -666,7 +667,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT
case TIOCSERGSTRUCT:
{
struct up_dev_s *user = (struct up_dev_s*)arg;
struct up_dev_s *user = (struct up_dev_s *)arg;
if (!user)
{
ret = -EINVAL;
@ -699,7 +700,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
#ifdef CONFIG_SERIAL_TERMIOS
case TCGETS:
{
struct termios *termiosp = (struct termios*)arg;
struct termios *termiosp = (struct termios *)arg;
if (!termiosp)
{
@ -719,7 +720,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
case TCSETS:
{
struct termios *termiosp = (struct termios*)arg;
struct termios *termiosp = (struct termios *)arg;
uint32_t lcr; /* Holds current values of line control register */
uint16_t dl; /* Divisor latch */
@ -788,7 +789,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
static int up_receive(struct uart_dev_s *dev, uint32_t *status)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
uint32_t rbr;
*status = up_serialin(priv, LPC11_UART_LSR_OFFSET);
@ -806,7 +807,7 @@ static int up_receive(struct uart_dev_s *dev, uint32_t *status)
static void up_rxint(struct uart_dev_s *dev, bool enable)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
if (enable)
{
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
@ -831,7 +832,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
static bool up_rxavailable(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
return ((up_serialin(priv, LPC11_UART_LSR_OFFSET) & UART_LSR_RDR) != 0);
}
@ -845,7 +846,7 @@ static bool up_rxavailable(struct uart_dev_s *dev)
static void up_send(struct uart_dev_s *dev, int ch)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
up_serialout(priv, LPC11_UART_THR_OFFSET, (uint32_t)ch);
}
@ -859,7 +860,7 @@ static void up_send(struct uart_dev_s *dev, int ch)
static void up_txint(struct uart_dev_s *dev, bool enable)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
irqstate_t flags;
flags = irqsave();
@ -895,7 +896,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
static bool up_txready(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
return ((up_serialin(priv, LPC11_UART_LSR_OFFSET) & UART_LSR_THRE) != 0);
}
@ -909,7 +910,7 @@ static bool up_txready(struct uart_dev_s *dev)
static bool up_txempty(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
return ((up_serialin(priv, LPC11_UART_LSR_OFFSET) & UART_LSR_THRE) != 0);
}
@ -991,7 +992,7 @@ void up_serialinit(void)
int up_putc(int ch)
{
#ifdef HAVE_SERIAL_CONSOLE
struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv;
struct up_dev_s *priv = (struct up_dev_s *)CONSOLE_DEV.priv;
uint32_t ier;
up_disableuartint(priv, &ier);
#endif

29
arch/arm/src/lpc11xx/lpc11_spi.c
View File

@ -269,9 +269,9 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev,
divisor = SPI_CLOCK / frequency;
/* The SPI CCR register must contain an even number greater than or equal
* to 8.
*/
/* The SPI CCR register must contain an even number greater than or equal
* to 8.
*/
if (divisor < 8)
{
@ -332,7 +332,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
/* Yes... Set CR appropriately */
regval = getreg32(LPC11_SPI_CR);
regval &= ~(SPI_CR_CPOL|SPI_CR_CPHA);
regval &= ~(SPI_CR_CPOL | SPI_CR_CPHA);
switch (mode)
{
@ -348,7 +348,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
break;
case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
regval |= (SPI_CR_CPOL|SPI_CR_CPHA);
regval |= (SPI_CR_CPOL | SPI_CR_CPHA);
break;
default:
@ -467,7 +467,7 @@ static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd)
static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer,
size_t nwords)
{
FAR uint8_t *ptr = (FAR uint8_t*)buffer;
FAR uint8_t *ptr = (FAR uint8_t *)buffer;
uint8_t data;
spidbg("nwords: %d\n", nwords);
@ -515,7 +515,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer,
static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer,
size_t nwords)
{
FAR uint8_t *ptr = (FAR uint8_t*)buffer;
FAR uint8_t *ptr = (FAR uint8_t *)buffer;
spidbg("nwords: %d\n", nwords);
while (nwords)
@ -531,16 +531,16 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer,
* data transfer.
*/
while ((getreg32(LPC11_SPI_SR) & SPI_SR_SPIF) == 0);
while ((getreg32(LPC11_SPI_SR) & SPI_SR_SPIF) == 0);
/* Read the SPI Status Register again to clear the status bit */
/* Read the SPI Status Register again to clear the status bit */
(void)getreg32(LPC11_SPI_SR);
(void)getreg32(LPC11_SPI_SR);
/* Read the received data from the SPI Data Register */
/* Read the received data from the SPI Data Register */
*ptr++ = (uint8_t)getreg32(LPC11_SPI_DR);
nwords--;
*ptr++ = (uint8_t)getreg32(LPC11_SPI_DR);
nwords--;
}
}
@ -598,7 +598,8 @@ FAR struct spi_dev_s *lpc11_spiinitialize(int port)
/* Configure 8-bit SPI mode and master mode */
putreg32(SPI_CR_BITS_8BITS|SPI_CR_BITENABLE|SPI_CR_MSTR, LPC11_SPI_CR);
putreg32(SPI_CR_BITS_8BITS | SPI_CR_BITENABLE | SPI_CR_MSTR,
LPC11_SPI_CR);
/* Set the initial SPI configuration */

6
arch/arm/src/lpc11xx/lpc11_ssp.c
View File

@ -518,7 +518,7 @@ static void ssp_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
/* Yes... Set CR0 appropriately */
regval = ssp_getreg(priv, LPC11_SSP_CR0_OFFSET);
regval &= ~(SSP_CR0_CPOL|SSP_CR0_CPHA);
regval &= ~(SSP_CR0_CPOL | SSP_CR0_CPHA);
switch (mode)
{
@ -534,7 +534,7 @@ static void ssp_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
break;
case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
regval |= (SSP_CR0_CPOL|SSP_CR0_CPHA);
regval |= (SSP_CR0_CPOL | SSP_CR0_CPHA);
break;
default:
@ -1012,7 +1012,7 @@ FAR struct spi_dev_s *lpc11_sspinitialize(int port)
/* Configure 8-bit SPI mode */
ssp_putreg(priv, LPC11_SSP_CR0_OFFSET, SSP_CR0_DSS_8BIT|SSP_CR0_FRF_SPI);
ssp_putreg(priv, LPC11_SSP_CR0_OFFSET, SSP_CR0_DSS_8BIT | SSP_CR0_FRF_SPI);
/* Disable the SSP and all interrupts (we'll poll for all data) */

4
arch/arm/src/lpc11xx/lpc11_timer.c
View File

@ -423,7 +423,7 @@ static int timer_setup(FAR struct pwm_lowerhalf_s *dev)
* external bit
*/
putreg32(((1 << 1)|(3 << 6)), LPC17_TMR0_EMR);
putreg32(((1 << 1) | (3 << 6)), LPC17_TMR0_EMR);
putreg32((1 << 0), LPC17_TMR0_TCR); /* Start timer0 */
/* Configure the output pins GPIO3.26 */
@ -436,7 +436,7 @@ static int timer_setup(FAR struct pwm_lowerhalf_s *dev)
putreg32(~(0x3 << 0), LPC17_TMR1_CCR); /* Prescaler count frequency:Fpclk/1 */
putreg32(~(0x3 << 0), LPC17_TMR1_CTCR);/* Prescaler count frequency:Fpclk/1 */
putreg32((2 << 0), LPC17_TMR1_MCR); /* Reset on match register MR0 */
// putreg32(((1 << 0)|(3 << 4)), LPC17_TMR1_EMR); /* Output bit toggle on external match event MAT0 */
// putreg32(((1 << 0) | (3 << 4)), LPC17_TMR1_EMR); /* Output bit toggle on external match event MAT0 */
putreg32((1 << 0), LPC17_TMR1_TCR); /* Start timer1 */
/* configure the output pins GPIO3.26 */

10
arch/arm/src/lpc11xx/lpc11_userspace.c
View File

@ -87,8 +87,8 @@ void lpc11_userspace(void)
DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 &&
USERSPACE->us_bssstart <= USERSPACE->us_bssend);
dest = (uint8_t*)USERSPACE->us_bssstart;
end = (uint8_t*)USERSPACE->us_bssend;
dest = (uint8_t *)USERSPACE->us_bssstart;
end = (uint8_t *)USERSPACE->us_bssend;
while (dest != end)
{
@ -101,9 +101,9 @@ void lpc11_userspace(void)
USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 &&
USERSPACE->us_datastart <= USERSPACE->us_dataend);
src = (uint8_t*)USERSPACE->us_datasource;
dest = (uint8_t*)USERSPACE->us_datastart;
end = (uint8_t*)USERSPACE->us_dataend;
src = (uint8_t *)USERSPACE->us_datasource;
dest = (uint8_t *)USERSPACE->us_datastart;
end = (uint8_t *)USERSPACE->us_dataend;
while (dest != end)
{