TMS570: Initalize SCI interrupt handling logic
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@ -244,9 +244,9 @@
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#define SCI_INT_PE (1 << 24) /* Bit 24: Parity error interrupt */
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#define SCI_INT_OE (1 << 25) /* Bit 25: Overrun error interrupt */
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#define SCI_INT_FE (1 << 26) /* Bit 26: Framing error interrupt */
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#define SCI_INT_NRE (1 << 27) /* Bit 27: No respose error interrupt */
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#define SCI_INT_ISFE (1 << 28) /* Bit 28: Inconsistene synch field error interrupt */
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#define SCI_INT_CE (1 << 29) /* Bit 29: checksum error interrupt */
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#define SCI_INT_NRE (1 << 27) /* Bit 27: No response error interrupt */
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#define SCI_INT_ISFE (1 << 28) /* Bit 28: Inconsistent synch field error interrupt */
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#define SCI_INT_CE (1 << 29) /* Bit 29: Checksum error interrupt */
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#define SCI_INT_PBE (1 << 30) /* Bit 30: Physical bus error interrupt */
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#define SCI_INT_BE (1 << 31) /* Bit 31: Bit error interrupt */
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@ -272,16 +272,32 @@
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#define SCI_FLR_PE (1 << 24) /* Bit 24: Parity error flag */
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#define SCI_FLR_OE (1 << 25) /* Bit 25: Overrun error flag */
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#define SCI_FLR_FE (1 << 26) /* Bit 26: Framing error flag */
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#define SCI_FLR_NRE (1 << 27) /* Bit 27: No respose error flag */
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#define SCI_FLR_ISFE (1 << 28) /* Bit 28: Inconsistene synch field error flag */
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#define SCI_FLR_NRE (1 << 27) /* Bit 27: No response error flag */
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#define SCI_FLR_ISFE (1 << 28) /* Bit 28: Inconsistent synch field error flag */
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#define SCI_FLR_CE (1 << 29) /* Bit 29: checksum error flag */
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#define SCI_FLR_PBE (1 << 30) /* Bit 30: Physical bus error flag */
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#define SCI_FLR_BE (1 << 31) /* Bit 31: Bit error flag */
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/* SCI Interrupt Vector Offset 0 */
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#define SCI_INTVECT0_
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/* SCI Interrupt Vector Offset 1 */
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#define SCI_INTVECT1_
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/* SCI Interrupt Vector Offset 0/1 */
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#define SCI_INTVECT_MASK (0x1f) /* Bits 0-4: Interrupt vector offset */
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# define SCI_INTVECT_NONE (0) /* No interrupt */
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# define SCI_INTVECT_WAKEUP (1) /* Wake-up interrupt */
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# define SCI_INTVECT_ISFE (2) /* Inconsistent synch field error interrupt */
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# define SCI_INTVECT_PE (3) /* Parity error interrupt */
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# define SCI_INTVECT_ID (4) /* Identification interrupt */
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# define SCI_INTVECT_PBE (5) /* Physical bus error interrupt */
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# define SCI_INTVECT_FE (6) /* Framing error interrupt */
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# define SCI_INTVECT_BRKDT (7) /* Break detect interrupt */
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# define SCI_INTVECT_CE (8) /* Checksum error interrupt */
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# define SCI_INTVECT_OE (9) /* Overrun error interrupt */
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# define SCI_INTVECT_BE (10) /* Bit error interrupt */
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# define SCI_INTVECT_RX (11) /* Receive interrupt */
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# define SCI_INTVECT_TX (12) /* Tranmit interrupt */
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# define SCI_INTVECT_NRE (13) /* No response error interrupt */
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# define SCI_INTVECT_TOAWUS (14) /* Timeout after wakeup signal interrupt */
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# define SCI_INTVECT_TOA3WUS (15) /* Timeout after 2 Wakeup signls interrupt */
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# define SCI_INTVECT_TIMEOUT (16) /* Timeout interrupt */
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/* SCI Format Control Register */
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@ -295,7 +295,7 @@ int tms570_sci_configure(uint32_t base, FAR const struct sci_config_s *config)
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return -ERANGE;
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}
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/* Disable all interrupts */
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/* Disable all interrupts and map them all to INT0 */
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putreg32(SCI_INT_ALL, base + TMS570_SCI_CLEARINT_OFFSET);
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putreg32(SCI_INT_ALL, base + TMS570_SCI_CLEARINTLVL_OFFSET);
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@ -279,7 +279,8 @@ static inline uint32_t tms570_serialin(struct tms570_dev_s *priv, int offset)
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* Name: tms570_serialout
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****************************************************************************/
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static inline void tms570_serialout(struct tms570_dev_s *priv, int offset, uint32_t value)
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static inline void tms570_serialout(struct tms570_dev_s *priv, int offset,
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uint32_t value)
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{
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putreg32(value, priv->scibase + offset);
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}
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@ -288,7 +289,8 @@ static inline void tms570_serialout(struct tms570_dev_s *priv, int offset, uint3
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* Name: tms570_restoresciint
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****************************************************************************/
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static inline void tms570_restoresciint(struct tms570_dev_s *priv, uint32_t imr)
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static inline void tms570_restoresciint(struct tms570_dev_s *priv,
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uint32_t imr)
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{
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/* Restore the previous interrupt state (assuming all interrupts disabled) */
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@ -431,51 +433,78 @@ static void tms570_detach(struct sci_dev_s *dev)
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static int tms570_interrupt(struct sci_dev_s *dev)
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{
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struct tms570_dev_s *priv;
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uint32_t pending;
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uint32_t imr;
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int passes;
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bool handled;
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uint32_t intvec;
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DEBUGASSERT(dev && dev->priv);
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DEBUGASSERT(dev != NULL && dev->priv != NULL);
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priv = (struct tms570_dev_s *)dev->priv;
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/* Loop until there are no characters to be transferred or, until we have
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* been looping for a long time.
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*/
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/* Loop until there are no further pending interrupts */
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handled = true;
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for (passes = 0; passes < 256 && handled; passes++)
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for (; ; )
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{
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handled = false;
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/* Get the SCI status (we are only interested in the unmasked interrupts). */
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priv->sr = tms570_serialin(priv, TMS570_SCI_SR_OFFSET);
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imr = tms570_serialin(priv, TMS570_SCI_IMR_OFFSET);
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pending = priv->sr & imr;
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/* Handle an incoming, receive byte. RXRDY: At least one complete character
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* has been received and US_RHR has not yet been read.
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/* Get the next pending interrupt. For most interrupts, reading the
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* INVECT0 register clears the corresonding INTFLAG.
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*/
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if ((pending & SCI_INT_RXRDY) != 0)
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intvec = tms570_serialin(priv, TMS570_SCI_INTVECT0_OFFSET) & SCI_INTVECT_MASK;
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/* Handle the pending interrupt */
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switch (intvec)
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{
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/* Received data ready... process incoming bytes */
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case SCI_INTVECT_NONE: /* No interrupt */
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return;
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sci_recvchars(dev);
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handled = true;
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}
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case SCI_INTVECT_WAKEUP: /* Wake-up interrupt */
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/* SCI sets the WAKEUP flag if bus activity on the RX line
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* either prevents power-down mode from being entered, or RX
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* line activity causes an exit from power-down mode. If
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* enabled wakeup interrupt is triggered once WAKEUP flag is
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* set.
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*/
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/* Handle outgoing, transmit bytes. TXRDY: There is no character in the
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* US_THR.
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*/
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#warning Missing Logic
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break;
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if ((pending & SCI_INT_TXRDY) != 0)
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{
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/* Transmit data register empty ... process outgoing bytes */
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/* SCI Errors */
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sci_xmitchars(dev);
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handled = true;
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case SCI_INTVECT_PE: /* Parity error interrupt */
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case SCI_INTVECT_FE: /* Framing error interrupt */
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case SCI_INTVECT_BRKDT: /* Break detect interrupt */
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case SCI_INTVECT_OE: /* Overrun error interrupt */
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case SCI_INTVECT_BE: /* Bit error interrupt */
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#warning Missing Logic
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break;
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case SCI_INTVECT_RX: /* Receive interrupt */
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{
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/* Receive data ready... process incoming bytes */
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uart_recvchars(dev);
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}
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break;
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case SCI_INTVECT_TX: /* Tranmit interrupt */
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{
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/* Transmit data register available ... process outgoing bytes */
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uart_xmitchars(dev);
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}
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break;
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/* LIN mode only. These should never occur in SCI mode */
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case SCI_INTVECT_ISFE: /* Inconsistent synch field error interrupt */
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case SCI_INTVECT_ID: /* Identification interrupt */
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case SCI_INTVECT_PBE: /* Physical bus error interrupt */
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case SCI_INTVECT_CE: /* Checksum error interrupt */
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case SCI_INTVECT_NRE: /* No response error interrupt */
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case SCI_INTVECT_TOAWUS: /* Timeout after wakeup signal interrupt */
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case SCI_INTVECT_TOA3WUS: /* Timeout after 2 Wakeup signls interrupt */
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case SCI_INTVECT_TIMEOUT: /* Timeout interrupt */
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default:
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PANIC();
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}
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}
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