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arch/arm/src/imxrt/imxrt_lpsrtc.c: SVNC LPCR register bits 0 & 1 are NOT reserved and are, in fact, needed to enabled the SRTC. Now the SRTC is working.

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This commit is contained in:
Ivan Ucherdzhiev 2018-09-26 10:13:20 -06:00 committed by Gregory Nutt
parent 6d2cce99e1
commit 910e7a3899
2 changed files with 5 additions and 4 deletions
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5
arch/arm/src/imxrt/chip/imxrt_snvs.h
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@ -200,10 +200,11 @@
/* SNVS_LP Control Register */
/* Bits 0-1: Reserved */
#define SVNS_LPCR_SRTCENV (1 << 0) /* Bit 0: Start SVNS RTC time counter */
#define SVNS_LPCR_LPTAEN (1 << 1) /* Bit 1: Enable SVNS RTC time alarm */
#define SNVS_LPCR_MCENV (1 << 2) /* Bit 2: Monotonic Counter Enabled and Valid */
#define SNVS_LPCR_LPWUIEN (1 << 3) /* Bit 3: LP Wake-Up Interrupt Enable */
/* Bit 4: Reserved */
/* Bit 4: Reserved */
#define SNVS_LPCR_DPEN (1 << 5) /* Bit 5: Dumb PMIC Enabled */
#define SNVS_LPCR_TOP (1 << 6) /* Bit 6: Turn off System Power */
#define SNVS_LPCR_PWRGLITCHEN (1 << 7) /* Bit 7: Power Glitch Enable */

4
arch/arm/src/imxrt/imxrt_lpsrtc.c
View File

@ -86,10 +86,10 @@ static void imxrt_lpsrtc_enable(void)
/* Enable the LPSRTC */
regval = getreg32(IMXRT_SNVS_LPCR);
regval |= SNVS_LPCR_MCENV;
regval |= SVNS_LPCR_SRTCENV;
putreg32(regval, IMXRT_SNVS_LPCR);
while ((getreg32(IMXRT_SNVS_LPCR) & SNVS_LPCR_MCENV) == 0)
while ((getreg32(IMXRT_SNVS_LPCR) & SVNS_LPCR_SRTCENV) == 0)
{
}
}