i.MX6: Finish off some missing IOMUXC register bit definitions
This commit is contained in:
Gregory Nutt
parent
012f1c0e90
commit
912008a883
@ -1738,7 +1738,470 @@
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/* IOMUXC Register Bit Definitions **************************************************/
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/* General Purpose Registers */
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/* General Purpose Register 0 (GPR0) */
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#define GPR0_DMAREQ_MUX_SEL0 (1 << 0)
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#define GPR0_DMAREQ_MUX_SEL1 (1 << 1)
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#define GPR0_DMAREQ_MUX_SEL2 (1 << 2)
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#define GPR0_DMAREQ_MUX_SEL3 (1 << 3)
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#define GPR0_DMAREQ_MUX_SEL4 (1 << 4)
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#define GPR0_DMAREQ_MUX_SEL5 (1 << 5)
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#define GPR0_DMAREQ_MUX_SEL6 (1 << 6)
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#define GPR0_DMAREQ_MUX_SEL7 (1 << 7)
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#define GPR0_AUDIO_VIDEO_MUXING_SHIFT (8)
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#define GPR0_AUDIO_VIDEO_MUXING_MASK (0x3f << GPR0_TX_CLK2_MUX_SEL_SHIFT)
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#define GPR0_TX_CLK2_MUX_SEL_SHIFT (14)
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#define GPR0_TX_CLK2_MUX_SEL_MASK (3 << GPR0_TX_CLK2_MUX_SEL_SHIFT)
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# define GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK1 (0 << GPR0_TX_CLK2_MUX_SEL_SHIFT)
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# define GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK2 (1 << GPR0_TX_CLK2_MUX_SEL_SHIFT)
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# define GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK3 (2 << GPR0_TX_CLK2_MUX_SEL_SHIFT)
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#define GPR0_CLOCK_1_MUX_SEL_SHIFT (16)
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#define GPR0_CLOCK_1_MUX_SEL_MASK (3 << GPR0_CLOCK_1_MUX_SEL_SHIFT)
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# define GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1_MUXED (0 << GPR0_CLOCK_1_MUX_SEL_SHIFT)
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# define GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1 (1 << GPR0_CLOCK_1_MUX_SEL_SHIFT)
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# define GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_SRCK (2 << GPR0_CLOCK_1_MUX_SEL_SHIFT)
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# define GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_RX_BIT_CLK (3 << GPR0_CLOCK_1_MUX_SEL_SHIFT)
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#define GPR0_CLOCK_9_MUX_SEL_SHIFT (3 << 18)
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#define GPR0_CLOCK_9_MUX_SEL_MASK (3 << GPR0_CLOCK_9_MUX_SEL_SHIFT)
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# define GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1_MUXED (0 << GPR0_CLOCK_9_MUX_SEL_SHIFT)
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# define GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1 (1 << GPR0_CLOCK_9_MUX_SEL_SHIFT)
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# define GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_STCK (2 << GPR0_CLOCK_9_MUX_SEL_SHIFT)
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# define GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_TX_BIT_CLK (3 << GPR0_CLOCK_9_MUX_SEL_SHIFT)
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#define GPR0_CLOCK_2_MUX_SEL_SHIFT (20)
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#define GPR0_CLOCK_2_MUX_SEL_MASK (3 << GPR0_CLOCK_2_MUX_SEL_SHIFT)
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# define GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2_MUXED (0 << GPR0_CLOCK_2_MUX_SEL_SHIFT)
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# define GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2 (1 << GPR0_CLOCK_2_MUX_SEL_SHIFT)
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# define GPR0_CLOCK_2_MUX_SEL_SSI2_SSI_SRCK (2 << GPR0_CLOCK_2_MUX_SEL_SHIFT)
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# define GPR0_CLOCK_2_MUX_SEL_SSI2_RX_BIT_CLK (3 << GPR0_CLOCK_2_MUX_SEL_SHIFT)
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#define GPR0_CLOCK_A_MUX_SEL_SHIFT (22)
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#define GPR0_CLOCK_A_MUX_SEL_MASK (3 << GPR0_CLOCK_A_MUX_SEL_SHIFT)
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# define GPR0_CLOCK_A_MUX_SEL_AUDMUX_TXCLK_P2_MUXED (0 << GPR0_CLOCK_A_MUX_SEL_SHIFT)
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# define GPR0_CLOCK_A_MUX_SEL_AUDMUX_TXCLK_P2 (1 << GPR0_CLOCK_A_MUX_SEL_SHIFT)
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# define GPR0_CLOCK_A_MUX_SEL_SSI2_SSI_STCK (2 << GPR0_CLOCK_A_MUX_SEL_SHIFT)
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# define GPR0_CLOCK_A_MUX_SEL_SSI2_TX_BIT_CLK (3 << GPR0_CLOCK_A_MUX_SEL_SHIFT)
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#define GPR0_CLOCK_3_MUX_SEL_SHIFT (24)
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#define GPR0_CLOCK_3_MUX_SEL_MASK (3 << GPR0_CLOCK_3_MUX_SEL_SHIFT)
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# define GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7_MUXED (3 << GPR0_CLOCK_3_MUX_SEL_SHIFT)
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# define GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7 (3 << GPR0_CLOCK_3_MUX_SEL_SHIFT)
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# define GPR0_CLOCK_3_MUX_SEL_SSI3_SSI_SRCK (3 << GPR0_CLOCK_3_MUX_SEL_SHIFT)
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# define GPR0_CLOCK_3_MUX_SEL_SSI3_RX_BIT_CLK (3 << GPR0_CLOCK_3_MUX_SEL_SHIFT)
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#define GPR0_CLOCK_B_MUX_SEL_SHIFT (26)
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#define GPR0_CLOCK_B_MUX_SEL_MASK (3 << GPR0_CLOCK_B_MUX_SEL_SHIFT)
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# define GPR0_CLOCK_B_MUX_SEL_AUDMUX_TXCLK_P7_MUXED (0 << GPR0_CLOCK_B_MUX_SEL_SHIFT)
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# define GPR0_CLOCK_B_MUX_SEL_AUDMUX_TXCLK_P7 (1 << GPR0_CLOCK_B_MUX_SEL_SHIFT)
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# define GPR0_CLOCK_B_MUX_SEL_SSI3_SSI_STCK (2 << GPR0_CLOCK_B_MUX_SEL_SHIFT)
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# define GPR0_CLOCK_B_MUX_SEL_SSI3_TX_BIT_CLK (3 << GPR0_CLOCK_B_MUX_SEL_SHIFT)
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#define GPR0_CLOCK_0_MUX_SEL_SHIFT (28)
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#define GPR0_CLOCK_0_MUX_SEL_MASK (3 << GPR0_CLOCK_0_MUX_SEL_SHIFT)
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# define GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_IND_SCKR_MUXED (0 << GPR0_CLOCK_0_MUX_SEL_SHIFT)
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# define GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_IND_SCKR (1 << GPR0_CLOCK_0_MUX_SEL_SHIFT)
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# define GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_DO_SCKR (2 << GPR0_CLOCK_0_MUX_SEL_SHIFT)
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#define GPR0_CLOCK_8_MUX_SEL_SHIFT (30)
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#define GPR0_CLOCK_8_MUX_SEL_MASK (3 << GPR0_CLOCK_8_MUX_SEL_SHIFT)
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# define GPR0_CLOCK_8_MUX_SEL_AUDMUX_RXCLK_P7_MUXED (0 << GPR0_CLOCK_8_MUX_SEL_SHIFT)
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# define GPR0_CLOCK_8_MUX_SEL_AUDMUX_RXCLK_P7 (1 << GPR0_CLOCK_8_MUX_SEL_SHIFT)
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# define GPR0_CLOCK_8_MUX_SEL_SSI3_SSI_SRCK (2 << GPR0_CLOCK_8_MUX_SEL_SHIFT)
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# define GPR0_CLOCK_8_MUX_SEL_SSI3_RX_BIT_CLK (3 << GPR0_CLOCK_8_MUX_SEL_SHIFT)
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#define GPR1_REF_SSP_EN (1 << 16)
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/* General Purpose Register 1 (GPR1) */
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#define GPR1_ACT_CS0 (1 << 0)
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#define GPR1_ADDRS0_SHIFT (1)
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#define GPR1_ADDRS0_MASK (3 << GPR1_ADDRS0_SHIFT)
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# define GPR1_ADDRS0(n) ((uint32_t)(n) << GPR1_ADDRS0_SHIFT)
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#define GPR1_ACT_CS1 (1 << 3)
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#define GPR1_ADDRS1_SHIFT (4)
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#define GPR1_ADDRS1_MASK (3 << GPR1_ADDRS1_SHIFT)
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# define GPR1_ADDRS1(n) ((uint32_t)(n) << GPR1_ADDRS1_SHIFT)
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#define GPR1_ACT_CS2 (1 << 6)
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#define GPR1_ADDRS2_SHFIT (7)
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#define GPR1_ADDRS2_MASK (3 << GPR1_ADDRS2_SHFIT)
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# define GPR1_ADDRS2(n) ((uint32_t)(n) << GPR1_ADDRS2_SHFIT)
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#define GPR1_ACT_CS3 (1 << 9)
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#define GPR1_ADDRS3_SHIFT (10)
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#define GPR1_ADDRS3_MASK (3 << GPR1_ADDRS3_SHIFT)
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# define GPR1_ADDRS3_32MB (0 << GPR1_ADDRS3_SHIFT)
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# define GPR1_ADDRS3_64MB (1 << GPR1_ADDRS3_SHIFT)
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# define GPR1_ADDRS3_128MB (2 << GPR1_ADDRS3_SHIFT)
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#define GPR1_GINT (1 << 12)
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#define GPR1_USB_OTG_ID_SEL (1 << 13)
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#define GPR1_SYS_INT (1 << 14)
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#define GPR1_USB_EXP_MODE (1 << 15)
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#define GPR1_IPU_VPU_MUX (1 << 17)
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#define GPR1_TEST_POWERDOWN (1 << 18)
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#define GPR1_MIPI_IPU1_MUX (1 << 19)
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#define GPR1_MIPI_IPU2_MUX (1 << 20)
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#define GPR1_ENET_CLK_SEL (1 << 21)
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#define GPR1_EXC_MON (1 << 22)
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#define GPR1_MIPI_DPI_OFF (1 << 24)
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#define GPR1_MIPI_COLOR_SW (1 << 25)
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#define GPR1_APP_REQ_ENTR_L1 (1 << 26)
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#define GPR1_APP_READY_ENTR_L23 (1 << 27)
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#define GPR1_APP_REQ_EXIT_L1 (1 << 28)
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#define GPR1_APP_CLK_REQ_N (1 << 30)
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#define GPR1_CFG_L1_CLK_REMOVAL_EN (1 << 31)
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/* General Purpose Register 2 (GPR2) */
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#define GPR2_CH0_MODE_SHIFT (0)
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#define GPR2_CH0_MODE_MASK (3 << GPR2_CH0_MODE_SHIFT)
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# define GPR2_CH0_MODE_DISABLED (0 << GPR2_CH0_MODE_SHIFT)
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# define GPR2_CH0_MODE_ROUTED_DI0 (1 << GPR2_CH0_MODE_SHIFT)
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# define GPR2_CH0_MODE_ROUTED_DI1 (3 << GPR2_CH0_MODE_SHIFT)
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#define GPR2_CH1_MODE_SHIFT (2)
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#define GPR2_CH1_MODE_MASK (3 << GPR2_CH1_MODE_SHIFT)
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# define GPR2_CH1_MODE_DISABLED (0 << GPR2_CH1_MODE_SHIFT)
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# define GPR2_CH1_MODE_ROUTED_DI0 (1 << GPR2_CH1_MODE_SHIFT)
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# define GPR2_CH1_MODE_ROUTED_DI1 (3 << GPR2_CH1_MODE_SHIFT)
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#define GPR2_SPLIT_MODE_EN (1 << 4)
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#define GPR2_DATA_WIDTH_CH0 (1 << 5)
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#define GPR2_BIT_MAPPING_CH0 (1 << 6)
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#define GPR2_DATA_WIDTH_CH1 (1 << 7)
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#define GPR2_BIT_MAPPING_CH1 (1 << 8)
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#define GPR2_DI0_VS_POLARITY (1 << 9)
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#define GPR2_DI1_VS_POLARITY (1 << 10)
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#define GPR2_LVDS_CLK_SHIFT_SHIFT (16)
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#define GPR2_LVDS_CLK_SHIFT_MASK (7 << GPR2_LVDS_CLK_SHIFT_SHIFT)
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# define GPR2_LVDS_CLK_SHIFT0 (0 << GPR2_LVDS_CLK_SHIFT_SHIFT)
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# define GPR2_LVDS_CLK_SHIFT1 (1 << GPR2_LVDS_CLK_SHIFT_SHIFT)
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# define GPR2_LVDS_CLK_SHIFT2 (2 << GPR2_LVDS_CLK_SHIFT_SHIFT)
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# define GPR2_LVDS_CLK_SHIFT3 (3 << GPR2_LVDS_CLK_SHIFT_SHIFT)
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# define GPR2_LVDS_CLK_SHIFT4 (4 << GPR2_LVDS_CLK_SHIFT_SHIFT)
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# define GPR2_LVDS_CLK_SHIFT5 (5 << GPR2_LVDS_CLK_SHIFT_SHIFT)
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# define GPR2_LVDS_CLK_SHIFT6 (6 << GPR2_LVDS_CLK_SHIFT_SHIFT)
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# define GPR2_LVDS_CLK_SHIFT7 (7 << GPR2_LVDS_CLK_SHIFT_SHIFT)
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#define GPR2_COUNTER_RESET_VAL_SHIFT (20)
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#define GPR2_COUNTER_RESET_VAL_MASK (3 << GPR2_COUNTER_RESET_VAL_SHIFT)
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# define GPR2_COUNTER_RESET_VAL5 (0 << GPR2_COUNTER_RESET_VAL_SHIFT)
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# define GPR2_COUNTER_RESET_VAL3 (1 << GPR2_COUNTER_RESET_VAL_SHIFT)
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# define GPR2_COUNTER_RESET_VAL4 (2 << GPR2_COUNTER_RESET_VAL_SHIFT)
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# define GPR2_COUNTER_RESET_VAL6 (3 << GPR2_COUNTER_RESET_VAL_SHIFT)
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/* General Purpose Register 3 (GPR3) */
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#define GPR3_HDMI_MUX_CTL_SHIFT (2)
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#define GPR3_HDMI_MUX_CTL_MASK (3 << GPR3_HDMI_MUX_CTL_SHIFT)
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# define GPR3_HDMI_MUX_CTL_IPU1_DI0 (0 << GPR3_HDMI_MUX_CTL_SHIFT)
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# define GPR3_HDMI_MUX_CTL_IPU1_DI1 (1 << GPR3_HDMI_MUX_CTL_SHIFT)
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# define GPR3_HDMI_MUX_CTL_IPU2_DI0 (2 << GPR3_HDMI_MUX_CTL_SHIFT)
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# define GPR3_HDMI_MUX_CTL_IPU2_DI1 (3 << GPR3_HDMI_MUX_CTL_SHIFT)
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#define GPR3_MIPI_MUX_CTL_SHIFT (4)
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#define GPR3_MIPI_MUX_CTL_MASK (3 << GPR3_MIPI_MUX_CTL_SHIFT)
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# define GPR3_MIPI_MUX_CTL_IPU1_DI0 (0 << GPR3_MIPI_MUX_CTL_SHIFT)
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# define GPR3_MIPI_MUX_CTL_IPU1_DI1 (1 << GPR3_MIPI_MUX_CTL_SHIFT)
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# define GPR3_MIPI_MUX_CTL_IPU2_DI0 (2 << GPR3_MIPI_MUX_CTL_SHIFT)
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# define GPR3_MIPI_MUX_CTL_IPU2_DI1 (3 << GPR3_MIPI_MUX_CTL_SHIFT)
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#define GPR3_LVDS0_MUX_CTL_SHIFT (6)
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#define GPR3_LVDS0_MUX_CTL_MASK (3 << GPR3_LVDS0_MUX_CTL_SHIFT)
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# define GPR3_LVDS0_MUX_CTL_IPU1_DI0 (0 << GPR3_LVDS0_MUX_CTL_SHIFT)
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# define GPR3_LVDS0_MUX_CTL_IPU1_DI1 (1 << GPR3_LVDS0_MUX_CTL_SHIFT)
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# define GPR3_LVDS0_MUX_CTL_IPU2_DI0 (2 << GPR3_LVDS0_MUX_CTL_SHIFT)
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# define GPR3_LVDS0_MUX_CTL_IPU2_DI1 (3 << GPR3_LVDS0_MUX_CTL_SHIFT)
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#define GPR3_LVDS1_MUX_CTL_SHIFT (8)
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#define GPR3_LVDS1_MUX_CTL_MASK (3 << GPR3_LVDS1_MUX_CTL_SHIFT)
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# define GPR3_LVDS1_MUX_CTL_IPU1_DI0 (0 << GPR3_LVDS1_MUX_CTL_SHIFT)
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# define GPR3_LVDS1_MUX_CTL_IPU1_DI1 (1 << GPR3_LVDS1_MUX_CTL_SHIFT)
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# define GPR3_LVDS1_MUX_CTL_IPU2_DI0 (2 << GPR3_LVDS1_MUX_CTL_SHIFT)
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# define GPR3_LVDS1_MUX_CTL_IPU2_DI1 (3 << GPR3_LVDS1_MUX_CTL_SHIFT)
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#define GPR3_IPU_DIAG (1 << 10)
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#define GPR3_TZASC1_BOOT_LOCK (1 << 11)
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#define GPR3_TZASC2_BOOT_LOCK (1 << 12)
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#define GPR3_CORE0_DBG_ACK_EN (1 << 13)
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#define GPR3_CORE1_DBG_ACK_EN (1 << 14)
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#define GPR3_CORE2_DBG_ACK_EN (1 << 15)
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#define GPR3_CORE3_DBG_ACK_EN (1 << 16)
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#define GPR3_OCRAM_STATUS_SHIFT (17)
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#define GPR3_OCRAM_STATUS_MASK (15 << GPR3_OCRAM_STATUS_SHIFT)
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# define GPR3_OCRAM_STATUS(n) ((uint32_t)(n) << GPR3_OCRAM_STATUS_SHIFT)
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#define GPR3_OCRAM_CTL_SHIFT (21)
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#define GPR3_OCRAM_CTL_MASK (15 << GPR3_OCRAM_CTL_SHIFT)
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# define GPR3_OCRAM_CTL(n) ((uint32_t)(n) << GPR3_OCRAM_CTL_SHIFT)
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#define GPR3_USDHCX_WR_CACHE_CTL (1 << 26)
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#define GPR3_USDHCX_RD_CACHE_CTL (1 << 25)
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#define GPR3_BCH_RD_CACHE_CTL (1 << 27)
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#define GPR3_BCH_WR_CACHE_CTL (1 << 28)
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#define GPR3_GPU_DBG_SHIFT (29)
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#define GPR3_GPU_DBG_MASK (3 << GPR3_GPU_DBG_SHIFT)
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# define GPR3_GPU_DBG_GPU3D (0 << GPR3_GPU_DBG_SHIFT)
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# define GPR3_GPU_DBG_GPU2D (1 << GPR3_GPU_DBG_SHIFT)
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# define GPR3_GPU_DBG_OPENVG (2 << GPR3_GPU_DBG_SHIFT)
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/* General Purpose Register 4 (GPR4) */
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#define GPR4_IPU_RD_CACHE_CTL (1 << 0)
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#define GPR4_IPU_WR_CACHE_CTL (1 << 1)
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#define GPR4_VPU_P_RD_CACHE_VAL (1 << 2)
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#define GPR4_VPU_P_WR_CACHE_VAL (1 << 3)
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#define GPR4_VPU_RD_CACHE_SEL (1 << 6)
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#define GPR4_VPU_WR_CACHE_SEL (1 << 7)
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#define GPR4_SOC_VERSION_SHIFT (8)
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#define GPR4_SOC_VERSION_MASK (0xff << GPR4_SOC_VERSION_SHIFT)
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#define GPR4_ENET_STOP_ACK (1 << 16)
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#define GPR4_CAN1_STOP_ACK (1 << 17)
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#define GPR4_CAN2_STOP_ACK (1 << 18)
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#define GPR4_SDMA_STOP_ACK (1 << 19)
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#define GPR4_PCIE_RD_CACHE_VAL (1 << 24)
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#define GPR4_PCIE_WR_CACHE_VAL (1 << 25)
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#define GPR4_PCIE_RD_CACHE_SEL (1 << 26)
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#define GPR4_PCIE_WR_CACHE_SEL (1 << 27)
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#define GPR4_VDOA_RD_CACHE_VAL (1 << 28)
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#define GPR4_VDOA_WR_CACHE_VAL (1 << 29)
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#define GPR4_VDOA_RD_CACHE_SEL (1 << 30)
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#define GPR4_VDOA_WR_CACHE_SEL (1 << 31)
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/* General Purpose Register 5 (GPR5) */
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#define GPR5_ARM_WFI_SHIFT (0)
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#define GPR5_ARM_WFI_MASK (15 << GPR5_ARM_WFI_SHIFT)
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#define GPR5_ARM_WFE_SHIFT (4)
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#define GPR5_ARM_WFE_MASK (15 << GPR5_ARM_WFE_SHIFT)
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#define GPR5_L2_CLK_STOP (1 << 8)
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/* General Purpose Register 6 (GPR6) */
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#define GPR6_IPU1_ID00_WR_QOS_SHIFT (0)
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#define GPR6_IPU1_ID00_WR_QOS_MASK (15 << GPR6_IPU1_ID00_WR_QOS_SHIFT)
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# define GPR6_IPU1_ID00_WR_QOS(n) ((uint32_t)(n) << GPR6_IPU1_ID00_WR_QOS_SHIFT)
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#define GPR6_IPU1_ID01_WR_QOS_SHIFT (4)
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#define GPR6_IPU1_ID01_WR_QOS_MASK (15 << GPR6_IPU1_ID01_WR_QOS_SHIFT)
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# define GPR6_IPU1_ID01_WR_QOS(n) ((uint32_t)(n) << GPR6_IPU1_ID01_WR_QOS_SHIFT)
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#define GPR6_IPU1_ID10_WR_QOS_SHIFT (8)
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#define GPR6_IPU1_ID10_WR_QOS_MASK (15 << GPR6_IPU1_ID10_WR_QOS_SHIFT)
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# define GPR6_IPU1_ID10_WR_QOS(n) ((uint32_t)(n) << GPR6_IPU1_ID10_WR_QOS_SHIFT)
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#define GPR6_IPU1_ID11_WR_QOS_SHIFT (12)
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#define GPR6_IPU1_ID11_WR_QOS_MASK (15 << GPR6_IPU1_ID11_WR_QOS_SHIFT)
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# define GPR6_IPU1_ID11_WR_QOS(n) ((uint32_t)(n) << GPR6_IPU1_ID11_WR_QOS_SHIFT)
|
||||
#define GPR6_IPU1_ID00_RD_QOS_SHIFT (16)
|
||||
#define GPR6_IPU1_ID00_RD_QOS_MASK (15 << GPR6_IPU1_ID00_RD_QOS_SHIFT)
|
||||
# define GPR6_IPU1_ID00_RD_QOS(n) ((uint32_t)(n) << GPR6_IPU1_ID00_RD_QOS_SHIFT)
|
||||
#define GPR6_IPU1_ID01_RD_QOS_SHIFT (20)
|
||||
#define GPR6_IPU1_ID01_RD_QOS_MASK (15 << GPR6_IPU1_ID01_RD_QOS_SHIFT)
|
||||
# define GPR6_IPU1_ID01_RD_QOS(n) ((uint32_t)(n) << GPR6_IPU1_ID01_RD_QOS_SHIFT)
|
||||
#define GPR6_IPU1_ID10_RD_QOS_SHIFT (24)
|
||||
#define GPR6_IPU1_ID10_RD_QOS_MASK (15 << GPR6_IPU1_ID10_RD_QOS_SHIFT)
|
||||
# define GPR6_IPU1_ID10_RD_QOS(n) ((uint32_t)(n) << GPR6_IPU1_ID10_RD_QOS_SHIFT)
|
||||
#define GPR6_IPU1_ID11_RD_QOS_SHIFT (28)
|
||||
#define GPR6_IPU1_ID11_RD_QOS_MASK (15 << GPR6_IPU1_ID11_RD_QOS_SHIFT)
|
||||
# define GPR6_IPU1_ID11_RD_QOS(n) ((uint32_t)(n) << GPR6_IPU1_ID11_RD_QOS_SHIFT)
|
||||
|
||||
/* General Purpose Register 7 (GPR7) */
|
||||
|
||||
#define GPR7_IPU2_ID00_WR_QOS_SHIFT (0)
|
||||
#define GPR7_IPU2_ID00_WR_QOS_MASK (15 << GPR7_IPU2_ID00_WR_QOS_SHIFT)
|
||||
# define GPR7_IPU2_ID00_WR_QOS(n) ((uint32_t)(n) << GPR7_IPU2_ID00_WR_QOS_SHIFT)
|
||||
#define GPR7_IPU2_ID01_WR_QOS_SHIFT (4)
|
||||
#define GPR7_IPU2_ID01_WR_QOS_MASK (15 << GPR7_IPU2_ID01_WR_QOS_SHIFT)
|
||||
# define GPR7_IPU2_ID01_WR_QOS(n) ((uint32_t)(n) << GPR7_IPU2_ID01_WR_QOS_SHIFT)
|
||||
#define GPR7_IPU2_ID10_WR_QOS_SHIFT (8)
|
||||
#define GPR7_IPU2_ID10_WR_QOS_MASK (15 << GPR7_IPU2_ID10_WR_QOS_SHIFT)
|
||||
# define GPR7_IPU2_ID10_WR_QOS(n) ((uint32_t)(n) << GPR7_IPU2_ID10_WR_QOS_SHIFT)
|
||||
#define GPR7_IPU2_ID11_WR_QOS_SHIFT (12)
|
||||
#define GPR7_IPU2_ID11_WR_QOS_MASK (15 << GPR7_IPU2_ID11_WR_QOS_SHIFT)
|
||||
# define GPR7_IPU2_ID11_WR_QOS(n) ((uint32_t)(n) << GPR7_IPU2_ID11_WR_QOS_SHIFT)
|
||||
#define GPR7_IPU2_ID00_RD_QOS_SHIFT (16)
|
||||
#define GPR7_IPU2_ID00_RD_QOS_MASK (15 << GPR7_IPU2_ID00_RD_QOS_SHIFT)
|
||||
# define GPR7_IPU2_ID00_RD_QOS(n) ((uint32_t)(n) << GPR7_IPU2_ID00_RD_QOS_SHIFT)
|
||||
#define GPR7_IPU2_ID01_RD_QOS_SHIFT (20)
|
||||
#define GPR7_IPU2_ID01_RD_QOS_MASK (15 << GPR7_IPU2_ID01_RD_QOS_SHIFT)
|
||||
# define GPR7_IPU2_ID01_RD_QOS(n) ((uint32_t)(n) << GPR7_IPU2_ID01_RD_QOS_SHIFT)
|
||||
#define GPR7_IPU2_ID10_RD_QOS_SHIFT (24)
|
||||
#define GPR7_IPU2_ID10_RD_QOS_MASK (15 << GPR7_IPU2_ID10_RD_QOS_SHIFT)
|
||||
# define GPR7_IPU2_ID10_RD_QOS(n) ((uint32_t)(n) << GPR7_IPU2_ID10_RD_QOS_SHIFT)
|
||||
#define GPR7_IPU2_ID11_RD_QOS_SHIFT (28)
|
||||
#define GPR7_IPU2_ID11_RD_QOS_MASK (15 << GPR7_IPU2_ID11_RD_QOS_SHIFT)
|
||||
# define GPR7_IPU2_ID11_RD_QOS(n) ((uint32_t)(n) << GPR7_IPU2_ID11_RD_QOS_SHIFT)
|
||||
|
||||
/* General Purpose Register 8 (GPR8) */
|
||||
|
||||
#define GPR8_PCS_TX_DEEMPH_GEN1_SHIFT (0)
|
||||
#define GPR8_PCS_TX_DEEMPH_GEN1_MASK (0x3f << GPR8_PCS_TX_DEEMPH_GEN1_SHIFT)
|
||||
# define GPR8_PCS_TX_DEEMPH_GEN1(n) ((uint32_t)(n) << GPR8_PCS_TX_DEEMPH_GEN1_SHIFT)
|
||||
#define GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_SHIFT (6)
|
||||
#define GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_MASK (0x3f << GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_SHIFT)
|
||||
# define GPR8_PCS_TX_DEEMPH_GEN2_3P5DB(n) ((uint32_t)(n) << GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_SHIFT)
|
||||
#define GPR8_PCS_TX_DEEMPH_GEN2_6DB_SHIFT (12)
|
||||
#define GPR8_PCS_TX_DEEMPH_GEN2_6DB_MASK (0x3f << GPR8_PCS_TX_DEEMPH_GEN2_6DB_SHIFT)
|
||||
# define GPR8_PCS_TX_DEEMPH_GEN2_6DB(n) ((uint32_t)(n) << GPR8_PCS_TX_DEEMPH_GEN2_6DB_SHIFT)
|
||||
#define GPR8_PCS_TX_SWING_FULL_SHIFT (18)
|
||||
#define GPR8_PCS_TX_SWING_FULL_MASK (0x7f << GPR8_PCS_TX_SWING_FULL_SHIFT)
|
||||
# define GPR8_PCS_TX_SWING_FULL(n) ((uint32_t)(n) << GPR8_PCS_TX_SWING_FULL_SHIFT)
|
||||
#define GPR8_PCS_TX_SWING_LOW_SHIFT (25)
|
||||
#define GPR8_PCS_TX_SWING_LOW_MASK (0x7f << GPR8_PCS_TX_SWING_LOW_SHIFT)
|
||||
# define GPR8_PCS_TX_SWING_LOW(n) ((uint32_t)(n) << GPR8_PCS_TX_SWING_LOW_SHIFT)
|
||||
|
||||
/* General Purpose Register 9 (GPR9) */
|
||||
|
||||
#define GPR9_TZASC1_BYP (1 << 0)
|
||||
#define GPR9_TZASC2_BYP (1 << 1)
|
||||
|
||||
/* General Purpose Register 10 (GPR10) */
|
||||
|
||||
#define GPR10_DCIC1_MUX_CTL_SHIFT (0)
|
||||
#define GPR10_DCIC1_MUX_CTL_MASK (3 << GPR10_DCIC1_MUX_CTL_SHIFT)
|
||||
# define GPR10_DCIC1_MUX_CTL_IPU1_DI0 (0 << GPR10_DCIC1_MUX_CTL_SHIFT)
|
||||
# define GPR10_DCIC1_MUX_CTL_IPU1_DI1 (1 << GPR10_DCIC1_MUX_CTL_SHIFT)
|
||||
# define GPR10_DCIC1_MUX_CTL_IPU2_DI0 (2 << GPR10_DCIC1_MUX_CTL_SHIFT)
|
||||
# define GPR10_DCIC1_MUX_CTL_IPU2_DI1 (3 << GPR10_DCIC1_MUX_CTL_SHIFT)
|
||||
#define GPR10_DCIC2_MUX_CTL_SHIFT (2)
|
||||
#define GPR10_DCIC2_MUX_CTL_MASK (3 << GPR10_DCIC2_MUX_CTL_SHIFT)
|
||||
# define GPR10_DCIC2_MUX_CTL_IPU1_DI0 (0 << GPR10_DCIC2_MUX_CTL_SHIFT)
|
||||
# define GPR10_DCIC2_MUX_CTL_IPU1_DI1 (1 << GPR10_DCIC2_MUX_CTL_SHIFT)
|
||||
# define GPR10_DCIC2_MUX_CTL_IPU2_DI0 (2 << GPR10_DCIC2_MUX_CTL_SHIFT)
|
||||
# define GPR10_DCIC2_MUX_CTL_IPU2_DI1 (3 << GPR10_DCIC2_MUX_CTL_SHIFT)
|
||||
#define GPR10_OCRAM_TZ_EN (1 << 4)
|
||||
#define GPR10_OCRAM_TZ_ADDR_SHIFT (5)
|
||||
#define GPR10_OCRAM_TZ_ADDR_MASK (0x3f << GPR10_OCRAM_TZ_ADDR_SHIFT)
|
||||
# define GPR10_OCRAM_TZ_ADDR(n) ((uint32_t)(n) << GPR10_OCRAM_TZ_ADDR_SHIFT)
|
||||
#define GPR10_SEC_ERR_RESP (1 << 11)
|
||||
#define GPR10_DBG_CLK_EN (1 << 12)
|
||||
#define GPR10_DBG_EN (1 << 13)
|
||||
#define GPR10_LOCK_DCIC1_MUX_SHIFT (16)
|
||||
#define GPR10_LOCK_DCIC1_MUX_MASK (3 << GPR10_LOCK_DCIC1_MUX_SHIFT)
|
||||
# define GPR10_LOCK_DCIC1_MUX_IPU1 (0 << GPR10_LOCK_DCIC1_MUX_SHIFT) /* DCIC-1 source is IPU1 or IPU2 DI0 port */
|
||||
# define GPR10_LOCK_DCIC1_MUX_LVDS0 (1 << GPR10_LOCK_DCIC1_MUX_SHIFT) /* DCIC-1 source is LVDS0 */
|
||||
# define GPR10_LOCK_DCIC1_MUX_LVDS1 (2 << GPR10_LOCK_DCIC1_MUX_SHIFT) /* DCIC-1 source is LVDS1 */
|
||||
# define GPR10_LOCK_DCIC1_MUX_MIPI (3 << GPR10_LOCK_DCIC1_MUX_SHIFT) /* DCIC-1 source is MIPI DPI */
|
||||
#define GPR10_LOCK_DCIC2_MUX_SHIFT (18)
|
||||
#define GPR10_LOCK_DCIC2_MUX_MASK (3 << GPR10_LOCK_DCIC2_MUX_SHIFT)
|
||||
# define GPR10_LOCK_DCIC2_MUX_IPU1 (0 << GPR10_LOCK_DCIC2_MUX_SHIFT) /* DCIC-2 source is IPU1 DI1 port */
|
||||
# define GPR10_LOCK_DCIC2_MUX_LVDS0 (1 << GPR10_LOCK_DCIC2_MUX_SHIFT) /* DCIC-2 source is LVDS0 */
|
||||
# define GPR10_LOCK_DCIC2_MUX_LVDS1 (2 << GPR10_LOCK_DCIC2_MUX_SHIFT) /* DCIC-2 source is LVDS1 */
|
||||
# define GPR10_LOCK_DCIC2_MUX_MIPI (3 << GPR10_LOCK_DCIC2_MUX_SHIFT) /* DCIC-2 source is MIPI DPI */
|
||||
#define GPR10_LOCK_OCRAM_TZ_EN (1 << 20)
|
||||
#define GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT (21)
|
||||
#define GPR10_LOCK_OCRAM_TZ_ADDR_MASK (0x3f << GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)
|
||||
# define GPR10_LOCK_OCRAM_TZ_ADDR(n) ((uint32_t)(n) << GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)
|
||||
#define GPR10_LOCK_SEC_ERR_RESP (1 << 27)
|
||||
#define GPR10_LOCK_DBG_CLK_EN (1 << 28)
|
||||
#define GPR10_LOCK_DBG_EN (1 << 29)
|
||||
|
||||
/* General Purpose Register 11 (GPR11) -- Contains no fields of interest. */
|
||||
/* General Purpose Register 12 (GPR12) */
|
||||
|
||||
#define GPR12_USDHC_DBG_MUX_SHIFT (2)
|
||||
#define GPR12_USDHC_DBG_MUX_MASK (3 << GPR12_USDHC_DBG_MUX_SHIFT)
|
||||
# define GPR12_USDHC_DBG_MUX_USDHC1 (0 << GPR12_USDHC_DBG_MUX_SHIFT) /* uSDHC1 debug */
|
||||
# define GPR12_USDHC_DBG_MUX_USDHC2 (1 << GPR12_USDHC_DBG_MUX_SHIFT) /* uSDHC2 debug */
|
||||
# define GPR12_USDHC_DBG_MUX_USDHC3 (2 << GPR12_USDHC_DBG_MUX_SHIFT) /* uSDHC3 debug */
|
||||
# define GPR12_USDHC_DBG_MUX_USDHC4 (3 << GPR12_USDHC_DBG_MUX_SHIFT) /* uSDHC4 debug */
|
||||
#define GPR12_LOS_LEVEL_SHIFT (4)
|
||||
#define GPR12_LOS_LEVEL_MASK (0x1f << GPR12_LOS_LEVEL_SHIFT)
|
||||
# define GPR12_LOS_LEVEL(n) ((uint32_t)(n) << GPR12_LOS_LEVEL_SHIFT)
|
||||
#define GPR12_APPS_PM_XMT_PME (1 << 9)
|
||||
#define GPR12_APP_LTSSM_ENABLE (1 << 10)
|
||||
#define GPR12_APP_INIT_RST (1 << 11)
|
||||
#define GPR12_DEVICE_TYPE_SHIFT (12)
|
||||
#define GPR12_DEVICE_TYPE_MASK (15 << GPR12_DEVICE_SHIFT)
|
||||
# define GPR12_DEVICE_TYPE_PCIE_EP (0 << GPR12_DEVICE_SHIFT) /* EP mode */
|
||||
# define GPR12_DEVICE_TYPE_PCIE_RC (2 << GPR12_DEVICE_SHIFT) /* RC mode */
|
||||
#define GPR12_APPS_PM_XMT_TURNOFF (1 << 16)
|
||||
#define GPR12_DIA_STATUS_BUS_SELECT_SHIFT (17)
|
||||
#define GPR12_DIA_STATUS_BUS_SELECT_MASK (15 << GPR12_DIA_STATUS_BUS_SELECT_SHIFT)
|
||||
# define GPR12_DIA_STATUS_BUS_SELECT(n) ((uint32_t)(n) << GPR12_DIA_STATUS_BUS_SELECT_SHIFT)
|
||||
#define GPR12_PCIE_CTL_7_SHIFT (21)
|
||||
#define GPR12_PCIE_CTL_7_MASK (7 << GPR12_PCIE_CTL_7_SHIFT)
|
||||
#define GPR12_PCIE_CTL_7(n) ((uint32_t)(n) << GPR12_PCIE_CTL_7_SHIFT)
|
||||
#define GPR12_ARMP_APB_CLK_EN (1 << 24)
|
||||
#define GPR12_ARMP_ATB_CLK_EN (1 << 25)
|
||||
#define GPR12_ARMP_AHB_CLK_EN (1 << 26)
|
||||
#define GPR12_ARMP_IPG_CLK_EN (1 << 27)
|
||||
|
||||
/* General Purpose Register 13 (GPR13) */
|
||||
|
||||
#define GPR13_SATA_PHY_0 (1 << 0)
|
||||
#define GPR13_SATA_PHY_1 (1 << 1)
|
||||
#define GPR13_SATA_PHY_2_SHIFT (2)
|
||||
#define GPR13_SATA_PHY_2_MASK (0x1f << GPR13_SATA_PHY_2_SHIFT)
|
||||
# define GPR13_SATA_PHY_2_0p937_V (0x00 << GPR13_SATA_PHY_2_SHIFT)
|
||||
# define GPR13_SATA_PHY_2_0p947_V (0x01 << GPR13_SATA_PHY_2_SHIFT)
|
||||
# define GPR13_SATA_PHY_2_0p957_V (0x02 << GPR13_SATA_PHY_2_SHIFT)
|
||||
# define GPR13_SATA_PHY_2_0p966_V (0x03 << GPR13_SATA_PHY_2_SHIFT)
|
||||
# define GPR13_SATA_PHY_2_0p976_V (0x04 << GPR13_SATA_PHY_2_SHIFT)
|
||||
# define GPR13_SATA_PHY_2_0p986_V (0x05 << GPR13_SATA_PHY_2_SHIFT)
|
||||
# define GPR13_SATA_PHY_2_0p996_V (0x06 << GPR13_SATA_PHY_2_SHIFT)
|
||||
# define GPR13_SATA_PHY_2_1p005_V (0x07 << GPR13_SATA_PHY_2_SHIFT)
|
||||
# define GPR13_SATA_PHY_2_1p015_V (0x08 << GPR13_SATA_PHY_2_SHIFT)
|
||||
# define GPR13_SATA_PHY_2_1p025_V (0x09 << GPR13_SATA_PHY_2_SHIFT)
|
||||
# define GPR13_SATA_PHY_2_1p035_V (0x0a << GPR13_SATA_PHY_2_SHIFT)
|
||||
# define GPR13_SATA_PHY_2_1p045_V (0x0b << GPR13_SATA_PHY_2_SHIFT)
|
||||
# define GPR13_SATA_PHY_2_1p054_V (0x0c << GPR13_SATA_PHY_2_SHIFT)
|
||||
# define GPR13_SATA_PHY_2_1p064_V (0x0d << GPR13_SATA_PHY_2_SHIFT)
|
||||
# define GPR13_SATA_PHY_2_1p074_V (0x0e << GPR13_SATA_PHY_2_SHIFT)
|
||||
# define GPR13_SATA_PHY_2_1p084_V (0x0f << GPR13_SATA_PHY_2_SHIFT)
|
||||
# define GPR13_SATA_PHY_2_1p094_V (0x10 << GPR13_SATA_PHY_2_SHIFT)
|
||||
# define GPR13_SATA_PHY_2_1p104_V (0x11 << GPR13_SATA_PHY_2_SHIFT)
|
||||
# define GPR13_SATA_PHY_2_1p113_V (0x12 << GPR13_SATA_PHY_2_SHIFT)
|
||||
# define GPR13_SATA_PHY_2_1p123_V (0x13 << GPR13_SATA_PHY_2_SHIFT)
|
||||
# define GPR13_SATA_PHY_2_1p133_V (0x14 << GPR13_SATA_PHY_2_SHIFT)
|
||||
# define GPR13_SATA_PHY_2_1p143_V (0x15 << GPR13_SATA_PHY_2_SHIFT)
|
||||
# define GPR13_SATA_PHY_2_1p152_V (0x16 << GPR13_SATA_PHY_2_SHIFT)
|
||||
# define GPR13_SATA_PHY_2_1p162_V (0x17 << GPR13_SATA_PHY_2_SHIFT)
|
||||
# define GPR13_SATA_PHY_2_1p172_V (0x18 << GPR13_SATA_PHY_2_SHIFT)
|
||||
# define GPR13_SATA_PHY_2_1p182_V (0x19 << GPR13_SATA_PHY_2_SHIFT)
|
||||
# define GPR13_SATA_PHY_2_1p191_V (0x1a << GPR13_SATA_PHY_2_SHIFT)
|
||||
# define GPR13_SATA_PHY_2_1p201_V (0x1b << GPR13_SATA_PHY_2_SHIFT)
|
||||
# define GPR13_SATA_PHY_2_1p211_V (0x1c << GPR13_SATA_PHY_2_SHIFT)
|
||||
# define GPR13_SATA_PHY_2_1p221_V (0x1d << GPR13_SATA_PHY_2_SHIFT)
|
||||
# define GPR13_SATA_PHY_2_1p230_V (0x1e << GPR13_SATA_PHY_2_SHIFT)
|
||||
# define GPR13_SATA_PHY_2_1p240_V (0x1f << GPR13_SATA_PHY_2_SHIFT)
|
||||
#define GPR13_SATA_PHY_3_SHIFT (7)
|
||||
#define GPR13_SATA_PHY_3_MASK (15 << GPR13_SATA_PHY_3_SHIFT)
|
||||
# define GPR13_SATA_PHY_3_0p00_DB (0 << GPR13_SATA_PHY_3_SHIFT)
|
||||
# define GPR13_SATA_PHY_3_0p37_DB (1 << GPR13_SATA_PHY_3_SHIFT)
|
||||
# define GPR13_SATA_PHY_3_0p74_DB (2 << GPR13_SATA_PHY_3_SHIFT)
|
||||
# define GPR13_SATA_PHY_3_1p11_DB (3 << GPR13_SATA_PHY_3_SHIFT)
|
||||
# define GPR13_SATA_PHY_3_1p48_DB (4 << GPR13_SATA_PHY_3_SHIFT)
|
||||
# define GPR13_SATA_PHY_3_1p85_DB (5 << GPR13_SATA_PHY_3_SHIFT)
|
||||
# define GPR13_SATA_PHY_3_2p22_DB (6 << GPR13_SATA_PHY_3_SHIFT)
|
||||
# define GPR13_SATA_PHY_3_2p59_DB (7 << GPR13_SATA_PHY_3_SHIFT)
|
||||
# define GPR13_SATA_PHY_3_2p96_DB (8 << GPR13_SATA_PHY_3_SHIFT)
|
||||
# define GPR13_SATA_PHY_3_3p33_DB (9 << GPR13_SATA_PHY_3_SHIFT)
|
||||
# define GPR13_SATA_PHY_3_3p70_DB (10 << GPR13_SATA_PHY_3_SHIFT)
|
||||
# define GPR13_SATA_PHY_3_4p07_DB (11 << GPR13_SATA_PHY_3_SHIFT)
|
||||
# define GPR13_SATA_PHY_3_4p44_DB (12 << GPR13_SATA_PHY_3_SHIFT)
|
||||
# define GPR13_SATA_PHY_3_4p81_DB (13 << GPR13_SATA_PHY_3_SHIFT)
|
||||
# define GPR13_SATA_PHY_3_5p28_DB (14 << GPR13_SATA_PHY_3_SHIFT)
|
||||
# define GPR13_SATA_PHY_3_5p75_DB (15 << GPR13_SATA_PHY_3_SHIFT)
|
||||
#define GPR13SATA_PHY_4_SHIFT (11)
|
||||
#define GPR13SATA_PHY_4_MASK (7 << GPR13SATA_PHY_4_SHIFT)
|
||||
# define GPR13SATA_PHY_4_16_16 (0 << GPR13SATA_PHY_4_SHIFT) /* 16/16 */
|
||||
# define GPR13SATA_PHY_4_14_16 (1 << GPR13SATA_PHY_4_SHIFT) /* 14/16 */
|
||||
# define GPR13SATA_PHY_4_12_16 (2 << GPR13SATA_PHY_4_SHIFT) /* 12/16 */
|
||||
# define GPR13SATA_PHY_4_10_16 (3 << GPR13SATA_PHY_4_SHIFT) /* 10/16 */
|
||||
# define GPR13SATA_PHY_4_9_16 (4 << GPR13SATA_PHY_4_SHIFT) /* 9/16 (default) */
|
||||
# define GPR13SATA_PHY_4_8_16 (5 << GPR13SATA_PHY_4_SHIFT) /* 8/16 */
|
||||
#define GPR13_SATA_PHY_5 (1 << 14)
|
||||
# define GPR13_SATA_PHY_5_SSEN (1 << 14)
|
||||
#define GPR13_SATA_SPEED (1 << 15)
|
||||
#define GPR13_SSATA_PHY_6_SHIFT (16)
|
||||
#define GPR13_SSATA_PHY_6_MASK (7 << GPR13_SSATA_PHY_6_SHIFT)
|
||||
# define GPR13_SSATA_PHY_6_1P_1F (0 << GPR13_SSATA_PHY_6_SHIFT)
|
||||
# define GPR13_SSATA_PHY_6_2P_2F (1 << GPR13_SSATA_PHY_6_SHIFT)
|
||||
# define GPR13_SSATA_PHY_6_1P_4F (2 << GPR13_SSATA_PHY_6_SHIFT)
|
||||
# define GPR13_SSATA_PHY_6_2P_4F (3 << GPR13_SSATA_PHY_6_SHIFT)
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#define GPR13_SATA_PHY_7_SHIFT (19)
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#define GPR13_SATA_PHY_7_MASK (0x1f << GPR13_SATA_PHY_7_SHIFT)
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# define GPR13_SATA_PHY_7_SATA1I (0x10 << GPR13_SATA_PHY_7_SHIFT)
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# define GPR13_SATA_PHY_7_SATA1M (0x10 << GPR13_SATA_PHY_7_SHIFT)
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# define GPR13_SATA_PHY_7_SATA1X (0x1a << GPR13_SATA_PHY_7_SHIFT)
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# define GPR13_SATA_PHY_7_SATA2I (0x12 << GPR13_SATA_PHY_7_SHIFT)
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# define GPR13_SATA_PHY_7_SATA2M (0x12 << GPR13_SATA_PHY_7_SHIFT)
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# define GPR13_SATA_PHY_7_SATA2X (0x1a << GPR13_SATA_PHY_7_SHIFT)
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#define GPR13_SATA_PHY_8_SHIFT (24)
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#define GPR13_SATA_PHY_8_MASK (7 << GPR13_SATA_PHY_8_SHIFT)
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# define GPR13_SATA_PHY_8_0p5_DB (0 << GPR13_SATA_PHY_8_SHIFT)
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# define GPR13_SATA_PHY_8_1p0_DB (1 << GPR13_SATA_PHY_8_SHIFT)
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# define GPR13_SATA_PHY_8_1p5_DB (2 << GPR13_SATA_PHY_8_SHIFT)
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# define GPR13_SATA_PHY_8_2p0_DB (3 << GPR13_SATA_PHY_8_SHIFT)
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# define GPR13_SATA_PHY_8_2p5_DB (4 << GPR13_SATA_PHY_8_SHIFT)
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# define GPR13_SATA_PHY_8_3p0_DB (5 << GPR13_SATA_PHY_8_SHIFT)
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# define GPR13_SATA_PHY_8_3p5_DB (6 << GPR13_SATA_PHY_8_SHIFT)
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# define GPR13_SATA_PHY_8_4p0_DB (7 << GPR13_SATA_PHY_8_SHIFT)
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#define GPR13_ENET_STOP_REQ (1 << 27)
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#define GPR13_CAN1_STOP_REQ (1 << 28)
|
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#define GPR13_CAN2_STOP_REQ (1 << 29)
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#define GPR13_SDMA_STOP_REQ (1 << 30)
|
||||
|
||||
/* Pad Mux Registers */
|
||||
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user