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arch/arm/src/lpc17xx_40xx/lpc17_40_can.c: f BOARD_CCLKSEL_DIVIDER is not equal to 1 on LPC178x or LPC40xx then base clock rate is calculated incorrectly because CCLK frequency does not correspond to PLL0 clock which is used for PCLK. This is partially workaround solution. It would be probably better to define BOARD_PCLK_FREQUENCY even for LPC176x targets and use that to replace divisor by base_clock in up_dev_s.

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This commit is contained in:
Pavel Pisa 2019-08-13 16:16:49 -06:00 committed by Gregory Nutt
parent fd237a87d1
commit 913de5e216
1 changed files with 6 additions and 1 deletions
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arch/arm/src/lpc17xx_40xx/lpc17_40_can.c
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@ -167,7 +167,12 @@
/* Timing *******************************************************************/
/* CAN clocking is provided at CCLK divided by the configured divisor */
#define CAN_CLOCK_FREQUENCY(d) ((uint32_t)LPC17_40_CCLK / (uint32_t)(d))
#ifdef BOARD_CCLKSEL_DIVIDER
# define CAN_CLOCK_FREQUENCY(d) \
((uint32_t)LPC17_40_CCLK * BOARD_CCLKSEL_DIVIDER / (uint32_t)(d))
#else
# define CAN_CLOCK_FREQUENCY(d) ((uint32_t)LPC17_40_CCLK / (uint32_t)(d))
#endif
/****************************************************************************
* Private Types