Add SAM4L BSCIF register definition file
This commit is contained in:
Gregory Nutt
parent
1029074cc6
commit
9149253356
316
arch/arm/src/sam34/chip/sam4l_bscif.h
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arch/arm/src/sam34/chip/sam4l_bscif.h
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/****************************************************************************************
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* arch/arm/src/sam34/chip/sam4l_bscif.h
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_BSCIF_H
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#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_BSCIF_H
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/****************************************************************************************
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* Included Files
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****************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "chip/sam_memorymap.h"
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/****************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************/
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/* BSCIF register offsets ***************************************************************/
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#define SAM_BSCIF_IER_OFFSET 0x0000 /* Interrupt Enable Register */
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#define SAM_BSCIF_IDR_OFFSET 0x0004 /* Interrupt Disable Register */
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#define SAM_BSCIF_IMR_OFFSET 0x0008 /* Interrupt Mask Register */
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#define SAM_BSCIF_ISR_OFFSET 0x000c /* Interrupt Status Register */
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#define SAM_BSCIF_ICR_OFFSET 0x0010 /* Interrupt Clear Register */
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#define SAM_BSCIF_PCLKSR_OFFSET 0x0014 /* Power and Clocks Status Register */
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#define SAM_BSCIF_UNLOCK_OFFSET 0x0018 /* Unlock Register */
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#define SAM_BSCIF_CSCR_OFFSET 0x001c /* Chip Specific Configuration Register */
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#define SAM_BSCIF_OSCCTRL32_OFFSET 0x0020 /* Oscillator 32 Control Register */
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#define SAM_BSCIF_RC32KCR_OFFSET 0x0024 /* 32kHz RC Oscillator Control Register */
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#define SAM_BSCIF_RC32KTUNE_OFFSET 0x0028 /* 32kHz RC Oscillator Tuning Register */
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#define SAM_BSCIF_BOD33CTRL_OFFSET 0x002c /* BOD33 Control Register */
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#define SAM_BSCIF_BOD33LEVEL_OFFSET 0x0030 /* BOD33 Level Register */
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#define SAM_BSCIF_BOD33SAMPLING_OFFSET 0x0034 /* BOD33 Sampling Control Register */
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#define SAM_BSCIF_BOD18CTRL_OFFSET 0x0038 /* BOD18 Control Register */
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#define SAM_BSCIF_BOD18LEVEL_OFFSET 0x003c /* BOD18 Level Register */
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#define SAM_BSCIF_BOD18SAMPLING_OFFSET 0x0040 /* BOD18 Sampling Control Register */
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#define SAM_BSCIF_VREGCR_OFFSET 0x0044 /* Voltage Regulator Configuration Register */
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#define SAM_BSCIF_RC1MCR_OFFSET 0x0058 /* 1MHz RC Clock Configuration Register */
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#define SAM_BSCIF_BGCTRL_OFFSET 0x0060 /* Bandgap Control Register */
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#define SAM_BSCIF_BGS_OFFSET 0x0064 /* Bandgap Status Register */
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#define SAM_BSCIF_BR_OFFSET(n) (0x0078+((n)<<2) /* 0x0078-0x0084 Backup register n=0..3 */
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#define SAM_BSCIF_BR0_OFFSET 0x0078 /* Backup register 0 */
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#define SAM_BSCIF_BR1_OFFSET 0x007c /* Backup register 1 */
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#define SAM_BSCIF_BR2_OFFSET 0x0080 /* Backup register 2 */
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#define SAM_BSCIF_BR3_OFFSET 0x0004 /* Backup register 3 */
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#define SAM_BSCIF_BRIFBVERSION_OFFSET 0x03e4 /* Backup Register Interface Version Register */
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#define SAM_BSCIF_BGREFIFBVERSION_OFFSET 0x03e8 /* BGREFIF Version Register */
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#define SAM_BSCIF_VREGIFGVERSION_OFFSET 0x03ec /* Voltage Regulator Version Register */
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#define SAM_BSCIF_BODIFCVERSION_OFFSET 0x03f0 /* BOD Version Register */
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#define SAM_BSCIF_RC32KIFBVERSION_OFFSET 0x03f4 /* 32kHz RC Oscillator Version Register */
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#define SAM_BSCIF_OSC32IFAVERSION_OFFSET 0x03f8 /* 32 kHz Oscillator Version Register */
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#define SAM_BSCIF_VERSION_OFFSET 0x03fc /* BSCIF Version Register */
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/* BSCIF register adresses **************************************************************/
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#define SAM_BSCIF_IER (SAM_BSCIF_BASE+SAM_BSCIF_IER_OFFSET)
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#define SAM_BSCIF_IDR (SAM_BSCIF_BASE+SAM_BSCIF_IDR_OFFSET)
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#define SAM_BSCIF_IMR (SAM_BSCIF_BASE+SAM_BSCIF_IMR_OFFSET)
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#define SAM_BSCIF_ISR (SAM_BSCIF_BASE+SAM_BSCIF_ISR_OFFSET)
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#define SAM_BSCIF_ICR (SAM_BSCIF_BASE+SAM_BSCIF_ICR_OFFSET)
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#define SAM_BSCIF_PCLKSR (SAM_BSCIF_BASE+SAM_BSCIF_PCLKSR_OFFSET)
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#define SAM_BSCIF_UNLOCK (SAM_BSCIF_BASE+SAM_BSCIF_UNLOCK_OFFSET)
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#define SAM_BSCIF_CSCR (SAM_BSCIF_BASE+SAM_BSCIF_CSCR_OFFSET)
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#define SAM_BSCIF_OSCCTRL32 (SAM_BSCIF_BASE+SAM_BSCIF_OSCCTRL32_OFFSET)
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#define SAM_BSCIF_RC32KCR (SAM_BSCIF_BASE+SAM_BSCIF_RC32KCR_OFFSET)
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#define SAM_BSCIF_RC32KTUNE (SAM_BSCIF_BASE+SAM_BSCIF_RC32KTUNE_OFFSET)
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#define SAM_BSCIF_BOD33CTRL (SAM_BSCIF_BASE+SAM_BSCIF_BOD33CTRL_OFFSET)
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#define SAM_BSCIF_BOD33LEVEL (SAM_BSCIF_BASE+SAM_BSCIF_BOD33LEVEL_OFFSET)
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#define SAM_BSCIF_BOD33SAMPLING (SAM_BSCIF_BASE+SAM_BSCIF_BOD33SAMPLING_OFFSET)
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#define SAM_BSCIF_BOD18CTRL (SAM_BSCIF_BASE+SAM_BSCIF_BOD18CTRL_OFFSET)
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#define SAM_BSCIF_BOD18LEVEL (SAM_BSCIF_BASE+SAM_BSCIF_BOD18LEVEL_OFFSET)
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#define SAM_BSCIF_BOD18SAMPLING (SAM_BSCIF_BASE+SAM_BSCIF_BOD18SAMPLING_OFFSET)
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#define SAM_BSCIF_VREGCR (SAM_BSCIF_BASE+SAM_BSCIF_VREGCR_OFFSET)
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#define SAM_BSCIF_RC1MCR (SAM_BSCIF_BASE+SAM_BSCIF_RC1MCR_OFFSET)
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#define SAM_BSCIF_BGCTRL (SAM_BSCIF_BASE+SAM_BSCIF_BGCTRL_OFFSET)
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#define SAM_BSCIF_BGS (SAM_BSCIF_BASE+SAM_BSCIF_BGS_OFFSET)
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#define SAM_BSCIF_BR(n) (SAM_BSCIF_BASE+SAM_BSCIF_BR_OFFSET(n))
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#define SAM_BSCIF_BR0 (SAM_BSCIF_BASE+SAM_BSCIF_BR0_OFFSET)
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#define SAM_BSCIF_BR1 (SAM_BSCIF_BASE+SAM_BSCIF_BR1_OFFSET)
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#define SAM_BSCIF_BR2 (SAM_BSCIF_BASE+SAM_BSCIF_BR2_OFFSET)
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#define SAM_BSCIF_BR3 (SAM_BSCIF_BASE+SAM_BSCIF_BR3_OFFSET)
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#define SAM_BSCIF_BRIFBVERSION (SAM_BSCIF_BASE+SAM_BSCIF_BRIFBVERSION_OFFSET)
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#define SAM_BSCIF_BGREFIFBVERSION (SAM_BSCIF_BASE+SAM_BSCIF_BGREFIFBVERSION_OFFSET)
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#define SAM_BSCIF_VREGIFGVERSION (SAM_BSCIF_BASE+SAM_BSCIF_VREGIFGVERSION_OFFSET)
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#define SAM_BSCIF_BODIFCVERSION (SAM_BSCIF_BASE+SAM_BSCIF_BODIFCVERSION_OFFSET)
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#define SAM_BSCIF_RC32KIFBVERSION (SAM_BSCIF_BASE+SAM_BSCIF_RC32KIFBVERSION_OFFSET)
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#define SAM_BSCIF_OSC32IFAVERSION (SAM_BSCIF_BASE+SAM_BSCIF_OSC32IFAVERSION_OFFSET)
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#define SAM_BSCIF_VERSION (SAM_BSCIF_BASE+SAM_BSCIF_VERSION_OFFSET)
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/* BSCIF register bit definitions *******************************************************/
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/* Interrupt Enable Register */
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/* Interrupt Disable Register */
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/* Interrupt Mask Register */
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/* Interrupt Status Register */
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/* Interrupt Clear Register */
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#define BSCIF_INT_OSC32RDY (1 << 0) /* Bit 0 */
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#define BSCIF_INT_RC32KRDY (1 << 1) /* Bit 1 */
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#define BSCIF_INT_RC32KLOCK (1 << 2) /* Bit 2 */
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#define BSCIF_INT_RC32KREFE (1 << 3) /* Bit 3 */
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#define BSCIF_INT_RC32KSAT (1 << 4) /* Bit 4 */
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#define BSCIF_INT_BOD33DET (1 << 5) /* Bit 5 */
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#define BSCIF_INT_BOD18DET (1 << 6) /* Bit 6 */
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#define BSCIF_INT_BOD33SYNRDY (1 << 7) /* Bit 7 */
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#define BSCIF_INT_BOD18SYNRDY (1 << 8) /* Bit 8 */
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#define BSCIF_INT_SSWRDY (1 << 9) /* Bit 9: Buck voltage regulator has stopped switching */
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#define BSCIF_INT_VREGOK (1 << 10) /* Bit 10 */
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#define BSCIF_INT_LPBGRDY (1 << 12) /* Bit 12 */
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#define BSCIF_INT_AE (1 << 31) /* Bit 31 */
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/* Power and Clocks Status Register */
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#define BSCIF_PCLKSR_OSC32RDY (1 << 0) /* Bit 0 */
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#define BSCIF_PCLKSR_RC32KRDY (1 << 1) /* Bit 1 */
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#define BSCIF_PCLKSR_RC32KLOCK (1 << 2) /* Bit 2 */
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#define BSCIF_PCLKSR_RC32KREFE (1 << 3) /* Bit 3 */
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#define BSCIF_PCLKSR_RC32KSAT (1 << 4) /* Bit 4 */
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#define BSCIF_PCLKSR_BOD33DET (1 << 5) /* Bit 5 */
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#define BSCIF_PCLKSR_BOD18DET (1 << 6) /* Bit 6 */
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#define BSCIF_PCLKSR_BOD33SYNRDY (1 << 7) /* Bit 7 */
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#define BSCIF_PCLKSR_BOD18SYNRDY (1 << 8) /* Bit 8 */
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#define BSCIF_PCLKSR_SSWRDY (1 << 9) /* Bit 9: Buck voltage regulator has stopped switching */
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#define BSCIF_PCLKSR_VREGOK (1 << 10) /* Bit 10 */
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#define BSCIF_PCLKSR_RC1MRDY (1 << 10) /* Bit 11 */
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#define BSCIF_PCLKSR_LPBGRDY (1 << 12) /* Bit 12 */
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/* Unlock Register */
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#define BSCIF_UNLOCK_ADDR_SHIFT (0) /* Bits 0-9: Unlock Address */
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#define BSCIF_UNLOCK_ADDR_MASK (0x3ff << BSCIF_UNLOCK_ADDR_SHIFT)
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# define BSCIF_UNLOCK_ADDR(n) ((n) << BSCIF_UNLOCK_ADDR_SHIFT)
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#define BSCIF_UNLOCK_KEY_SHIFT (24) /* Bits 24-31: Unlock Key */
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#define BSCIF_UNLOCK_KEY_MASK (0xff << BSCIF_UNLOCK_KEY_SHIFT)
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# define BSCIF_UNLOCK_KEY(n) ((n) << BSCIF_UNLOCK_KEY_SHIFT)
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/* Chip Specific Configuration Register */
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/* Oscillator 32 Control Register */
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#define BSCIF_OSCCTRL32_OSC32EN (1 << 0) /* Bit 0: 32 KHz Oscillator Enable */
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#define BSCIF_OSCCTRL32_EN32K (1 << 2) /* Bit 2: 32 KHz output Enable */
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#define BSCIF_OSCCTRL32_EN1K (1 << 3) /* Bit 3: 1 KHz output Enable */
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#define BSCIF_OSCCTRL32_MODE_SHIFT (8) /* Bits 8-10: Oscillator Mode */
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#define BSCIF_OSCCTRL32_MODE_MASK (7 << BSCIF_OSCCTRL32_MODE_SHIFT)
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# define BSCIF_OSCCTRL32_MODE_EXTCLK (0 << BSCIF_OSCCTRL32_MODE_SHIFT) /* External clock */
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# define BSCIF_OSCCTRL32_MODE_XTAL (1 << BSCIF_OSCCTRL32_MODE_SHIFT) /* Crystal mode */
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# define BSCIF_OSCCTRL32_MODE_XTALAC (3 << BSCIF_OSCCTRL32_MODE_SHIFT) /* Crystal + amplitude controlled mode */
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# define BSCIF_OSCCTRL32_MODE_XTALHC (4 << BSCIF_OSCCTRL32_MODE_SHIFT) /* Crystal + high current mode */
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# define BSCIF_OSCCTRL32_MODE_XTALHCAC (5 << BSCIF_OSCCTRL32_MODE_SHIFT) /* Crystal + high current + amplitude controlled mode */
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#define BSCIF_OSCCTRL32_SELCURR_SHIFT (12) /* Bits 12-15: Current Selection */
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#define BSCIF_OSCCTRL32_SELCURR_MASK (15 << BSCIF_OSCCTRL32_SELCURR_SHIFT)
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# define BSCIF_OSCCTRL32_SELCURR_50 (0 << BSCIF_OSCCTRL32_SELCURR_SHIFT)
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# define BSCIF_OSCCTRL32_SELCURR_75 (1 << BSCIF_OSCCTRL32_SELCURR_SHIFT)
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# define BSCIF_OSCCTRL32_SELCURR_100 (2 << BSCIF_OSCCTRL32_SELCURR_SHIFT)
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# define BSCIF_OSCCTRL32_SELCURR_125 (3 << BSCIF_OSCCTRL32_SELCURR_SHIFT)
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# define BSCIF_OSCCTRL32_SELCURR_150 (4 << BSCIF_OSCCTRL32_SELCURR_SHIFT)
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# define BSCIF_OSCCTRL32_SELCURR_175 (5 << BSCIF_OSCCTRL32_SELCURR_SHIFT)
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# define BSCIF_OSCCTRL32_SELCURR_200 (6 << BSCIF_OSCCTRL32_SELCURR_SHIFT)
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# define BSCIF_OSCCTRL32_SELCURR_225 (7 << BSCIF_OSCCTRL32_SELCURR_SHIFT)
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# define BSCIF_OSCCTRL32_SELCURR_250 (8 << BSCIF_OSCCTRL32_SELCURR_SHIFT)
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# define BSCIF_OSCCTRL32_SELCURR_275 (9 << BSCIF_OSCCTRL32_SELCURR_SHIFT)
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# define BSCIF_OSCCTRL32_SELCURR_300 (10 << BSCIF_OSCCTRL32_SELCURR_SHIFT) /* (recommended value) */
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# define BSCIF_OSCCTRL32_SELCURR_325 (11 << BSCIF_OSCCTRL32_SELCURR_SHIFT)
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# define BSCIF_OSCCTRL32_SELCURR_350 (12 << BSCIF_OSCCTRL32_SELCURR_SHIFT)
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# define BSCIF_OSCCTRL32_SELCURR_375 (13 << BSCIF_OSCCTRL32_SELCURR_SHIFT)
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# define BSCIF_OSCCTRL32_SELCURR_400 (14 << BSCIF_OSCCTRL32_SELCURR_SHIFT)
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# define BSCIF_OSCCTRL32_SELCURR_425 (15 << BSCIF_OSCCTRL32_SELCURR_SHIFT)
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#define BSCIF_OSCCTRL32_STARTUP_SHIFT (16) /* Bits 16-18: Oscillator Start-up Time */
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#define BSCIF_OSCCTRL32_STARTUP_MASK (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT)
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# define BSCIF_OSCCTRL32_STARTUP_0 (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT)
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# define BSCIF_OSCCTRL32_STARTUP_128 (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) /* 128 1.1 ms */
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# define BSCIF_OSCCTRL32_STARTUP_8K (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) /* 8192 72.3 ms */
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# define BSCIF_OSCCTRL32_STARTUP_16K (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) /* 16384 143 ms */
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# define BSCIF_OSCCTRL32_STARTUP_54K (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) /* 65536 570 ms */
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# define BSCIF_OSCCTRL32_STARTUP_128K (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) /* 131072 1.1 s */
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# define BSCIF_OSCCTRL32_STARTUP_256K (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) /* 262144 2.3 s */
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# define BSCIF_OSCCTRL32_STARTUP_512K (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) /* 524288 4.6 s */
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#define BSCIF_OSCCTRL32_RESERVED (1 << 31) /* Bit 31: Reserved, must always be written as zero */
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/* 32kHz RC Oscillator Control Register */
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#define BSCIF_RC32KCR_EN (1 << 0) /* Bit 0: Enable as Generic clock source */
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#define BSCIF_RC32KCR_TCEN (1 << 1) /* Bit 1: Temperature Compensation Enable */
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#define BSCIF_RC32KCR_EN32K (1 << 2) /* Bit 2: Enable 32 KHz output */
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#define BSCIF_RC32KCR_EN1K (1 << 3) /* Bit 3: Enable 1 kHz output */
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#define BSCIF_RC32KCR_MODE (1 << 4) /* Bit 4: Mode Selection */
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#define BSCIF_RC32KCR_REF (1 << 5) /* Bit 5: Reference select */
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#define BSCIF_RC32KCR_FCD (1 << 7) /* Bit 7: Flash calibration done */
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/* 32kHz RC Oscillator Tuning Register */
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#define BSCIF_RC32KTUNE_FINE_SHIFT (0) /* Bits 0-5: Fine Value */
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#define BSCIF_RC32KTUNE_FINE_MASK (0x3f << BSCIF_RC32KTUNE_FINE_SHIFT)
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#define BSCIF_RC32KTUNE_COARSE_SHIFT (16) /* Bits 16-22: Coarse value */
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#define BSCIF_RC32KTUNE_COARSE_MASK (0x7f << BSCIF_RC32KTUNE_COARSE_SHIFT)
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/* BOD33 Control Register */
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/* BOD18 Control Register */
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#define BSCIF_BODCTRL_EN (1 << 0) /* Bit 0: Enable */
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#define BSCIF_BODCTRL_HYST (1 << 1) /* Bit 1: BOD Hysteresis */
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#define BSCIF_BODCTRL_ACTION_SHIFT (8) /* Bits 8-9: Action */
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# define BSCIF_BODCTRL_ACTION_RESET (1 << BSCIF_BODCTRL_ACTION_SHIFT) /* The BOD generates a reset */
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# define BSCIF_BODCTRL_ACTION_INTR (2 << BSCIF_BODCTRL_ACTION_SHIFT) /* The BOD generates an interrupt */
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#define BSCIF_BODCTRL_MODE (1 << 0) /* Bit 0: Operation modes */
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#define BSCIF_BODCTRL_FCD (1 << 0) /* Bit 0: BOD Fuse Calibration Done */
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#define BSCIF_BODCTRL_SFV (1 << 0) /* Bit 0: BOD Control Register Store Final Value */
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/* BOD33 Level Register */
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/* BOD18 Level Register */
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#define BSCIF_BODLEVEL_CEN (1 << 0) /* Bit 0: Clock Enable */
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#define BSCIF_BODLEVEL_CSSEL (1 << 1) /* Bit 1: Clock Source Select */
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#define BSCIF_BODLEVEL_PSEL_SHIFT (8) /* Bits 8-11: Prescaler Select */
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#define BSCIF_BODLEVEL_PSEL_MASK (15 << BSCIF_BODLEVEL_PSEL_SHIFT)
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/* BOD33 Sampling Control Register */
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/* BOD18 Sampling Control Register */
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#define BSCIF_BODSAMPLING_VAL_SHIFT (0) /* Bits 0-5: BOD Value */
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#define BSCIF_BODSAMPLING_VAL_MASK (0x3f << BSCIF_BODSAMPLING_VAL_SHIFT)
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#define BSCIF_BODSAMPLING_RANGE (1 << 31) /* Bit 31: BOD Threshold Range (available for BOD18 only */
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/* Voltage Regulator Configuration Register */
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#define BSCIF_VREGCR_DIS (1 << 0) /* Bit 0: Voltage Regulator disable */
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#define BSCIF_VREGCR_SSG (1 << 8) /* Bit 8: Spread Spectrum Generator Enable */
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#define BSCIF_VREGCR_SSW (1 << 9) /* Bit 9: Stop Switching */
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#define BSCIF_VREGCR_SSWEVT (1 << 10) /* Bit 10: Stop Switching On Event Enable */
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#define BSCIF_VREGCR_SFV (1 << 31) /* Bit 31: Store Final Value */
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/* 1MHz RC Clock Configuration Register */
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#define BSCIF_RC1MCR_FCD (1 << 0) /* Bit 0: Flash Calibration Done */
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#define BSCIF_RC1MCR_CLKOEN (1 << 7) /* Bit 7: 1MHz RC Osc Clock Output Enable */
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#define BSCIF_RC1MCR_CLKCAL_SHIFT (8) /* Bits 8-12: 1MHz RC Osc Calibration */
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#define BSCIF_RC1MCR_CLKCAL_MASK (31 << BSCIF_RC1MCR_CLKCAL_SHIFT)
|
||||
|
||||
/* Bandgap Control Register */
|
||||
|
||||
#define BSCIF_BGCTRL_ADCISEL_SHIFT (0) /* Bits 0-1: ADC Input Selection */
|
||||
#define BSCIF_BGCTRL_ADCISEL_MASK (3 << BSCIF_BGCTRL_ADCISEL_SHIFT)
|
||||
#define BSCIF_BGCTRL_TSEN (1 << 8)
|
||||
|
||||
/* Bandgap Status Register */
|
||||
|
||||
#define BSCIF_BGS_BGBUFRDY_SHIFT (0) /* Bits 0-7: Bandgap Buffer Ready */
|
||||
#define BSCIF_BGS_BGBUFRDY_MASK (0xff << BSCIF_BGS_BGBUFRDY_SHIFT)
|
||||
#define BSCIF_BGS_BGRDY (1 << 16) /* Bit 16: Bandgap Voltage Reference Ready */
|
||||
#define BSCIF_BGS_LPBGRDY (1 << 17) /* Bit 17: Low Power Bandgap Voltage Reference Ready */
|
||||
#define BSCIF_BGS_VREF_SHIFT (18) /* Bits 18-19: Voltage Reference Used by the System */
|
||||
#define BSCIF_BGS_VREF_MASK (3 << BSCIF_BGS_VREF_SHIFT)
|
||||
|
||||
/* 0x0078-0x0084 Backup register n=0..3 (32-bit data) */
|
||||
|
||||
/* Backup Register Interface Version Register */
|
||||
/* BGREFIF Version Register */
|
||||
/* Voltage Regulator Version Register */
|
||||
/* BOD Version Register */
|
||||
/* 32kHz RC Oscillator Version Register */
|
||||
/* 32 kHz Oscillator Version Register */
|
||||
/* BSCIF Version Register */
|
||||
|
||||
#define BSCIF_VERSION_SHIFT (0) /* Bits 0-11: Version Number */
|
||||
#define BSCIF_VERSION_MASK (0xfff << BSCIF_VERSION_VERSION_SHIFT)
|
||||
#define BSCIF_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */
|
||||
#define BSCIF_VARIANT_MASK (15 << BSCIF_VARIANT_SHIFT)
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_BSCIF_H */
|
||||
@ -176,17 +176,32 @@
|
||||
# define SCIF_UNLOCK_KEY(n) ((n) << SCIF_UNLOCK_KEY_SHIFT)
|
||||
|
||||
/* Chip Specific Configuration Register */
|
||||
#define SCIF_CSCR_
|
||||
|
||||
|
||||
/* Oscillator Control Register */
|
||||
|
||||
#define SCIF_OSCCTRL0_MODE (1 << 0) /* Bit 0: Oscillator Mode */
|
||||
#define SCIF_OSCCTRL0_GAIN_SHIFT (1) /* Bits 1-2: Gain */
|
||||
#define SCIF_OSCCTRL0_GAIN_ (3 << SCIF_OSCCTRL0_GAIN_SHIFT)
|
||||
#define SCIF_OSCCTRL0_GAIN_MASK (3 << SCIF_OSCCTRL0_GAIN_SHIFT)
|
||||
# define SCIF_OSCCTRL0_GAIN(n) ((n) << SCIF_OSCCTRL0_GAIN_SHIFT)
|
||||
#define SCIF_OSCCTRL0_AGC (1 << 3) /* Bit 3: Automatic Gain Control */
|
||||
#define SCIF_OSCCTRL0_STARTUP_SHIFT (9) /* Bits 8-11: Oscillator Start-up Time */
|
||||
#define SCIF_OSCCTRL0_STARTUP_MASK (15 << SCIF_OSCCTRL0_STARTUP_SHIFT)
|
||||
# define SCIF_OSCCTRL0_STARTUP_0 (0 << SCIF_OSCCTRL0_STARTUP_SHIFT)
|
||||
# define SCIF_OSCCTRL0_STARTUP_64 (1 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 64 557 us */
|
||||
# define SCIF_OSCCTRL0_STARTUP_128 (2 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 128 1.1 ms */
|
||||
# define SCIF_OSCCTRL0_STARTUP_2K (3 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 2048 18 ms */
|
||||
# define SCIF_OSCCTRL0_STARTUP_4K (4 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 4096 36 ms */
|
||||
# define SCIF_OSCCTRL0_STARTUP_8K (5 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 8192 71 ms */
|
||||
# define SCIF_OSCCTRL0_STARTUP_16K (6 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 16384 143 ms */
|
||||
# define SCIF_OSCCTRL0_STARTUP_32K (7 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 32768 285 ms */
|
||||
# define SCIF_OSCCTRL0_STARTUP_4 (8 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 4 35 us */
|
||||
# define SCIF_OSCCTRL0_STARTUP_8 (9 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 8 70 us */
|
||||
# define SCIF_OSCCTRL0_STARTUP_16 (10 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 16 139 us */
|
||||
# define SCIF_OSCCTRL0_STARTUP_32 (11 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 32 278 us */
|
||||
# define SCIF_OSCCTRL0_STARTUP_256 (12 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 256 2.2 ms */
|
||||
# define SCIF_OSCCTRL0_STARTUP_512 (13 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 512 4.5 ms */
|
||||
# define SCIF_OSCCTRL0_STARTUP_1K (14 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 1024 8.9 ms */
|
||||
# define SCIF_OSCCTRL0_STARTUP_32K2 (15 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 2768 285 ms */
|
||||
#define SCIF_OSCCTRL0_OSCEN (1 << 16) /* Bit 16: Oscillator Enable */
|
||||
|
||||
/* PLL0 Control Register */
|
||||
|
||||
@ -67,10 +67,80 @@
|
||||
#define SAM_RCFAST12M_FREQUENCY 12000000 /* Nominal frequency of RCFAST12M (Hz) */
|
||||
#define SAM_RC1M_FREQUENCY 1000000 /* Nominal frequency of RC1M (Hz) */
|
||||
|
||||
#if defined(SAM_CLOCK_OSC0) || \
|
||||
(defined (SAM_CLOCK_PLL0) && defined(SAM_CLOCK_PLL0_OSC0)) || \
|
||||
(defined (SAM_CLOCK_PLL1) && defined(SAM_CLOCK_PLL1_OSC0))
|
||||
# define NEED_OSC0
|
||||
/* Oscillator 0. This might be the system clock or the source clock for
|
||||
* either PLL0 or DFPLL.
|
||||
*
|
||||
* By selecting CONFIG_SAM_OSC0, you can also force the clock to be enabled
|
||||
* at boot time.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_SAM_OSC0) || defined(BOARD_SYSCLK_SOURCE_OSC0) || \
|
||||
defined(BOARD_DFLL0_SOURCE_OSC0) || defined(BOARD_PLL0_SOURCE_OSC0)
|
||||
# define NEED_OSC0 1
|
||||
#endif
|
||||
|
||||
#ifdef NEED_OSC0
|
||||
# if !defined(BOARD_OSC0_STARTUP_US)
|
||||
# error BOARD_OSC0_STARTUP_US is not defined
|
||||
# if BOARD_OSC0_STARTUP_US == 0
|
||||
# define OSC0_STARTUP_VALUE SCIF_OSCCTRL0_STARTUP_0
|
||||
# define OSC0_STARTUP_TIMEOUT 8
|
||||
# elif BOARD_OSC0_STARTUP_US <= 557
|
||||
# define OSC0_STARTUP_VALUE SCIF_OSCCTRL0_STARTUP_64
|
||||
# define OSC0_STARTUP_TIMEOUT 80
|
||||
# elif BOARD_OSC0_STARTUP_US <= 1100
|
||||
# define OSC0_STARTUP_VALUE SCIF_OSCCTRL0_STARTUP_128
|
||||
# define OSC0_STARTUP_TIMEOUT 160
|
||||
# elif BOARD_OSC0_STARTUP_US <= 18000
|
||||
# define OSC0_STARTUP_VALUE SCIF_OSCCTRL0_STARTUP_2K
|
||||
# define OSC0_STARTUP_TIMEOUT 2560
|
||||
# elif BOARD_OSC0_STARTUP_US <= 36000
|
||||
# define OSC0_STARTUP_VALUE SCIF_OSCCTRL0_STARTUP_4K
|
||||
# define OSC0_STARTUP_TIMEOUT 5120
|
||||
# elif BOARD_OSC0_STARTUP_US <= 71000
|
||||
# define OSC0_STARTUP_VALUE SCIF_OSCCTRL0_STARTUP_8K
|
||||
# define OSC0_STARTUP_TIMEOUT 10240
|
||||
# elif BOARD_OSC0_STARTUP_US <= 143000
|
||||
# define OSC0_STARTUP_VALUE SCIF_OSCCTRL0_STARTUP_16K
|
||||
# define OSC0_STARTUP_TIMEOUT 20480
|
||||
# elif BOARD_OSC0_STARTUP_US <= 285000
|
||||
# define OSC0_STARTUP_VALUE SCIF_OSCCTRL0_STARTUP_32K
|
||||
# define OSC0_STARTUP_TIMEOUT 40960
|
||||
# else
|
||||
# error BOARD_OSC0_STARTUP_US is out of range
|
||||
# endif
|
||||
|
||||
# ifdef BOARD_OSC0_IS_XTAL
|
||||
# define OSC0_MODE_VALUE SCIF_OSCCTRL0_MODE
|
||||
# if BOARD_OSC0_FREQUENCY < 2000000
|
||||
# define OSC0_GAIN_VALUE SCIF_OSCCTRL0_GAIN(0)
|
||||
# elif BOARD_OSC0_FREQUENCY < 4000000
|
||||
# define OSC0_GAIN_VALUE SCIF_OSCCTRL0_GAIN(1)
|
||||
# elif BOARD_OSC0_FREQUENCY < 8000000
|
||||
# define OSC0_GAIN_VALUE SCIF_OSCCTRL0_GAIN(2)
|
||||
# elif BOARD_OSC0_FREQUENCY < 16000000
|
||||
# define OSC0_GAIN_VALUE SCIF_OSCCTRL0_GAIN(3)
|
||||
# else
|
||||
# define OSC0_GAIN_VALUE ((0x1u << 4) | SCIF_OSCCTRL0_GAIN(0))
|
||||
# endif
|
||||
# else
|
||||
# define OSC0_MODE_VALUE 0
|
||||
# define OSC0_GAIN_VALUE 0
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* OSC32. The 32K oscillator may be the source clock for DFPLL0.
|
||||
*
|
||||
* By selecting CONFIG_SAM_OSC32K, you can also force the clock to be
|
||||
* enabled at boot time. OSC32 may needed by other devices as well
|
||||
* (AST, WDT, PICUART, RTC).
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_SAM_OSC32K) || defined(BOARD_DFLL0_SOURCE_OSC32K)
|
||||
# define NEED_OSC32K 1
|
||||
#endif
|
||||
|
||||
#ifdef NEED_OSC32K
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
@ -127,7 +197,7 @@ static inline void sam_picocache(void)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef SAM_CLOCK_OSC32
|
||||
#ifdef NEED_OSC32K
|
||||
static inline void sam_enableosc32(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
@ -159,41 +229,23 @@ static inline void sam_enableosc32(void)
|
||||
#ifdef NEED_OSC0
|
||||
static inline void sam_enableosc0(void)
|
||||
{
|
||||
irqstate_t flags;
|
||||
uint32_t regval;
|
||||
|
||||
/* Enable OSC0 in the correct crystal mode by setting the mode value in OSCCTRL0 */
|
||||
regval = OSC0_STARTUP_VALUE | OSC0_GAIN_VALUE | OSC0_MODE_VALUE |
|
||||
SCIF_OSCCTRL0_OSCEN;
|
||||
|
||||
regval = getreg32(SAM_PM_OSCCTRL0);
|
||||
regval &= ~PM_OSCCTRL_MODE_MASK;
|
||||
#if SAM_FOSC0 < 900000
|
||||
regval |= PM_OSCCTRL_MODE_XTALp9; /* Crystal XIN 0.4-0.9MHz */
|
||||
#elif SAM_FOSC0 < 3000000
|
||||
regval |= PM_OSCCTRL_MODE_XTAL3; /* Crystal XIN 0.9-3.0MHz */
|
||||
#elif SAM_FOSC0 < 8000000
|
||||
regval |= PM_OSCCTRL_MODE_XTAL8; /* Crystal XIN 3.0-8.0MHz */
|
||||
#else
|
||||
regval |= PM_OSCCTRL_MODE_XTALHI; /* Crystal XIN above 8.0MHz */
|
||||
#endif
|
||||
putreg32(regval, SAM_PM_OSCCTRL0);
|
||||
/* The following two statements must be atomic */
|
||||
|
||||
/* Enable OSC0 using the startup time provided in board.h. This startup time
|
||||
* is critical and depends on the characteristics of the crystal.
|
||||
*/
|
||||
|
||||
regval = getreg32(SAM_PM_OSCCTRL0);
|
||||
regval &= ~PM_OSCCTRL_STARTUP_MASK;
|
||||
regval |= (SAM_OSC0STARTUP << PM_OSCCTRL_STARTUP_SHIFT);
|
||||
putreg32(regval, SAM_PM_OSCCTRL0);
|
||||
|
||||
/* Enable OSC0 */
|
||||
|
||||
regval = getreg32(SAM_PM_MCCTRL);
|
||||
regval |= PM_MCCTRL_OSC0EN;
|
||||
putreg32(regval, SAM_PM_MCCTRL);
|
||||
flags = irqsave();
|
||||
putreg32(SCIF_UNLOCK_KEY(0xaa) | SCIF_UNLOCK_ADDR(SAM_SCIF_OSCCTRL0_OFFSET),
|
||||
SAM_SCIF_UNLOCK);
|
||||
putreg32(regval, SAM_SCIF_OSCCTRL0);
|
||||
irqrestore(flags);
|
||||
|
||||
/* Wait for OSC0 to be ready */
|
||||
|
||||
while ((getreg32(SAM_PM_POSCSR) & PM_POSCSR_OSC0RDY) == 0);
|
||||
while (getreg32(SAM_SCIF_PCLKSR) & SCIF_INT_OSC0RDY) == 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -531,17 +583,35 @@ void sam_clockconfig(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef SAM_CLOCK_OSC32
|
||||
/* Enable clock sources:
|
||||
*
|
||||
* OSC0: Might by the system clock or the source clock for PLL0 or DFLL0
|
||||
* OSC32: Might be source clock for DFLL0
|
||||
*/
|
||||
|
||||
#if NEED_OSC0
|
||||
/* Enable OSC0 using the settings in board.h */
|
||||
|
||||
sam_enableosc0();
|
||||
#endif
|
||||
|
||||
#ifdef NEED_OSC32K
|
||||
/* Enable the 32KHz oscillator (need by the RTC module) */
|
||||
|
||||
sam_enableosc32();
|
||||
#endif
|
||||
|
||||
/* Switch to the system clock selected by the settings in the board.h
|
||||
* header file.
|
||||
*/
|
||||
|
||||
#if defined(BOARD_SYSCLK_SOURCE_RCSYS)
|
||||
/* Since this function only executes at power up, we know that we are
|
||||
* already running from RCSYS.
|
||||
*/
|
||||
#endif
|
||||
|
||||
#ifdef NEED_OSC0
|
||||
/* Enable OSC0 using the settings in board.h */
|
||||
|
||||
sam_enableosc0();
|
||||
|
||||
/* Set up FLASH wait states */
|
||||
|
||||
sam_fws(SAM_FOSC0);
|
||||
@ -551,12 +621,6 @@ void sam_clockconfig(void)
|
||||
sam_mainclk(PM_MCCTRL_MCSEL_OSC0);
|
||||
#endif
|
||||
|
||||
#ifdef NEED_OSC1
|
||||
/* Enable OSC1 using the settings in board.h */
|
||||
|
||||
sam_enableosc1();
|
||||
#endif
|
||||
|
||||
#ifdef SAM_CLOCK_PLL0
|
||||
/* Enable PLL0 using the settings in board.h */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user