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Merged in slorquet/nuttx/stm32l4usb (pull request #127)

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Apply stm32 fix to stm32l4
This commit is contained in:
Gregory Nutt 2016-08-31 07:01:53 -06:00
commit 9162b34099
2 changed files with 185 additions and 161 deletions
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6
arch/arm/src/stm32l4/chip/stm32l4x6xx_otgfs.h
View File

@ -555,20 +555,20 @@
#define OTGFS_GINT_NPTXFE (1 << 5) /* Bit 5: Non-periodic TxFIFO empty */ #define OTGFS_GINT_NPTXFE (1 << 5) /* Bit 5: Non-periodic TxFIFO empty */
#define OTGFS_GINT_GINAKEFF (1 << 6) /* Bit 6: Global IN non-periodic NAK effective */ #define OTGFS_GINT_GINAKEFF (1 << 6) /* Bit 6: Global IN non-periodic NAK effective */
#define OTGFS_GINT_GONAKEFF (1 << 7) /* Bit 7: Global OUT NAK effective */ #define OTGFS_GINT_GONAKEFF (1 << 7) /* Bit 7: Global OUT NAK effective */
/* Bits 8-9: Reserved, must be kept at reset value */ #define OTGFS_GINT_RES89 (3 << 8) /* Bits 8-9: Reserved, must be kept at reset value */
#define OTGFS_GINT_ESUSP (1 << 10) /* Bit 10: Early suspend */ #define OTGFS_GINT_ESUSP (1 << 10) /* Bit 10: Early suspend */
#define OTGFS_GINT_USBSUSP (1 << 11) /* Bit 11: USB suspend */ #define OTGFS_GINT_USBSUSP (1 << 11) /* Bit 11: USB suspend */
#define OTGFS_GINT_USBRST (1 << 12) /* Bit 12: USB reset */ #define OTGFS_GINT_USBRST (1 << 12) /* Bit 12: USB reset */
#define OTGFS_GINT_ENUMDNE (1 << 13) /* Bit 13: Enumeration done */ #define OTGFS_GINT_ENUMDNE (1 << 13) /* Bit 13: Enumeration done */
#define OTGFS_GINT_ISOODRP (1 << 14) /* Bit 14: Isochronous OUT packet dropped interrupt */ #define OTGFS_GINT_ISOODRP (1 << 14) /* Bit 14: Isochronous OUT packet dropped interrupt */
#define OTGFS_GINT_EOPF (1 << 15) /* Bit 15: End of periodic frame interrupt */ #define OTGFS_GINT_EOPF (1 << 15) /* Bit 15: End of periodic frame interrupt */
/* Bits 16-17: Reserved, must be kept at reset value */ #define OTGFS_GINT_RES1617 (3 << 16) /* Bits 16-17: Reserved, must be kept at reset value */
#define OTGFS_GINT_IEP (1 << 18) /* Bit 18: IN endpoint interrupt */ #define OTGFS_GINT_IEP (1 << 18) /* Bit 18: IN endpoint interrupt */
#define OTGFS_GINT_OEP (1 << 19) /* Bit 19: OUT endpoint interrupt */ #define OTGFS_GINT_OEP (1 << 19) /* Bit 19: OUT endpoint interrupt */
#define OTGFS_GINT_IISOIXFR (1 << 20) /* Bit 20: Incomplete isochronous IN transfer */ #define OTGFS_GINT_IISOIXFR (1 << 20) /* Bit 20: Incomplete isochronous IN transfer */
#define OTGFS_GINT_IISOOXFR (1 << 21) /* Bit 21: Incomplete isochronous OUT transfer (device) */ #define OTGFS_GINT_IISOOXFR (1 << 21) /* Bit 21: Incomplete isochronous OUT transfer (device) */
#define OTGFS_GINT_IPXFR (1 << 21) /* Bit 21: Incomplete periodic transfer (host) */ #define OTGFS_GINT_IPXFR (1 << 21) /* Bit 21: Incomplete periodic transfer (host) */
/* Bit 22: Reserved, must be kept at reset value */ #define OTGFS_GINT_RES22 (1 << 22) /* Bit 22: Reserved, must be kept at reset value */
#define OTGFS_GINT_RSTDET (1 << 23) /* Bit 23: Reset detected interrupt */ #define OTGFS_GINT_RSTDET (1 << 23) /* Bit 23: Reset detected interrupt */
#define OTGFS_GINT_HPRT (1 << 24) /* Bit 24: Host port interrupt */ #define OTGFS_GINT_HPRT (1 << 24) /* Bit 24: Host port interrupt */
#define OTGFS_GINT_HC (1 << 25) /* Bit 25: Host channels interrupt */ #define OTGFS_GINT_HC (1 << 25) /* Bit 25: Host channels interrupt */

96
arch/arm/src/stm32l4/stm32l4_otgfsdev.c
View File

@ -225,6 +225,27 @@
# error "CONFIG_USBDEV_EP5_TXFIFO_SIZE is out of range" # error "CONFIG_USBDEV_EP5_TXFIFO_SIZE is out of range"
#endif #endif
#define OTGFS_GINT_RESERVED (OTGFS_GINT_RES89 | \
OTGFS_GINT_RES1617 | \
OTGFS_GINT_RES22)
#define OTGFS_GINT_RC_W1 (OTGFS_GINT_MMIS | \
OTGFS_GINT_SOF | \
OTGFS_GINT_ESUSP | \
OTGFS_GINT_USBSUSP | \
OTGFS_GINT_USBRST | \
OTGFS_GINT_ENUMDNE | \
OTGFS_GINT_ISOODRP | \
OTGFS_GINT_EOPF | \
OTGFS_GINT_IISOIXFR | \
OTGFS_GINT_IISOOXFR | \
OTGFS_GINT_RSTDET | \
OTGFS_GINT_LPMINT | \
OTGFS_GINT_CIDSCHG | \
OTGFS_GINT_DISC | \
OTGFS_GINT_SRQ | \
OTGFS_GINT_WKUP)
/* Debug ***********************************************************************/ /* Debug ***********************************************************************/
/* Trace error codes */ /* Trace error codes */
@ -3221,9 +3242,8 @@ static inline void stm32l4_rxinterrupt(FAR struct stm32l4_usbdev_s *priv)
/* Disable the Rx status queue level interrupt */ /* Disable the Rx status queue level interrupt */
regval = stm32l4_getreg(STM32L4_OTGFS_GINTMSK); while(0 != (stm32l4_getreg(STM32L4_OTGFS_GINTSTS) & OTGFS_GINT_RXFLVL))
regval &= ~OTGFS_GINT_RXFLVL; {
stm32l4_putreg(regval, STM32L4_OTGFS_GINTMSK);
/* Get the status from the top of the FIFO */ /* Get the status from the top of the FIFO */
@ -3233,6 +3253,11 @@ static inline void stm32l4_rxinterrupt(FAR struct stm32l4_usbdev_s *priv)
epphy = (regval & OTGFS_GRXSTSD_EPNUM_MASK) >> OTGFS_GRXSTSD_EPNUM_SHIFT; epphy = (regval & OTGFS_GRXSTSD_EPNUM_MASK) >> OTGFS_GRXSTSD_EPNUM_SHIFT;
/* Workaround for bad values read from the STM32L4_OTGFS_GRXSTSP register
* happens regval is 0xb4e48168 or 0xa80c9367 or 267E781c
* All of which provide out of range indexes for epout[epphy]
*/
if (epphy < STM32L4_NENDPOINTS) if (epphy < STM32L4_NENDPOINTS)
{ {
privep = &priv->epout[epphy]; privep = &priv->epout[epphy];
@ -3299,6 +3324,22 @@ static inline void stm32l4_rxinterrupt(FAR struct stm32l4_usbdev_s *priv)
case OTGFS_GRXSTSD_PKTSTS_SETUPDONE: case OTGFS_GRXSTSD_PKTSTS_SETUPDONE:
{ {
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETUPDONE), epphy); usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETUPDONE), epphy);
/* Now that the Setup Phase is complete if it was an OUT enable
* the endpoint
* (Doing this here prevents the loss of the first FIFO word)
*/
if (priv->ep0state == EP0STATE_SETUP_OUT)
{
/* Clear NAKSTS so that we can receive the data */
regval = stm32l4_getreg(STM32L4_OTGFS_DOEPCTL0);
regval |= OTGFS_DOEPCTL0_CNAK;
stm32l4_putreg(regval, STM32L4_OTGFS_DOEPCTL0);
}
} }
break; break;
@ -3334,12 +3375,6 @@ static inline void stm32l4_rxinterrupt(FAR struct stm32l4_usbdev_s *priv)
datlen = GETUINT16(priv->ctrlreq.len); datlen = GETUINT16(priv->ctrlreq.len);
if (USB_REQ_ISOUT(priv->ctrlreq.type) && datlen > 0) if (USB_REQ_ISOUT(priv->ctrlreq.type) && datlen > 0)
{ {
/* Clear NAKSTS so that we can receive the data */
regval = stm32l4_getreg(STM32L4_OTGFS_DOEPCTL0);
regval |= OTGFS_DOEPCTL0_CNAK;
stm32l4_putreg(regval, STM32L4_OTGFS_DOEPCTL0);
/* Wait for the data phase. */ /* Wait for the data phase. */
priv->ep0state = EP0STATE_SETUP_OUT; priv->ep0state = EP0STATE_SETUP_OUT;
@ -3363,12 +3398,7 @@ static inline void stm32l4_rxinterrupt(FAR struct stm32l4_usbdev_s *priv)
break; break;
} }
} }
}
/* Enable the Rx Status Queue Level interrupt */
regval = stm32l4_getreg(STM32L4_OTGFS_GINTMSK);
regval |= OTGFS_GINT_RXFLVL;
stm32l4_putreg(regval, STM32L4_OTGFS_GINTMSK);
} }
/**************************************************************************** /****************************************************************************
@ -3391,7 +3421,7 @@ static inline void stm32l4_enuminterrupt(FAR struct stm32l4_usbdev_s *priv)
regval = stm32l4_getreg(STM32L4_OTGFS_GUSBCFG); regval = stm32l4_getreg(STM32L4_OTGFS_GUSBCFG);
regval &= ~OTGFS_GUSBCFG_TRDT_MASK; regval &= ~OTGFS_GUSBCFG_TRDT_MASK;
regval |= OTGFS_GUSBCFG_TRDT(5); regval |= OTGFS_GUSBCFG_TRDT(6);
stm32l4_putreg(regval, STM32L4_OTGFS_GUSBCFG); stm32l4_putreg(regval, STM32L4_OTGFS_GUSBCFG);
} }
@ -3605,32 +3635,38 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context)
/* At present, there is only a single OTG FS device support. Hence it is /* At present, there is only a single OTG FS device support. Hence it is
* pre-allocated as g_otgfsdev. However, in most code, the private data * pre-allocated as g_otgfsdev. However, in most code, the private data
* structure will be referenced using the 'priv' pointer (rather than the * structure will be referenced using the 'priv' pointer (rather than the
* global data) in order to simplify any future support for multiple * global data) in order to simplify any future support for multiple devices.
* devices.
*/ */
FAR struct stm32l4_usbdev_s *priv = &g_otgfsdev; FAR struct stm32l4_usbdev_s *priv = &g_otgfsdev;
uint32_t regval; uint32_t regval;
uint32_t reserved;
usbtrace(TRACE_INTENTRY(STM32L4_TRACEINTID_USB), 0); usbtrace(TRACE_INTENTRY(STM32L4_TRACEINTID_USB), 0);
/* Assure that we are in device mode */ /* Assure that we are in device mode */
DEBUGASSERT((stm32l4_getreg(STM32L4_OTGFS_GINTSTS) & OTGFS_GINTSTS_CMOD) == DEBUGASSERT((stm32l4_getreg(STM32L4_OTGFS_GINTSTS) & OTGFS_GINTSTS_CMOD) == OTGFS_GINTSTS_DEVMODE);
OTGFS_GINTSTS_DEVMODE);
/* Get the state of all enabled interrupts. We will do this repeatedly /* Get the state of all enabled interrupts. We will do this repeatedly
* some interrupts (like RXFLVL) will generate additional interrupting * some interrupts (like RXFLVL) will generate additional interrupting
* events. * events.
*/ */
for (; ; ) for (; ; )
{ {
/* Get the set of pending, un-masked interrupts */ /* Get the set of pending, un-masked interrupts */
regval = stm32l4_getreg(STM32L4_OTGFS_GINTSTS); regval = stm32l4_getreg(STM32L4_OTGFS_GINTSTS);
reserved = (regval & OTGFS_GINT_RESERVED);
regval &= stm32l4_getreg(STM32L4_OTGFS_GINTMSK); regval &= stm32l4_getreg(STM32L4_OTGFS_GINTMSK);
/* With out modifying the reserved bits, acknowledge all
* **Writable** pending irqs we will service below
*/
stm32l4_putreg(((regval | reserved) & OTGFS_GINT_RC_W1), STM32L4_OTGFS_GINTSTS);
/* Break out of the loop when there are no further pending (and /* Break out of the loop when there are no further pending (and
* unmasked) interrupts to be processes. * unmasked) interrupts to be processes.
*/ */
@ -3639,7 +3675,6 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context)
{ {
break; break;
} }
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_INTPENDING), (uint16_t)regval); usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_INTPENDING), (uint16_t)regval);
/* OUT endpoint interrupt. The core sets this bit to indicate that an /* OUT endpoint interrupt. The core sets this bit to indicate that an
@ -3650,7 +3685,6 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context)
{ {
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUT), (uint16_t)regval); usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUT), (uint16_t)regval);
stm32l4_epout_interrupt(priv); stm32l4_epout_interrupt(priv);
stm32l4_putreg(OTGFS_GINT_OEP, STM32L4_OTGFS_GINTSTS);
} }
/* IN endpoint interrupt. The core sets this bit to indicate that /* IN endpoint interrupt. The core sets this bit to indicate that
@ -3661,7 +3695,6 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context)
{ {
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN), (uint16_t)regval); usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN), (uint16_t)regval);
stm32l4_epin_interrupt(priv); stm32l4_epin_interrupt(priv);
stm32l4_putreg(OTGFS_GINT_IEP, STM32L4_OTGFS_GINTSTS);
} }
/* Host/device mode mismatch error interrupt */ /* Host/device mode mismatch error interrupt */
@ -3670,7 +3703,6 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context)
if ((regval & OTGFS_GINT_MMIS) != 0) if ((regval & OTGFS_GINT_MMIS) != 0)
{ {
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_MISMATCH), (uint16_t)regval); usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_MISMATCH), (uint16_t)regval);
stm32l4_putreg(OTGFS_GINT_MMIS, STM32L4_OTGFS_GINTSTS);
} }
#endif #endif
@ -3680,7 +3712,6 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context)
{ {
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_WAKEUP), (uint16_t)regval); usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_WAKEUP), (uint16_t)regval);
stm32l4_resumeinterrupt(priv); stm32l4_resumeinterrupt(priv);
stm32l4_putreg(OTGFS_GINT_WKUP, STM32L4_OTGFS_GINTSTS);
} }
/* USB suspend interrupt */ /* USB suspend interrupt */
@ -3689,7 +3720,6 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context)
{ {
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SUSPEND), (uint16_t)regval); usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SUSPEND), (uint16_t)regval);
stm32l4_suspendinterrupt(priv); stm32l4_suspendinterrupt(priv);
stm32l4_putreg(OTGFS_GINT_USBSUSP, STM32L4_OTGFS_GINTSTS);
} }
/* Start of frame interrupt */ /* Start of frame interrupt */
@ -3698,7 +3728,6 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context)
if ((regval & OTGFS_GINT_SOF) != 0) if ((regval & OTGFS_GINT_SOF) != 0)
{ {
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SOF), (uint16_t)regval); usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SOF), (uint16_t)regval);
stm32l4_putreg(OTGFS_GINT_SOF, STM32L4_OTGFS_GINTSTS);
} }
#endif #endif
@ -3710,7 +3739,6 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context)
{ {
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_RXFIFO), (uint16_t)regval); usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_RXFIFO), (uint16_t)regval);
stm32l4_rxinterrupt(priv); stm32l4_rxinterrupt(priv);
stm32l4_putreg(OTGFS_GINT_RXFLVL, STM32L4_OTGFS_GINTSTS);
} }
/* USB reset interrupt */ /* USB reset interrupt */
@ -3723,7 +3751,6 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context)
stm32l4_usbreset(priv); stm32l4_usbreset(priv);
usbtrace(TRACE_INTEXIT(STM32L4_TRACEINTID_USB), 0); usbtrace(TRACE_INTEXIT(STM32L4_TRACEINTID_USB), 0);
stm32l4_putreg(OTGFS_GINT_USBRST, STM32L4_OTGFS_GINTSTS);
return OK; return OK;
} }
@ -3733,7 +3760,6 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context)
{ {
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_ENUMDNE), (uint16_t)regval); usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_ENUMDNE), (uint16_t)regval);
stm32l4_enuminterrupt(priv); stm32l4_enuminterrupt(priv);
stm32l4_putreg(OTGFS_GINT_ENUMDNE, STM32L4_OTGFS_GINTSTS);
} }
/* Incomplete isochronous IN transfer interrupt. When the core finds /* Incomplete isochronous IN transfer interrupt. When the core finds
@ -3747,7 +3773,6 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context)
{ {
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_IISOIXFR), (uint16_t)regval); usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_IISOIXFR), (uint16_t)regval);
stm32l4_isocininterrupt(priv); stm32l4_isocininterrupt(priv);
stm32l4_putreg(OTGFS_GINT_IISOIXFR, STM32L4_OTGFS_GINTSTS);
} }
/* Incomplete isochronous OUT transfer. For isochronous OUT /* Incomplete isochronous OUT transfer. For isochronous OUT
@ -3764,7 +3789,6 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context)
{ {
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_IISOOXFR), (uint16_t)regval); usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_IISOOXFR), (uint16_t)regval);
stm32l4_isocoutinterrupt(priv); stm32l4_isocoutinterrupt(priv);
stm32l4_putreg(OTGFS_GINT_IISOOXFR, STM32L4_OTGFS_GINTSTS);
} }
#endif #endif
@ -3775,7 +3799,6 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context)
{ {
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SRQ), (uint16_t)regval); usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SRQ), (uint16_t)regval);
stm32l4_sessioninterrupt(priv); stm32l4_sessioninterrupt(priv);
stm32l4_putreg(OTGFS_GINT_SRQ, STM32L4_OTGFS_GINTSTS);
} }
/* OTG interrupt */ /* OTG interrupt */
@ -3784,7 +3807,6 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context)
{ {
usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_OTG), (uint16_t)regval); usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_OTG), (uint16_t)regval);
stm32l4_otginterrupt(priv); stm32l4_otginterrupt(priv);
stm32l4_putreg(OTGFS_GINT_OTG, STM32L4_OTGFS_GINTSTS);
} }
#endif #endif
} }
@ -5458,7 +5480,9 @@ static void stm32l4_hwinitialize(FAR struct stm32l4_usbdev_s *priv)
/* Clear any pending interrupts */ /* Clear any pending interrupts */
stm32l4_putreg(0xbfffffff, STM32L4_OTGFS_GINTSTS); regval = stm32l4_getreg(STM32L4_OTGFS_GINTSTS);
regval &= OTGFS_GINT_RESERVED;
stm32l4_putreg(regval | OTGFS_GINT_RC_W1, STM32L4_OTGFS_GINTSTS);
/* Enable the interrupts in the INTMSK */ /* Enable the interrupts in the INTMSK */