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arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h: Fix nxstyle issues

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Signed-off-by: Jukka Laitinen <jukka.laitinen@intel.com>
This commit is contained in:
Jukka Laitinen 2020-06-01 14:46:23 +03:00 committed by David Sidrane
parent 3c4fec80f8
commit 91779e997a
1 changed files with 12 additions and 13 deletions
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25
arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h
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@ -261,11 +261,11 @@
# define SPI_CFG1_UDRDET_BEG (0 << SPI_CFG1_UDRDET_SHIFT)
# define SPI_CFG1_UDRDET_END (1 << SPI_CFG1_UDRDET_SHIFT)
# define SPI_CFG1_UDRDET_SS (2 << SPI_CFG1_UDRDET_SHIFT)
/* 11: Reserved */
/* Bit 13: Reserved */
/* 11: Reserved */
/* Bit 13: Reserved */
#define SPI_CFG1_RXDMAEN (1 << 14) /* Bit 14: RX-DMA stream enable */
#define SPI_CFG1_TXDMAEN (1 << 15) /* Bit 15: TX-DMA stream enable */
#define SPI_CFG1_CRCSIZE_SHIFT (16) /* Bits 16-20: length of CRC frame to be transacted and compared */
#define SPI_CFG1_CRCSIZE_SHIFT (16) /* Bits 16-20: length of CRC frame to be transacted and compared */
#define SPI_CFG1_CRCSIZE_VAL(n) ((n-1) << SPI_CFG1_CRCSIZE_SHIFT)
#define SPI_CFG1_CRCSIZE_MASK (0x1f << SPI_CFG1_CRCSIZE_SHIFT)
/* 00000-00010: Reserved */
@ -298,10 +298,10 @@
# define SPI_CFG1_CRCSIZE_30BIT (29 << SPI_CFG1_CRCSIZE_SHIFT)
# define SPI_CFG1_CRCSIZE_31BIT (30 << SPI_CFG1_CRCSIZE_SHIFT)
# define SPI_CFG1_CRCSIZE_32BIT (31 << SPI_CFG1_CRCSIZE_SHIFT)
/* Bit 21: Reserved */
/* Bit 21: Reserved */
#define SPI_CFG1_CRCEN (1 << 22) /* Bit 22: hardware CRC computation enable */
/* Bits 23-27: Reserved */
#define SPI_CFG1_MBR_SHIFT (28) /* Bits 28-30: master baud rate */
/* Bits 23-27: Reserved */
#define SPI_CFG1_MBR_SHIFT (28) /* Bits 28-30: master baud rate */
#define SPI_CFG1_MBR_MASK (0x7 << SPI_CFG1_MBR_SHIFT)
# define SPI_CFG1_MBR_FPCLKd2 (0 << SPI_CFG1_MBR_SHIFT)
# define SPI_CFG1_MBR_FPCLKd4 (1 << SPI_CFG1_MBR_SHIFT)
@ -351,10 +351,10 @@
# define SPI_CFG2_MIDI_13CLK (13 << SPI_CFG2_MIDI_SHIFT)
# define SPI_CFG2_MIDI_14CLK (14 << SPI_CFG2_MIDI_SHIFT)
# define SPI_CFG2_MIDI_15CLK (15 << SPI_CFG2_MIDI_SHIFT)
/* Bits 8-14: Reserved */
/* Bits 8-14: Reserved */
#define SPI_CFG2_IOSWP (1 << 15) /* Bit 15: swap functionality of MISO and MOSI pins */
/* Bit 16: Reserved */
#define SPI_CFG2_COMM_SHIFT (17) /* Bits 17-18: SPI communication mode */
/* Bit 16: Reserved */
#define SPI_CFG2_COMM_SHIFT (17) /* Bits 17-18: SPI communication mode */
#define SPI_CFG2_COMM_MASK (0x3 << SPI_CFG2_COMM_SHIFT)
# define SPI_CFG2_COMM_FULL (0 << SPI_CFG2_COMM_SHIFT)
# define SPI_CFG2_COMM_STX (1 << SPI_CFG2_COMM_SHIFT)
@ -364,13 +364,13 @@
#define SPI_CFG2_SP_MASK (0x7 << SPI_CFG2_SP_SHIFT)
# define SPI_CFG2_SP_MOTOROLA (0 << SPI_CFG2_SP_SHIFT)
# define SPI_CFG2_SP_TI (1 << SPI_CFG2_SP_SHIFT)
/* 010-111: Reserved */
/* 010-111: Reserved */
#define SPI_CFG2_MASTER (1 << 22) /* Bit 22: SPI master */
#define SPI_CFG2_LSBFRST (1 << 23) /* Bit 23: data frame format */
#define SPI_CFG2_CPHA (1 << 24) /* Bit 24: clock phase */
#define SPI_CFG2_CPOL (1 << 25) /* Bit 25: clock polarity */
#define SPI_CFG2_SSM (1 << 26) /* Bit 26: software management of SS signal input */
/* Bit 27: Reserved */
/* Bit 27: Reserved */
#define SPI_CFG2_SSIOP (1 << 28) /* Bit 28: SS input/output polarity */
#define SPI_CFG2_SSOE (1 << 29) /* Bit 29: SS output enable */
#define SPI_CFG2_SSOM (1 << 30) /* Bit 30: SS output management in master mode */
@ -447,8 +447,7 @@
#define SPI_UDRDR_UDRDR_MASK (0xffff << SPI_UDRDR_UDRDR_SHIFT)
/* Bits 16-31: read zero */
/* TODO: SPI/I2S configuration register*/
/* TODO: SPI/I2S configuration register */
#endif /* CONFIG_STM32H7_STM32H7X3XX */
#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_SPI_H */