arm/cortex-r: rename PCMR_* to PMCR_*
It should be PMCR (Performance Monitors Control Register) Signed-off-by: chao.an <anchao@xiaomi.com>
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@ -251,18 +251,18 @@
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* TODO: To be provided
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*/
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#define PCMR_E (1 << 0) /* Enable all counters */
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#define PCMR_P (1 << 1) /* Reset all counter eventts (except PMCCNTR) */
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#define PCMR_C (1 << 2) /* Reset cycle counter (PMCCNTR) to zero */
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#define PCMR_D (1 << 3) /* Enable cycle counter clock (PMCCNTR) divider */
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#define PCMR_X (1 << 4) /* Export of events is enabled */
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#define PCMR_DP (1 << 5) /* Disable PMCCNTR if event counting is prohibited */
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#define PCMR_N_SHIFT (11) /* Bits 11-15: Number of event counters */
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#define PCMR_N_MASK (0x1f << PCMR_N_SHIFT)
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#define PCMR_IDCODE_SHIFT (16) /* Bits 16-23: Identification code */
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#define PCMR_IDCODE_MASK (0xff << PCMR_IDCODE_SHIFT)
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#define PCMR_IMP_SHIFT (24) /* Bits 24-31: Implementer code */
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#define PCMR_IMP_MASK (0xff << PCMR_IMP_SHIFT)
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#define PMCR_E (1 << 0) /* Enable all counters */
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#define PMCR_P (1 << 1) /* Reset all counter eventts (except PMCCNTR) */
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#define PMCR_C (1 << 2) /* Reset cycle counter (PMCCNTR) to zero */
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#define PMCR_D (1 << 3) /* Enable cycle counter clock (PMCCNTR) divider */
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#define PMCR_X (1 << 4) /* Export of events is enabled */
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#define PMCR_DP (1 << 5) /* Disable PMCCNTR if event counting is prohibited */
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#define PMCR_N_SHIFT (11) /* Bits 11-15: Number of event counters */
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#define PMCR_N_MASK (0x1f << PMCR_N_SHIFT)
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#define PMCR_IDCODE_SHIFT (16) /* Bits 16-23: Identification code */
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#define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT)
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#define PMCR_IMP_SHIFT (24) /* Bits 24-31: Implementer code */
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#define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT)
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/* 32-bit Performance Monitors Count Enable Set register (PMCNTENSET):
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* CRn=c9, opc1=0, CRm=c12, opc2=1
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@ -105,7 +105,7 @@
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static inline void tms570_event_export(void)
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{
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uint32_t pmcr = cp15_pmu_rdpmcr();
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pmcr |= PCMR_X;
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pmcr |= PMCR_X;
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cp15_pmu_wrpmcr(pmcr);
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}
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