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RISC-V: Add common data memory and instruction barriers

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Ville Juven 2021-12-28 16:27:18 +02:00 committed by Xiang Xiao
parent 5665b7a585
commit 9269a86d00
1 changed files with 32 additions and 0 deletions
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arch/risc-v/include/barriers.h Normal file
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/****************************************************************************
* arch/risc-v/include/barriers.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_INCLUDE_BARRIERS_H
#define __ARCH_RISCV_INCLUDE_BARRIERS_H
/* Common memory barriers:
* __DMB() is used to synchronize external devices (I/O domain mainly)
* __ISB() is used to synchronize the instruction and data streams
*/
#define __DMB() __asm__ __volatile__ ("fence" ::: "memory")
#define __ISB() __asm__ __volatile__ ("fence.i" ::: "memory")
#endif /* __ARCH_RISCV_INCLUDE_BARRIERS_H */