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arch/risc-v: Move epc adjustment to riscv_doirq

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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit is contained in:
Huang Qi 2022-04-08 16:28:07 +08:00 committed by Xiang Xiao
parent 833211680a
commit 9284770f75
10 changed files with 8 additions and 69 deletions
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8
arch/risc-v/src/bl602/bl602_irq_dispatch.c
View File

@ -44,7 +44,6 @@
void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
{
int irq = vector & 0x3ff; /* E24 [9:0] */
uintptr_t *mepc = regs;
/* If current is interrupt */
@ -53,13 +52,6 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
irq += RISCV_IRQ_ASYNC;
}
/* NOTE: In case of ecall, we need to adjust mepc in the context */
if (RISCV_IRQ_ECALLM == irq)
{
*mepc += 4;
}
/* Acknowledge the interrupt */
riscv_ack_irq(irq);

8
arch/risc-v/src/c906/c906_irq_dispatch.c
View File

@ -52,7 +52,6 @@
void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
{
int irq = (vector >> RV_IRQ_MASK) | (vector & 0xf);
uintptr_t *mepc = regs;
/* Firstly, check if the irq is machine external interrupt */
@ -65,13 +64,6 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
irq = val + C906_IRQ_PERI_START;
}
/* NOTE: In case of ecall, we need to adjust mepc in the context */
if (RISCV_IRQ_ECALLM == irq || RISCV_IRQ_ECALLU == irq)
{
*mepc += 4;
}
/* Acknowledge the interrupt */
riscv_ack_irq(irq);

8
arch/risc-v/src/common/riscv_doirq.c
View File

@ -61,6 +61,14 @@ uintptr_t *riscv_doirq(int irq, uintptr_t *regs)
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
/* NOTE: In case of ecall, we need to adjust mepc in the context */
if (irq >= RISCV_IRQ_ECALLU && irq <= RISCV_IRQ_ECALLM)
{
regs[REG_EPC] += 4;
}
/* Current regs non-zero indicates that we are processing an interrupt;
* CURRENT_REGS is also used to manage interrupt level context switches.
*

5
arch/risc-v/src/esp32c3/esp32c3_irq.c
View File

@ -391,11 +391,6 @@ IRAM_ATTR uintptr_t *esp32c3_dispatch_irq(uintptr_t mcause, uintptr_t *regs)
irq = mcause;
}
if (mcause == RISCV_IRQ_ECALLM)
{
regs[REG_EPC] += 4;
}
regs = riscv_doirq(irq, regs);
/* Toggle the bit back to zero. */

8
arch/risc-v/src/fe310/fe310_irq_dispatch.c
View File

@ -51,7 +51,6 @@
void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
{
int irq = (vector >> RV_IRQ_MASK) | (vector & 0xf);
uintptr_t *mepc = regs;
/* Firstly, check if the irq is machine external interrupt */
@ -64,13 +63,6 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
irq += val;
}
/* NOTE: In case of ecall, we need to adjust mepc in the context */
if (RISCV_IRQ_ECALLM == irq)
{
*mepc += 4;
}
/* Acknowledge the interrupt */
riscv_ack_irq(irq);

8
arch/risc-v/src/k210/k210_irq_dispatch.c
View File

@ -53,7 +53,6 @@
void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
{
int irq = (vector >> RV_IRQ_MASK) | (vector & 0xf);
uintptr_t *mepc = regs;
/* Firstly, check if the irq is machine external interrupt */
@ -66,13 +65,6 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
irq += val;
}
/* NOTE: In case of ecall, we need to adjust mepc in the context */
if (RISCV_IRQ_ECALLM == irq || RISCV_IRQ_ECALLU == irq)
{
*mepc += 4;
}
/* Acknowledge the interrupt */
riscv_ack_irq(irq);

8
arch/risc-v/src/litex/litex_irq_dispatch.c
View File

@ -50,7 +50,6 @@
void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
{
int irq = (vector >> RV_IRQ_MASK) | (vector & 0xf);
uintptr_t *mepc = regs;
int i;
/* Firstly, check if the irq is machine external interrupt */
@ -80,13 +79,6 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
irq += val;
}
/* NOTE: In case of ecall, we need to adjust mepc in the context */
if (RISCV_IRQ_ECALLM == irq)
{
*mepc += 4;
}
/* Acknowledge the interrupt */
riscv_ack_irq(irq);

8
arch/risc-v/src/mpfs/mpfs_irq_dispatch.c
View File

@ -50,7 +50,6 @@
void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
{
int irq = (vector & 0x3f);
uintptr_t *epc = regs;
if ((vector & RISCV_IRQ_BIT) != 0)
{
@ -70,13 +69,6 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
irq = MPFS_IRQ_EXT_START + ext;
}
/* NOTE: In case of ecall, we need to adjust epc in the context */
if (irq == RISCV_IRQ_ECALLM || irq == RISCV_IRQ_ECALLU)
{
*epc += 4;
}
/* Acknowledge the interrupt */
riscv_ack_irq(irq);

8
arch/risc-v/src/qemu-rv/qemu_rv_irq_dispatch.c
View File

@ -56,7 +56,6 @@
void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
{
int irq = (vector >> RV_IRQ_MASK) | (vector & 0xf);
uintptr_t *mepc = regs;
/* Firstly, check if the irq is machine external interrupt */
@ -69,13 +68,6 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
irq += val;
}
/* NOTE: In case of ecall, we need to adjust mepc in the context */
if (RISCV_IRQ_ECALLM == irq)
{
*mepc += 4;
}
/* MEXT means no interrupt */
if (RISCV_IRQ_MEXT != irq)

8
arch/risc-v/src/rv32m1/rv32m1_irq_dispatch.c
View File

@ -53,16 +53,8 @@ void *rv32m1_dispatch_irq(uintptr_t vector, uintptr_t *regs)
{
uint32_t vec = vector & 0x1f;
int irq = (vector >> RV_IRQ_MASK) + vec;
uintptr_t *mepc = regs;
int irqofs = 0;
/* NOTE: In case of ecall, we need to adjust mepc in the context */
if (RISCV_IRQ_ECALLM == irq)
{
*mepc += 4;
}
if (RV32M1_IRQ_INTMUX0 <= irq)
{
uintptr_t chn = irq - RV32M1_IRQ_INTMUX0;