SAMV71-XULT: Add support for SDRAM (unverified)
This commit is contained in:
Gregory Nutt
parent
6c262a4dfb
commit
93a58ea955
@ -42,7 +42,7 @@ AOBJS = $(ASRCS:.S=$(OBJEXT))
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CSRCS = sam_boot.c
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CSRCS = sam_boot.c
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ifeq ($(CONFIG_SAMA5_SDRAMC),y)
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ifeq ($(CONFIG_SAMV7_SDRAMC),y)
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CSRCS += sam_sdram.c
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CSRCS += sam_sdram.c
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endif
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endif
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@ -71,6 +71,14 @@
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void sam_boardinitialize(void)
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void sam_boardinitialize(void)
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{
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{
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#ifdef CONFIG_SAMV7_SDRAMC
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/* Configure SDRAM if it has been enabled in the NuttX configuration. Here we
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* assume, of course, that we are not running out SDRAM.
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*/
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sam_sdram_config();
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#endif
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/* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function
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/* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function
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* sam_spiinitialize() has been brought into the link.
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* sam_spiinitialize() has been brought into the link.
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*/
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*/
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281
configs/samv71-xult/src/sam_sdram.c
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281
configs/samv71-xult/src/sam_sdram.c
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@ -0,0 +1,281 @@
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/****************************************************************************
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* configs/samv71-xult/src/sam_sdram.c
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Most of this file derives from Atmel sample code for the SAMV71-XULT
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* board. That sample code has licensing that is compatible with the NuttX
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* modified BSD license:
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*
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* Copyright (c) 2012, Atmel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor Atmel nor the names of its contributors may
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* be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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#include "up_arch.h"
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#include "sam_periphclks.h"
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#include "chip/sam_memorymap.h"
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#include "chip/sam_pinmap.h"
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#include "chip/sam_pmc.h"
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#include "chip/sam_matrix.h"
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#include "chip/sam_sdramc.h"
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#include "samv71-xult.h"
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#ifdef CONFIG_SAMV7_SDRAMC
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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/************************************************************************************
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* Name: sam_sdram_config
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*
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* Description:
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* Configures the on-board SDRAM. SAMV71 Xplained Ultra features one external
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* IS42S16100E-7BLI, 512Kx16x2, 10ns, SDRAM. SDRAM0 is connected to chip select
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* NCS1.
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*
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* Input Parameters:
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* None
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*
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* Assumptions:
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* The DDR memory regions is configured as strongly ordered memory. When we
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* complete initialization of SDRAM and it is ready for use, we will make DRAM
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* into normal memory.
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*
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************************************************************************************/
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void sam_sdram_config(void)
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{
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volatile uint8_t *psdram = (uint8_t *)SAM_SDRAMCS_BASE;
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uint32_t regval;
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int i;
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/* Configure SDRAM pins */
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sam_configgpio(GPIO_SMC_D0);
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sam_configgpio(GPIO_SMC_D1);
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sam_configgpio(GPIO_SMC_D2);
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sam_configgpio(GPIO_SMC_D3);
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sam_configgpio(GPIO_SMC_D4);
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sam_configgpio(GPIO_SMC_D5);
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sam_configgpio(GPIO_SMC_D6);
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sam_configgpio(GPIO_SMC_D7);
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sam_configgpio(GPIO_SMC_D8);
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sam_configgpio(GPIO_SMC_D9);
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sam_configgpio(GPIO_SMC_D10);
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sam_configgpio(GPIO_SMC_D11);
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sam_configgpio(GPIO_SMC_D12);
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sam_configgpio(GPIO_SMC_D13);
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sam_configgpio(GPIO_SMC_D14);
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sam_configgpio(GPIO_SMC_D15);
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sam_configgpio(GPIO_SMC_A0);
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sam_configgpio(GPIO_SMC_A1);
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sam_configgpio(GPIO_SMC_A2);
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sam_configgpio(GPIO_SMC_A3);
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sam_configgpio(GPIO_SMC_A4);
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sam_configgpio(GPIO_SMC_A5);
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sam_configgpio(GPIO_SMC_A6);
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sam_configgpio(GPIO_SMC_A7);
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sam_configgpio(GPIO_SMC_A8);
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sam_configgpio(GPIO_SMC_A9);
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sam_configgpio(GPIO_SDRAMC_A10_1);
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sam_configgpio(GPIO_SDRAMC_CAS);
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sam_configgpio(GPIO_SDRAMC_RAS);
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sam_configgpio(GPIO_SDRAMC_CKE);
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sam_configgpio(GPIO_SDRAMC_CK);
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sam_configgpio(GPIO_SDRAMC_CS_1);
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sam_configgpio(GPIO_SMC_NBS0);
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sam_configgpio(GPIO_SMC_NBS1);
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sam_configgpio(GPIO_SDRAMC_WE);
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sam_configgpio(GPIO_SDRAMC_BA0);
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/* Enable the SDRAMC peripheral */
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sam_sdramc_enableclk();
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regval = getreg32(SAM_MATRIX_CCFG_SMCNFCS);
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regval |= MATRIX_CCFG_SMCNFCS_SDRAMEN;
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putreg32(regval, SAM_MATRIX_CCFG_SMCNFCS);
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/* 1. SDRAM features must be set in the configuration register:
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* asynchronous timings (TRC, TRAS, etc.), number of columns, rows, CAS
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* latency, and the data bus width.
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*
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* SDRAMC_CR_NC_COL8 8 column bits
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* SDRAMC_CR_NR_ROW11 1 row bits
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* SDRAMC_CR_NB_BANK2 2 banks
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* SDRAMC_CR_CAS_LATENCY3 3 cycle CAS latency
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* SDRAMC_CR_DBW 16 bit
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* SDRAMC_CR_TWR(4) 4 cycle write recovery delay
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* SDRAMC_CR_TRCTRFC(11) 63 ns min
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* SDRAMC_CR_TRP(5) 21 ns min Command period (PRE to ACT)
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* SDRAMC_CR_TRCD(5) 21 ns min Active Command to read/Write Command delay time
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* SDRAMC_CR_TRAS(8) 42 ns min Command period (ACT to PRE)
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* SDRAMC_CR_TXSR(13) 70 ns min Exit self-refresh to active time
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*/
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regval = SDRAMC_CR_NC_COL8 | /* 8 column bits */
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SDRAMC_CR_NR_ROW11 | /* 11 row bits */
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SDRAMC_CR_NB_BANK2 | /* 2 banks */
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SDRAMC_CR_CAS_LATENCY3 | /* 3 cycle CAS latency */
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SDRAMC_CR_DBW | /* 16 bit */
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SDRAMC_CR_TWR(4) | /* 4 cycle write recovery delay */
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SDRAMC_CR_TRCTRFC(11) | /* 63 ns min */
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SDRAMC_CR_TRP(5) | /* 21 ns min Command period (PRE to ACT) */
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SDRAMC_CR_TRCD(5) | /* 21 ns min Active Command to read/Write Command delay time */
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SDRAMC_CR_TRAS(8) | /* 42 ns min Command period (ACT to PRE) */
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SDRAMC_CR_TXSR(13); /* 70 ns min Exit self-refresh to active time */
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putreg32(regval, SAM_SDRAMC_CR);
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/* 2. For mobile SDRAM, temperature-compensated self refresh (TCSR), drive
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* strength (DS) and partial array self refresh (PASR) must be set in
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* the Low Power Register.
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*/
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/* 3. The SDRAM memory type must be set in the Memory Device Register.*/
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putreg32(SDRAMC_MDR_SDRAM, SAM_SDRAMC_MDR);
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/* 4. A minimum pause of 200 usec is provided to precede any signal toggle.*/
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up_udelay(200);
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/* 5. A NOP command is issued to the SDRAM devices. The application must
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* set Mode to 1 in the Mode Register and perform a write access to any
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* SDRAM address.
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*/
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putreg32(SDRAMC_MR_MODE_NOP, SAM_SDRAMC_MR);
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*psdram = 0;
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up_udelay(200);
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/* 6. An All Banks Precharge command is issued to the SDRAM devices. The
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* application must set Mode to 2 in the Mode Register and perform a
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* write access to any SDRAM address.
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*/
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putreg32(SDRAMC_MR_MODE_PRECHARGE, SAM_SDRAMC_MR);
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*psdram = 0;
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up_udelay(200);
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/* 7. Eight auto-refresh (CBR) cycles are provided. The application must
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* set the Mode to 4 in the Mode Register and perform a write access to
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* any SDRAM location eight times.
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*/
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for (i = 0 ; i< 8; i++)
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{
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putreg32(SDRAMC_MR_MODE_AUTOREFRESH, SAM_SDRAMC_MR);
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*psdram = 0;
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}
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up_udelay(200);
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/* 8. A Mode Register set (MRS) cycle is issued to program the parameters
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* of the SDRAM devices, in particular CAS latency and burst length.
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* The application must set Mode to 3 in the Mode Register and perform
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* a write access to the SDRAM. The write address must be chosen so
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* that BA[1:0] are set to 0. For example, with a 16-bit 128 MB SDRAM
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* (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access
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* should be done at the address 0x70000000.
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*/
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putreg32(SDRAMC_MR_MODE_LOADMODE, SAM_SDRAMC_MR);
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*psdram = 0;
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up_udelay(200);
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/* 9. For mobile SDRAM initialization, an Extended Mode Register set
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* (EMRS) cycle is issued to program the SDRAM parameters (TCSR, PASR,
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* DS). The application must set Mode to 5 in the Mode Register and
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* perform a write access to the SDRAM. The write address must be
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* chosen so that BA[1] or BA[0] are set to 1.
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*
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* For example, with a 16-bit 128 MB SDRAM, (12 rows, 9 columns, 4
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* banks) bank address the SDRAM write access should be done at the
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* address 0x70800000 or 0x70400000.
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*/
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//putreg32(SDRAMC_MR_MODE_EXTLOADMODE, SDRAMC_MR_MODE_EXT_LOAD_MODEREG);
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// *((uint8_t *)(psdram + SDRAM_BA0)) = 0;
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/* 10. The application must go into Normal Mode, setting Mode to 0 in the
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* Mode Register and performing a write access at any location in the
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* SDRAM.
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*/
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putreg32(SDRAMC_MR_MODE_NORMAL, SAM_SDRAMC_MR);
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*psdram = 0;
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up_udelay(200);
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/* 11. Write the refresh rate into the count field in the SDRAMC Refresh
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* Timer register. (Refresh rate = delay between refresh cycles). The
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* SDRAM device requires a refresh every 15.625 usec or 7.81 usec. With
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* a 100 MHz frequency, the Refresh Timer Counter Register must be set
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* with the value 1562(15.625 usec x 100 MHz) or 781(7.81 usec x 100
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* MHz).
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*
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* For IS42S16100E, 2048 refresh cycle every 32ms, every 15.625 usec
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*/
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putreg32(1562, SAM_SDRAMC_TR);
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regval = getreg32(SAM_SDRAMC_CFR1);
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regval |= SDRAMC_CFR1_UNAL;
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putreg32(regval, SAM_SDRAMC_CFR1);
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/* After initialization, the SDRAM devices are fully functional. */
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}
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#endif /* CONFIG_SAMV7_SDRAMC */
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@ -286,7 +286,7 @@
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*
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*
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************************************************************************************/
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************************************************************************************/
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#ifdef CONFIG_SAMA5_SDRAMC
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#ifdef CONFIG_SAMV7_SDRAMC
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void sam_sdram_config(void);
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void sam_sdram_config(void);
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#else
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#else
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# define sam_sdram_config(t)
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# define sam_sdram_config(t)
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