Add a bare bones framework that will do nothing more than support configuration for the Atmel SAMV71 Xplained Ultra board. Very much a work in progress.
This commit is contained in:
Gregory Nutt
parent
9bcdf974a0
commit
93a6b16718
@ -171,6 +171,7 @@ config ARCH_CHIP_SAMV7
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bool "Atmel SAMV7"
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select ARCH_HAVE_CMNVECTOR
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select ARMV7M_CMNVECTOR
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select ARCH_CORTEXM7
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select ARCH_HAVE_MPU
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select ARCH_HAVE_RAMFUNCS
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---help---
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95
arch/arm/src/samv7/Make.defs
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95
arch/arm/src/samv7/Make.defs
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@ -0,0 +1,95 @@
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############################################################################
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# arch/arm/src/samv7/Make.defs
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#
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# Copyright (C) 2009-2011, 2013-2015 Gregory Nutt. All rights reserved.
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# Author: Gregory Nutt <gnutt@nuttx.org>
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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#
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# 1. Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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# 2. Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in
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# the documentation and/or other materials provided with the
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# distribution.
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# 3. Neither the name NuttX nor the names of its contributors may be
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# used to endorse or promote products derived from this software
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# without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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# POSSIBILITY OF SUCH DAMAGE.
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#
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############################################################################
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# The start-up, "head", file
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HEAD_ASRC = sam_vectors.S
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# Common ARM and Cortex-M3 files
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CMN_UASRCS =
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CMN_UCSRCS =
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CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
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CMN_ASRCS += vfork.S
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CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c
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CMN_CSRCS += up_mdelay.c up_udelay.c up_exit.c up_idle.c up_initialize.c
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CMN_CSRCS += up_initialstate.c up_interruptcontext.c up_memfault.c up_modifyreg8.c
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CMN_CSRCS += up_modifyreg16.c up_modifyreg32.c up_releasepending.c
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CMN_CSRCS += up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c
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CMN_CSRCS += up_sigdeliver.c up_stackframe.c up_unblocktask.c up_usestack.c
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CMN_CSRCS += up_doirq.c up_hardfault.c up_svcall.c up_vfork.c
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# Configuration-dependent common files
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ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
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ifeq ($(CONFIG_ARMV7M_ARMV7M_LAZYFPU),y)
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CMN_ASRCS += up_lazyexception.S
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else
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CMN_ASRCS += up_exception.S
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endif
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CMN_CSRCS += up_vectors.c
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endif
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ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
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CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c
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endif
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ifeq ($(CONFIG_ARCH_MEMCPY),y)
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CMN_ASRCS += up_memcpy.S
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endif
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ifeq ($(CONFIG_BUILD_PROTECTED),y)
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CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
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ifneq ($(CONFIG_DISABLE_SIGNALS),y)
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CMN_CSRCS += up_signal_dispatch.c
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CMN_UASRCS += up_signal_handler.S
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endif
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endif
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ifeq ($(CONFIG_ELF),y)
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CMN_CSRCS += up_elf.c
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endif
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ifeq ($(CONFIG_STACK_COLORATION),y)
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CMN_CSRCS += up_checkstack.c
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endif
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# Required SAM3/4 files
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CHIP_ASRCS =
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CHIP_CSRCS = sam_start.c
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# Configuration-dependent SAM3/4 files
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342
arch/arm/src/samv7/sam_start.c
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342
arch/arm/src/samv7/sam_start.c
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@ -0,0 +1,342 @@
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/****************************************************************************
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* arch/arm/src/samv7/sam_start.c
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <assert.h>
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#include <debug.h>
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#include <nuttx/init.h>
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#include <arch/board/board.h>
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#include "up_arch.h"
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#include "up_internal.h"
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#include "sam_clockconfig.h"
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#include "sam_lowputc.h"
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#include "sam_userspace.h"
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#ifdef CONFIG_ARCH_FPU
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# include "nvic.h"
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#endif
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/****************************************************************************
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* Private Function prototypes
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****************************************************************************/
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#ifdef CONFIG_ARCH_FPU
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static inline void sam_fpuconfig(void);
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#endif
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#ifdef CONFIG_STACK_COLORATION
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static void go_os_start(void *pv, unsigned int nbytes)
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__attribute__ ((naked,no_instrument_function,noreturn));
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#endif
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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#ifdef CONFIG_ARMV7M_STACKCHECK
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/* we need to get r10 set before we can allow instrumentation calls */
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void __start(void) __attribute__ ((no_instrument_function));
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#endif
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/****************************************************************************
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* Name: showprogress
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*
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* Description:
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* Print a character on the UART to show boot status.
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*
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****************************************************************************/
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#ifdef CONFIG_DEBUG
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# define showprogress(c) up_lowputc(c)
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#else
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# define showprogress(c)
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#endif
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/****************************************************************************
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* Name: sam_fpuconfig
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*
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* Description:
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* Configure the FPU. Relative bit settings:
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*
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* CPACR: Enables access to CP10 and CP11
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* CONTROL.FPCA: Determines whether the FP extension is active in the
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* current context:
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* FPCCR.ASPEN: Enables automatic FP state preservation, then the
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* processor sets this bit to 1 on successful completion of any FP
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* instruction.
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* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
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* done, the processor reserves space on the stack for the FP state,
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* but does not save that state information to the stack.
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*
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* Software must not change the value of the ASPEN bit or LSPEN bit while either:
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* - the CPACR permits access to CP10 and CP11, that give access to the FP
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* extension, or
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* - the CONTROL.FPCA bit is set to 1
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*
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****************************************************************************/
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#ifdef CONFIG_ARCH_FPU
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#if defined(CONFIG_ARMV7M_CMNVECTOR) && !defined(CONFIG_ARMV7M_LAZYFPU)
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static inline void sam_fpuconfig(void)
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{
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uint32_t regval;
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/* Set CONTROL.FPCA so that we always get the extended context frame
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* with the volatile FP registers stacked above the basic context.
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*/
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regval = getcontrol();
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regval |= (1 << 2);
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setcontrol(regval);
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/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
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* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
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* are going to turn on CONTROL.FPCA for all contexts.
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*/
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regval = getreg32(NVIC_FPCCR);
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regval &= ~((1 << 31) | (1 << 30));
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putreg32(regval, NVIC_FPCCR);
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/* Enable full access to CP10 and CP11 */
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regval = getreg32(NVIC_CPACR);
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regval |= ((3 << (2*10)) | (3 << (2*11)));
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putreg32(regval, NVIC_CPACR);
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}
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#else
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static inline void sam_fpuconfig(void)
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{
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uint32_t regval;
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/* Clear CONTROL.FPCA so that we do not get the extended context frame
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* with the volatile FP registers stacked in the saved context.
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*/
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regval = getcontrol();
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regval &= ~(1 << 2);
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setcontrol(regval);
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/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
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* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
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* are going to keep CONTROL.FPCA off for all contexts.
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*/
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regval = getreg32(NVIC_FPCCR);
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regval &= ~((1 << 31) | (1 << 30));
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putreg32(regval, NVIC_FPCCR);
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/* Enable full access to CP10 and CP11 */
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regval = getreg32(NVIC_CPACR);
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regval |= ((3 << (2*10)) | (3 << (2*11)));
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putreg32(regval, NVIC_CPACR);
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}
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#endif
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#else
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# define sam_fpuconfig()
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#endif
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/****************************************************************************
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* Name: go_os_start
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*
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* Description:
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* Set the IDLE stack to the
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*
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****************************************************************************/
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#ifdef CONFIG_STACK_COLORATION
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static void go_os_start(void *pv, unsigned int nbytes)
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{
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/* Set the IDLE stack to the stack coloration value then jump to
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* os_start(). We take extreme care here because were currently
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* executing on this stack.
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*
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* We want to avoid sneak stack access generated by the compiler.
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*/
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__asm__ __volatile__
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(
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"\tmov r1, r1, lsr #2\n" /* R1 = nwords = nbytes >> 2 */
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"\tbeq 2f\n" /* (should not happen) */
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"\tbic r0, r0, #3\n" /* R0 = Aligned stackptr */
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"\tmovw r2, #0xbeef\n" /* R2 = STACK_COLOR = 0xdeadbeef */
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"\tmovt r2, #0xdead\n"
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"1:\n" /* Top of the loop */
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"\tsub r1, r1, #1\n" /* R1 nwords-- */
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"\tcmp r1, #0\n" /* Check (nwords == 0) */
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"\tstr r2, [r0], #4\n" /* Save stack color word, increment stackptr */
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"\tbne 1b\n" /* Bottom of the loop */
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"2:\n"
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"\tmov r14, #0\n" /* LR = return address (none) */
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"\tb os_start\n" /* Branch to os_start */
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);
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}
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: _start
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*
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* Description:
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* This is the reset entry point.
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*
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****************************************************************************/
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void __start(void)
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{
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const uint32_t *src;
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uint32_t *dest;
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#ifdef CONFIG_ARMV7M_STACKCHECK
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/* Set the stack limit before we attempt to call any functions */
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__asm__ volatile ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) : );
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#endif
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/* Clear .bss. We'll do this inline (vs. calling memset) just to be
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* certain that there are no issues with the state of global variables.
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*/
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for (dest = &_sbss; dest < &_ebss; )
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{
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*dest++ = 0;
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}
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/* Move the initialized data section from his temporary holding spot in
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* FLASH into the correct place in SRAM. The correct place in SRAM is
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* give by _sdata and _edata. The temporary location is in FLASH at the
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* end of all of the other read-only data (.text, .rodata) at _eronly.
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*/
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for (src = &_eronly, dest = &_sdata; dest < &_edata; )
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{
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*dest++ = *src++;
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}
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/* Copy any necessary code sections from FLASH to RAM. The correct
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* destination in SRAM is geive by _sramfuncs and _eramfuncs. The
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* temporary location is in flash after the data initalization code
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* at _framfuncs. This must be done before sam_clockconfig() can be
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* called (at least for the SAM4L family).
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*/
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#ifdef CONFIG_ARCH_RAMFUNCS
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for (src = &_framfuncs, dest = &_sramfuncs; dest < &_eramfuncs; )
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{
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*dest++ = *src++;
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}
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#endif
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/* Configure the UART so that we can get debug output as soon as possible */
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sam_clockconfig();
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sam_fpuconfig();
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sam_lowsetup();
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showprogress('A');
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/* Perform early serial initialization */
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#ifdef USE_EARLYSERIALINIT
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up_earlyserialinit();
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#endif
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showprogress('B');
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/* For the case of the separate user-/kernel-space build, perform whatever
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* platform specific initialization of the user memory is required.
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* Normally this just means initializing the user space .data and .bss
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* segements.
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*/
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#ifdef CONFIG_BUILD_PROTECTED
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sam_userspace();
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showprogress('C');
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#endif
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/* Initialize onboard resources */
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sam_boardinitialize();
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showprogress('D');
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#ifdef CONFIG_SAMV7_CMCC
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/* Enable the Cortex-M Cache
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*
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* REVISIT: This logic is complete but I have not yet tried to enable it.
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* I have some questions about how the cache will effect memory mapped
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* register accesses.
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*/
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sam_cmcc_enable();
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#endif
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/* Then start NuttX */
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showprogress('\r');
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showprogress('\n');
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#ifdef CONFIG_STACK_COLORATION
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/* Set the IDLE stack to the coloration value and jump into os_start() */
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go_os_start((FAR void *)&_ebss, CONFIG_IDLETHREAD_STACKSIZE);
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#else
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/* Call os_start() */
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os_start();
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/* Shouldn't get here */
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for (;;);
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#endif
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}
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