sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Early bringup bugfixes

Browse Source 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2753 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2010-06-19 19:30:01 +00:00
parent 89725360e1
commit 93bd6fa7f6
4 changed files with 12 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/src/lpc17xx/lpc17_internal.h
View File

@ -187,7 +187,7 @@
#define GPIO_I2C1_SCL_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN1)
#define GPIO_UART0_TXD (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN2)
#define GPIO_AD0p7 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN2)
#define GPIO_UART0_RXD (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN3
#define GPIO_UART0_RXD (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN3)
#define GPIO_AD0p6 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN3)
#define GPIO_I2S_RXCLK_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN4)
#define GPIO_CAN2_RD (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN4)

16
arch/arm/src/lpc17xx/lpc17_lowputc.c
View File

@ -48,6 +48,7 @@
#include "up_arch.h"
#include "lpc17_internal.h"
#include "lpc17_syscon.h"
#include "lpc17_uart.h"
#include "lpc17_serial.h"
@ -118,9 +119,9 @@
/* Get stop-bit setting for the console and UART0-3 */
#if CONSOLE_2STOP != 0
# define CONSOLE_LCR_STOP LPC214X_LCR_STOP_2
# define CONSOLE_LCR_STOP UART_LCR_STOP
#else
# define CONSOLE_LCR_STOP LPC214X_LCR_STOP_1
# define CONSOLE_LCR_STOP 0
#endif
/* LCR and FCR values for the console */
@ -209,7 +210,7 @@
/* Then this is the value to use for the DLM and DLL registers */
#define CONSOLE_DL (CONSOLE_NUMERATOR / (CONSOLE_BAUD << 4)
#define CONSOLE_DL (CONSOLE_NUMERATOR / (CONSOLE_BAUD << 4))
/**************************************************************************
* Private Types
@ -297,7 +298,7 @@ void lpc17_lowsetup(void)
regval = getreg32(LPC17_SYSCON_PCONP);
regval &= ~(SYSCON_PCONP_PCUART0|SYSCON_PCONP_PCUART1|
SYSCON_PCONP_PCUART2|SYSCON_PCONP_PCUART3)
SYSCON_PCONP_PCUART2|SYSCON_PCONP_PCUART3);
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
regval |= SYSCON_PCONP_PCUART0;
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
@ -314,7 +315,7 @@ void lpc17_lowsetup(void)
*/
regval = getreg32(LPC17_SYSCON_PCLKSEL0);
regval &= SYSCON_PCLKSEL0_UART1_MASK;
regval &= ~(SYSCON_PCLKSEL0_UART0_MASK|SYSCON_PCLKSEL0_UART1_MASK);
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
regval |= (CONSOLE_CCLKDIV << SYSCON_PCLKSEL0_UART0_SHIFT);
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
@ -323,11 +324,11 @@ void lpc17_lowsetup(void)
putreg32(regval, LPC17_SYSCON_PCLKSEL0);
regval = getreg32(LPC17_SYSCON_PCLKSEL1);
regval &= SYSCON_PCLKSEL0_UART2_MASK;
regval &= ~(SYSCON_PCLKSEL1_UART2_MASK|SYSCON_PCLKSEL1_UART3_SHIFT);
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
regval |= (CONSOLE_CCLKDIV << SYSCON_PCLKSEL1_UART2_SHIFT);
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
regval |= (CONSOLE_CCLKDIV << SYSCON_PCLKSEL1_UART23_SHIFT);
regval |= (CONSOLE_CCLKDIV << SYSCON_PCLKSEL1_UART3_SHIFT);
#endif
putreg32(regval, LPC17_SYSCON_PCLKSEL1);
@ -336,7 +337,6 @@ void lpc17_lowsetup(void)
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
lpc17_configgpio(GPIO_UART0_TXD);
lpc17_configgpio(GPIO_UART0_RXD);
irqrestore(flags);
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
lpc17_configgpio(GPIO_UART1_TXD);
lpc17_configgpio(GPIO_UART1_RXD);

2
arch/arm/src/lpc17xx/lpc17_serial.h
View File

@ -57,7 +57,7 @@
#undef HAVE_UART
#if defined(CONFIG_LPC17_UART0) || defined(CONFIG_LPC17_UART1) || \
defined(CONFIG_LPC17_UART2) || defined(CONFIG_LPC17_UART3)
# define HAVE_UART1
# define HAVE_UART 1
#endif
/* Is there a serial console? There should be at most one defined. It could be on

4
arch/arm/src/lpc17xx/lpc17_syscon.h
View File

@ -296,7 +296,7 @@
#define SYSCON_PCLKSEL0_TMR1_SHIFT (4) /* Bits 4-5: Peripheral clock TIMER1 */
#define SYSCON_PCLKSEL0_TMR1_MASK (3 << SYSCON_PCLKSEL0_TMR1_SHIFT)
#define SYSCON_PCLKSEL0_UART0_SHIFT (6) /* Bits 6-7: Peripheral clock UART0 */
#define SYSCON_PCLKSEL0_UART0_MASK (3 << SYSCON_PCLKSEL0_UART0_MASK)
#define SYSCON_PCLKSEL0_UART0_MASK (3 << SYSCON_PCLKSEL0_UART0_SHIFT)
#define SYSCON_PCLKSEL0_UART1_SHIFT (8) /* Bits 8-9: Peripheral clock UART1 */
#define SYSCON_PCLKSEL0_UART1_MASK (3 << SYSCON_PCLKSEL0_UART1_SHIFT)
/* Bits 10-11: Reserved */
@ -314,7 +314,7 @@
#define SYSCON_PCLKSEL0_ADC_SHIFT (24) /* Bits 24-25: Peripheral clock ADC */
#define SYSCON_PCLKSEL0_ADC_MASK (3 << SYSCON_PCLKSEL0_ADC_SHIFT)
#define SYSCON_PCLKSEL0_CAN1_SHIFT (26) /* Bits 26-27: Peripheral clock CAN1 */
#define SYSCON_PCLKSEL0_CAN1_MASK (3 << SYSCON_PCLKSEL0_CAN1_MASK
#define SYSCON_PCLKSEL0_CAN1_MASK (3 << SYSCON_PCLKSEL0_CAN1_SHIFT
#define SYSCON_PCLKSEL0_CAN2_SHIFT (28) /* Bits 28-29: Peripheral clock CAN2 */
#define SYSCON_PCLKSEL0_CAN2_MASK (3 << SYSCON_PCLKSEL0_CAN2_SHIFT)
#define SYSCON_PCLKSEL0_ACF_SHIFT (30) /* Bits 30-31: Peripheral clock CAN AF */