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SAMD20: Initial debug changes to get clocking

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This commit is contained in:
Gregory Nutt 2014-02-17 11:36:52 -06:00
parent 05b5d78ae1
commit 93ca836b85
6 changed files with 112 additions and 18 deletions
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30
arch/arm/src/samd/chip/sam_gclk.h
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@ -82,6 +82,36 @@
#define GCLK_CLKCTRL_ID_SHIFT (0) /* Bits 0-5: Generic Clock Selection ID */
#define GCLK_CLKCTRL_ID_MASK (0x3f << GCLK_CLKCTRL_ID_SHIFT)
# define GCLK_CLKCTRL_ID(n) ((n) << GCLK_CLKCTRL_ID_SHIFT)
# define GCLK_CLKCTRL_ID_DFLL48M (0 << GCLK_CLKCTRL_ID_SHIFT) /* DFLL48M Reference */
# define GCLK_CLKCTRL_ID_WDT (1 << GCLK_CLKCTRL_ID_SHIFT) /* WDT */
# define GCLK_CLKCTRL_ID_RTC (2 << GCLK_CLKCTRL_ID_SHIFT) /* RTC */
# define GCLK_CLKCTRL_ID_EIC (3 << GCLK_CLKCTRL_ID_SHIFT) /* EIC */
# define GCLK_CLKCTRL_ID_EVSYS(n) (((n)+4) << GCLK_CLKCTRL_ID_SHIFT)
# define GCLK_CLKCTRL_ID_EVSYS1 (5 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_1 */
# define GCLK_CLKCTRL_ID_EVSYS1 (5 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_1 */
# define GCLK_CLKCTRL_ID_EVSYS2 (6 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_2 */
# define GCLK_CLKCTRL_ID_EVSYS3 (7 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_3 */
# define GCLK_CLKCTRL_ID_EVSYS4 (8 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_4 */
# define GCLK_CLKCTRL_ID_EVSYS5 (9 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_5 */
# define GCLK_CLKCTRL_ID_EVSYS6 (10 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_6 */
# define GCLK_CLKCTRL_ID_EVSYS7 (11 << GCLK_CLKCTRL_ID_SHIFT) /* EVSYS_CHANNEL_7 */
# define GCLK_CLKCTRL_ID_SERCOMS (12 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOMx_SLOW */
# define GCLK_CLKCTRL_ID_SERCOMC(n) (((n)+13) << GCLK_CLKCTRL_ID_SHIFT)
# define GCLK_CLKCTRL_ID_SERCOM0C (13 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOM0_CORE */
# define GCLK_CLKCTRL_ID_SERCOM1C (14 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOM1_CORE */
# define GCLK_CLKCTRL_ID_SERCOM2C (15 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOM2_CORE */
# define GCLK_CLKCTRL_ID_SERCOM3C (16 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOM3_CORE */
# define GCLK_CLKCTRL_ID_SERCOM4C (17 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOM4_CORE */
# define GCLK_CLKCTRL_ID_SERCOM5C (18 << GCLK_CLKCTRL_ID_SHIFT) /* SERCOM5_CORE */
# define GCLK_CLKCTRL_ID_TC01 (19 << GCLK_CLKCTRL_ID_SHIFT) /* TC0,TC1 */
# define GCLK_CLKCTRL_ID_TC23 (20 << GCLK_CLKCTRL_ID_SHIFT) /* TC2,TC3 */
# define GCLK_CLKCTRL_ID_TC45 (21 << GCLK_CLKCTRL_ID_SHIFT) /* TC4,TC5 */
# define GCLK_CLKCTRL_ID_TC67 (22 << GCLK_CLKCTRL_ID_SHIFT) /* TC6,TC7 */
# define GCLK_CLKCTRL_ID_ADC (23 << GCLK_CLKCTRL_ID_SHIFT) /* ADC */
# define GCLK_CLKCTRL_ID_ACDIG (24 << GCLK_CLKCTRL_ID_SHIFT) /* AC_DIG */
# define GCLK_CLKCTRL_ID_ACANA (25 << GCLK_CLKCTRL_ID_SHIFT) /* AC_ANA */
# define GCLK_CLKCTRL_ID_DAC (26 << GCLK_CLKCTRL_ID_SHIFT) /* DAC */
# define GCLK_CLKCTRL_ID_PTC (27 << GCLK_CLKCTRL_ID_SHIFT) /* PTC */
#define GCLK_CLKCTRL_GEN_SHIFT (8) /* Bits 8-11: Generic Clock Generator */
#define GCLK_CLKCTRL_GEN_MASK (15 << GCLK_CLKCTRL_GEN_SHIFT)
# define GCLK_CLKCTRL_GEN(n) ((n) << GCLK_CLKCTRL_GEN_SHIFT) /* Generic clock generator n */

5
arch/arm/src/samd/chip/sam_sysctrl.h
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@ -105,8 +105,11 @@
#define SYSCTRL_INT_BOD33RDY (1 << 9) /* Bit 9: BOD33 ready interrupt */
#define SYSCTRL_INT_BOD33DET (1 << 10) /* Bit 10: BOD33 detection interrupt */
#define SYSCTRL_INT_B33SRDY (1 << 11) /* Bit 11: BOD33 synchronization ready interrupt */
#define SYSCTRL_INT_BOD12RDY (1 << 12) /* Bit 12: BOD12 ready interrupt */
#define SYSCTRL_INT_BOD12DET (1 << 13) /* Bit 13: BOD12 detection interrupt */
#define SYSCTRL_INT_B12SRDY (1 << 14) /* Bit 14: BOD12 synchronization ready interrupt */
#define SYSCTRL_INT_ALL (0x00000fff)
#define SYSCTRL_INT_ALL (0x00007fff)
/* External multi-purpose crystal oscillator control register */

57
arch/arm/src/samd/sam_clockconfig.c
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@ -487,6 +487,26 @@ static inline void sam_osc32k_config(void)
* BOARD_OSC8M_ONDEMAND - Boolean (defined / not defined)
* BOARD_OSC8M_RUNINSTANDBY - Boolean (defined / not defined)
*
* On any reset the synchronous clocks start to their initial state:
*
* OSC8M is enabled and divided by 8
* GCLK_MAIN uses OSC8M as source
* CPU and BUS clocks are undivided
*
* The reset state of the OSC8M register is:
*
* FFxx CCCC CCCC CCCC xxxx xxPP ORxx xxEx
* xx00 xxxx xxxx xxxx 0000 0011 1000 0010
*
* FRANGE FF Loaded from FLASH calibration at startup
* CALIB CCC...C Loaded from FLASH calibration at startup
* PRESC PP 3 = Divide by 8
* ONDEMAND O 1
* RUNSTBY R 0
* ENABLE 1 1
*
* NOTE that since we are running from OSC8M, it cannot be disable!
*
* Input Parameters:
* None
*
@ -501,21 +521,28 @@ static inline void sam_osc8m_config(void)
/* Configure OSC8M */
regval = BOARD_OSC8M_PRESCALER;
regval = getreg32(SAM_SYSCTRL_OSC8M);
regval &= ~(SYSCTRL_OSC8M_PRESC_MASK | SYSCTRL_OSC8M_ONDEMAND |
SYSCTRL_OSC8M_RUNSTDBY);
/* Select the prescaler */
regval |= (BOARD_OSC8M_PRESCALER | SYSCTRL_OSC8M_ENABLE);
#ifdef BOARD_OSC8M_ONDEMAND
/* Select on-demand oscillator controls */
regval |= SYSCTRL_OSC8M_ONDEMAND;
#endif
#ifdef BOARD_OSC8M_RUNINSTANDBY
/* The oscillator continues to run in standby sleep mode */
regval |= SYSCTRL_OSC8M_RUNSTDBY;
#endif
putreg32(regval, SAM_SYSCTRL_OSC8M);
/* Set the OSC8M configuration */
/* Then enable OSC8M */
regval |= SYSCTRL_OSC8M_ENABLE;
putreg32(regval, SAM_SYSCTRL_OSC8M);
}
@ -596,7 +623,7 @@ static inline void sam_dfll_config(void)
#ifndef BOARD_DFLL_OPENLOOP
regval = SYSCTRL_DFLLMUL_CSTEP(BOARD_DFLL_MAXCOARSESTEP) |
SYSCTRL_DFLLMUL_FSTEP(BOARD_DFLL_MAXFINESTEP) |
SYSCTRL_DFLLMUL_MUL(BOARD_DFLL_MULTIPLIER);
SYSCTRL_DFLLMUL_MUL(BOARD_DFLL_MULTIPLIER);
putreg32(regval, SAM_SYSCTRL_DFLLMUL);
#else
putreg32(0, SAM_SYSCTRL_DFLLMUL);
@ -605,8 +632,8 @@ static inline void sam_dfll_config(void)
/* Set up the DFLL value register */
regval = SYSCTRL_DFLLVAL_COARSE(BOARD_DFLL_COARSEVALUE) |
SYSCTRL_DFLLVAL_FINE(BOARD_DFLL_FINEVALUE);
putreg32(regval, SAM_SYSCTRL_DFLLMUL);
SYSCTRL_DFLLVAL_FINE(BOARD_DFLL_FINEVALUE);
putreg32(regval, SAM_SYSCTRL_DFLLVAL);
/* Finally, set the state of the ONDEMAND bit if necessary */
@ -642,25 +669,25 @@ static inline void sam_dfll_reference(void)
{
uint16_t regval;
/* Disabled the generic clock */
/* Disabled the DFLL reference clock */
regval = GCLK_CLKCTRL_GEN0;
regval = GCLK_CLKCTRL_ID_DFLL48M;
putreg16(regval, SAM_GCLK_CLKCTRL);
/* Wait for the clock to become disabled */
while ((getreg16(SAM_GCLK_CLKCTRL) & GCLK_CLKCTRL_CLKEN) != 0);
/* Select the configured clock generator and configure the GCLK output
* (always Generic clock generator 0)
/* Select the configured clock generator as the source for the DFLL
* reference clock.
*
* NOTE: We could enable write lock here to prevent further modification
*/
regval = (GCLK_CLKCTRL_GEN0 | BOARD_DFLL_SRCGCLKGEN);
regval = (BOARD_DFLL_SRCGCLKGEN | GCLK_CLKCTRL_ID_DFLL48M);
putreg16(regval, SAM_GCLK_CLKCTRL);
/* Enable the generic clock */
/* Enable the DFLL reference clock */
regval |= GCLK_CLKCTRL_CLKEN;
putreg16(regval, SAM_GCLK_CLKCTRL);
@ -786,7 +813,7 @@ static inline void sam_gclk_config(FAR const struct sam_gclkconfig_s *config)
/* Enable the clock generator */
genctrl |= GCLK_GENCTRL_GENEN;
putreg16(genctrl, SAM_GCLK_GENCTRL);
putreg32(genctrl, SAM_GCLK_GENCTRL);
/* Wait for synchronization */

22
configs/samd20-xplained/README.txt
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@ -23,6 +23,7 @@ Contents
- NuttX EABI "buildroot" Toolchain
- LEDs
- Serial Consoles
- Atmel Studio 6.1
- SAMD20 Xplained Pro-specific Configuration Options
- Configurations
@ -426,6 +427,27 @@ Serial Consoles
PA24 SERCOM3 / USART TXD
PA25 SERCOM3 / USART RXD
Atmel Studio 6.1
^^^^^^^^^^^^^^^^
Loading Code into FLASH:
-----------------------
Tools menus: Tool -> Device Programming.
Debugging the NuttX Object File
-------------------------------
1) Rename object file from nutt to nuttx.elf. That is an extension that
will be recognized by the file menu.
2) File menu: File -> Open -> Open object file for debugging
- Select nuttx.elf object file
- Select AT91SAMD20J18
- Select files for symbols as desired
- Select debugger
3) Debug menu: Debug -> Start debugging and break
- This will reload the nuttx.elf file into FLASH
SAMD20 Xplained Pro-specific Configuration Options
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

14
configs/samd20-xplained/include/board.h
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@ -335,9 +335,19 @@
#define BOARD_PBC_FREQUENCY (BOARD_MCK_FREQUENCY)
#define BOARD_PBD_FREQUENCY (BOARD_MCK_FREQUENCY)
/* FLASH wait states */
/* FLASH wait states
*
* Vdd Range Wait states Maximum Operating Frequency
* ------------- -------------- ---------------------------
* 1.62V to 2.7V 0 14 MHz
* 1 28 MHz
* 2 42 MHz
* 3 48 MHz
* 2.7V to 3.63V 0 24 MHz
* 1 48 MHz
*/
#define BOARD_FLASH_WAITSTATES 0
#define BOARD_FLASH_WAITSTATES 1
/* SERCOM definitions ***************************************************************/
/* SERCOM4 is available on connectors EXT1 and EXT3

2
configs/samd20-xplained/scripts/flash.ld
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@ -44,7 +44,9 @@ MEMORY
}
OUTPUT_ARCH(arm)
EXTERN(_vectors)
ENTRY(_stext)
SECTIONS
{
.text : {