From 93d75129de204ba982dc046676390ebeb561e287 Mon Sep 17 00:00:00 2001 From: Huang Qi Date: Thu, 18 Apr 2024 16:44:57 +0800 Subject: [PATCH] riscv: Add Vector CSRs to csr.h The CSR register definitions from RVV 1.0 spec: https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-registers Signed-off-by: Huang Qi --- arch/risc-v/include/csr.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/risc-v/include/csr.h b/arch/risc-v/include/csr.h index 90d9543bdc..6102b620e5 100644 --- a/arch/risc-v/include/csr.h +++ b/arch/risc-v/include/csr.h @@ -304,6 +304,16 @@ #define CSR_DSCRATCH0 0x7b2 /* Debug Scratch 0 */ #define CSR_DSCRATCH1 0x7b3 /* Debug Scratch 1 */ +/* Vector CSRs */ + +#define CSR_VSTART 0x008 /* Vector Start Position */ +#define CSR_VXSAT 0x009 /* Fixed-Point Saturate Flag */ +#define CSR_VXRM 0x00a /* Fixed-Point Rounding Mode */ +#define CSR_VCSR 0x00f /* Vector Control and Status */ +#define CSR_VL 0xc20 /* Vector Length */ +#define CSR_VTYPE 0xc21 /* Vector Data Type */ +#define CSR_VLENB 0xc22 /* Vector Length in Bytes (VLEN/8) */ + /* In mstatus register */ #define MSTATUS_UIE (0x1 << 0) /* User Interrupt Enable */