Add support for teensy-3.0
This commit is contained in:
Gregory Nutt
parent
96137f25a9
commit
93e0980623
@ -910,7 +910,7 @@ config ARCH_BOARD_TEENSY_20
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config ARCH_BOARD_TEENSY_3X
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bool "PJRC Teensy++ 3.1 board"
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depends on ARCH_CHIP_MK20DX256VLH7
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depends on ARCH_CHIP_MK20DX256VLH7 || ARCH_CHIP_MK20DX128VLH5
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select ARCH_HAVE_LEDS
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---help---
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This is the port of NuttX to the PJRC Teensy++ 2.0 board. This board is
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@ -929,7 +929,7 @@ config ARCH_BOARD_TEENSY_3X
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This board configuration can also be used with the older Teensy-3.0. The
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Teensy-3.0 has the same schematic (although some pins are not used on the
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Teensy-3.0). the primary difference is that the Teensy 3.0 has a
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MK30DX128VLH5 with slightly less capability.
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MK20DX128VLH5 with slightly less capability.
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config ARCH_BOARD_TEENSY_LC
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bool "Teensy LC"
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@ -20,5 +20,4 @@ config SAM4S_XPLAINED_PRO_CPULOAD_TIMER_DEVPATH
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default "/dev/tc0"
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depends on TIMER && SCHED_CPULOAD && SCHED_CPULOAD_EXTCLK
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endif
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@ -2,3 +2,11 @@
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# For a description of the syntax of this configuration file,
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# see misc/tools/kconfig-language.txt.
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#
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if ARCH_BOARD_TEENSY_3X
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config TEENSY_3X_OVERCLOCK
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bool "Overclock"
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default n
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endif
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@ -13,17 +13,17 @@ README
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This board configuration can also be used with the older Teensy-3.0. The
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Teensy-3.0 has the same schematic (although some pins are not used on the
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Teensy-3.0). The primary difference is that the Teensy 3.0 has a
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MK30DX128VLH5 with slightly less capability. There are many difference
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between the MK30DX256VLH7 and the MK30DX128VLH5 but the basic differences
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MK20DX128VLH5 with slightly less capability. There are many difference
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between the MK30DX256VLH7 and the MK20DX128VLH5 but the basic differences
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that effect how you configure NuttX are:
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--------------- -------------- -------------- ---------------------------
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Feature Teensy 3.0 Teensy 3.1 CONFIGURATION
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--------------- -------------- -------------- ---------------------------
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Processor
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Core MK20DX128VLH5 MK20DX256VLH7 CONFIG_ARCH_CHIP_xyz
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Core MK20DX128VLH5 MK20DX256VLH7 CONFIG_ARCH_CHIP_MK20DX128VLH5
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Rated Speed 48 MHz 72 MHz Settings in include/board.h
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Overclockable 96 MHz 96 MHz Settings in include/board.h
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Overclockable 96 MHz 96 MHz CONFIG_TEENSY_3X_OVERCLOCK
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Flash Memory 128 KB 256 KB See scripts/flash.ld
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SRAM 16 KB 64 KB See scripts/flash.ld and
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set CONFIG_RAM_SIZE=???
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@ -61,75 +61,73 @@
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* produce a 2MHz reference clock to the PLL. The rated speed is 72MHz, but can
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* be overclocked at 96MHz
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*
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* 48MHz (rated 50MHz)
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*
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* PLL Input frequency: PLLIN = REFCLK/PRDIV = 16MHz/1 = 16MHz
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* PLL Output frequency: PLLOUT = PLLIN*VDIV = 8Mhz*3 = 72MHz
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* MCG Frequency: PLLOUT = 48MHz
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*
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* 72MHz
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*
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* PLL Input frequency: PLLIN = REFCLK/PRDIV = 16MHz/2 = 8MHz
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* PLL Output frequency: PLLOUT = PLLIN*VDIV = 8Mhz*9 = 72MHz
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* MCG Frequency: PLLOUT = 96MHz
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* MCG Frequency: PLLOUT = 72MHz
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*
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* 96MHz
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* 96MHz (Overclocked)
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* PLL Input frequency: PLLIN = REFCLK/PRDIV = 16MHz/1 = 16MHz
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* PLL Output frequency: PLLOUT = PLLIN*VDIV = 16Mhz*6 = 96MHz
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* MCG Frequency: PLLOUT = 96MHz
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*/
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#define BOARD_PRDIV 2 /* PLL External Reference Divider */
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#define BOARD_VDIV 24 /* PLL VCO Divider (frequency multiplier) */
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#if defiend(CONFIG_TEENSY_3X_OVERCLOCK)
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/* PLL Configuration */
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# define BOARD_PRDIV 1 /* PLL External Reference Divider */
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# define BOARD_VDIV 6 /* PLL VCO Divider (frequency multiplier) */
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/* SIM CLKDIV1 dividers */
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# define BOARD_OUTDIV1 1 /* Core = MCG, 96MHz */
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# define BOARD_OUTDIV2 2 /* Bus = MCG/2, 48MHz */
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# define BOARD_OUTDIV3 2 /* FlexBus = MCG/2, 48MHz */
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# define BOARD_OUTDIV4 4 /* Flash clock = MCG/4, 24MHz */
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#elif defined(CONFIG_ARCH_CHIP_MK20DX256VLH7)
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/* PLL Configuration */
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# define BOARD_PRDIV 2 /* PLL External Reference Divider */
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# define BOARD_VDIV 9 /* PLL VCO Divider (frequency multiplier) */
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/* SIM CLKDIV1 dividers */
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# define BOARD_OUTDIV1 1 /* Core = MCG, 72MHz */
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# define BOARD_OUTDIV2 2 /* Bus = MCG/2, 36MHz */
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# define BOARD_OUTDIV3 2 /* FlexBus = MCG/2, 36MHz */
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# define BOARD_OUTDIV4 3 /* Flash clock = MCG/3, 72MHz */
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#elif defined(CONFIG_ARCH_CHIP_MK20DX128VLH5)
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/* PLL Configuration */
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# define BOARD_PRDIV 1 /* PLL External Reference Divider */
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# define BOARD_VDIV 3 /* PLL VCO Divider (frequency multiplier) */
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/* SIM CLKDIV1 dividers */
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# define BOARD_OUTDIV1 1 /* Core = MCG, 48MHz */
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# define BOARD_OUTDIV2 1 /* Bus = MCG/1, 48MHz */
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# define BOARD_OUTDIV3 1 /* FlexBus = MCG/1, 48MHz */
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# define BOARD_OUTDIV4 2 /* Flash clock = MCG/2, 24MHz */
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#endif
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#define BOARD_PLLIN_FREQ (BOARD_EXTAL_FREQ / BOARD_PRDIV)
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#define BOARD_PLLOUT_FREQ (BOARD_PLLIN_FREQ * BOARD_VDIV)
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#define BOARD_MCG_FREQ BOARD_PLLOUT_FREQ
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/* SIM CLKDIV1 dividers */
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#define BOARD_OUTDIV1 1 /* Core = MCG, 96MHz */
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#define BOARD_OUTDIV2 2 /* Bus = MCG/2, 48MHz */
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#define BOARD_OUTDIV3 2 /* FlexBus = MCG/2, 48MHz */
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#define BOARD_OUTDIV4 4 /* Flash clock = MCG/4, 24MHz */
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#define BOARD_CORECLK_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV1)
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#define BOARD_BUS_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV2)
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#define BOARD_FLEXBUS_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV3)
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#define BOARD_FLASHCLK_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV4)
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/* SDHC clocking ********************************************************************/
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/* SDCLK configurations corresponding to various modes of operation. Formula is:
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*
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* SDCLK frequency = (base clock) / (prescaler * divisor)
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*
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* The SDHC module is always configure configured so that the core clock is the base
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* clock.
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*/
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/* Identification mode: 400KHz = 96MHz / ( 16 * 15) */
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#define BOARD_SDHC_IDMODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV16
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#define BOARD_SDHC_IDMODE_DIVISOR SDHC_SYSCTL_DVS_DIV(15)
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/* MMC normal mode: 16MHz = 96MHz / (2 * 3) */
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#define BOARD_SDHC_MMCMODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2
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#define BOARD_SDHC_MMCMODE_DIVISOR SDHC_SYSCTL_DVS_DIV(3)
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/* SD normal mode (1-bit): 16MHz = 96MHz / (2 * 3) */
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#define BOARD_SDHC_SD1MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2
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#define BOARD_SDHC_SD1MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(3)
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/* SD normal mode (4-bit): 24MHz = 96MHz / (2 * 2) (with DMA)
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* SD normal mode (4-bit): 16MHz = 96MHz / (2 * 3) (no DMA)
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*/
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#ifdef CONFIG_SDIO_DMA
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# define BOARD_SDHC_SD4MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2
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# define BOARD_SDHC_SD4MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(2)
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#else
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//# define BOARD_SDHC_SD4MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2
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//# define BOARD_SDHC_SD4MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(3)
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# define BOARD_SDHC_SD4MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV16
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# define BOARD_SDHC_SD4MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(15)
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#endif
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#define BOARD_CORECLK_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV1)
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#define BOARD_BUS_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV2)
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#define BOARD_FLEXBUS_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV3)
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#define BOARD_FLASHCLK_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV4)
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/* LED definitions ******************************************************************/
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/* A single LED is available driven by PTC5. The LED is grounded so bringing PTC5
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@ -135,6 +135,14 @@ CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y
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#
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# Kinetis Configuration Options
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#
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# CONFIG_ARCH_CHIP_MK20DN32VLH5 is not set
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# CONFIG_ARCH_CHIP_MK20DX32VLH5 is not set
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# CONFIG_ARCH_CHIP_MK20DN64VLH5 is not set
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# CONFIG_ARCH_CHIP_MK20DX64VLH5 is not set
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# CONFIG_ARCH_CHIP_MK20DN128VLH5 is not set
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# CONFIG_ARCH_CHIP_MK20DX128VLH5 is not set
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# CONFIG_ARCH_CHIP_MK20DX64VLH7 is not set
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# CONFIG_ARCH_CHIP_MK20DX128VLH7 is not set
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CONFIG_ARCH_CHIP_MK20DX256VLH7=y
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# CONFIG_ARCH_CHIP_MK40N512VLQ100 is not set
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# CONFIG_ARCH_CHIP_MK40N512VMD100 is not set
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@ -278,6 +286,7 @@ CONFIG_NSH_MMCSDMINOR=0
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#
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# Board-Specific Options
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#
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# CONFIG_TEENSY_3X_OVERCLOCK is not set
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# CONFIG_LIB_BOARDCTL is not set
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#
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@ -24,6 +24,12 @@ fs/unionfs/README.txt
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The Union File System is enabled by selecting the CONFIG_FS_UNIONFS option
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in the NuttX configuration file.
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Disclaimer: This Union File System was certainly inspired by UnionFS
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(http://en.wikipedia.org/wiki/UnionFS) and the similarity in naming is
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unavoidable. However, other than that, the NuttX Union File System
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has no relationship with the UnioinFS project in specification, usage,
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design, or implementation.
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Uses of the Union File System
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------------------------------
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The original motivation for this file was for the use of the built-in
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