net:Add support for multi PHY
Support runtime phy selection based on a list
supplied by board.h
For Example:
#define BOARD_ETH0_PHY_LIST \
{ \
"LAN8742A", \
MII_PHYID1_LAN8742A, \
MII_PHYID2_LAN8742A, \
MII_LAN8740_SCSR, \
0, \
0xffff, \
MII_LAN8720_SPSCR_10MBPS, \
MII_LAN8720_SPSCR_100MBPS, \
MII_LAN8720_SPSCR_DUPLEX, \
22, \
}, \
{ \
"TJA1103", \
MII_PHYID1_TJA1103, \
MII_PHYID2_TJA1103, \
0xffff, \
18, \
0xffff, \
0, \
MII_LAN8720_SPSCR_100MBPS, \
MII_LAN8720_SPSCR_DUPLEX, \
45, \
}, \
This commit is contained in:
David Sidrane
Xiang Xiao
parent
e9a146bbfc
commit
93f37ab1da
@ -549,6 +549,13 @@ choice
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config ETH0_PHY_NONE
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bool "No PHY support"
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config ETH0_PHY_MULTI
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bool "Multiple PHYs are supported"
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---help---
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The Board will provide a list of PHYs to probe for.
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The first one found on the bpard will be used.
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This setting is not supported by all Ethernet drivers.
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config ETH0_PHY_AM79C874
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bool "AMD Am79C874 PHY"
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@ -21,11 +21,14 @@
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#ifndef __INCLUDE_NUTTX_NET_MII_H
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#define __INCLUDE_NUTTX_NET_MII_H
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#ifndef __ASSEMBLY__
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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/****************************************************************************
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* Pre-processor Definitions
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@ -62,12 +65,14 @@
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/* AR8031: */
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#define MII_AR8031_NAME "AR8031"
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#define MII_AR8031_PSSR 0x11 /* Phy-Specific Status Register */
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/* National Semiconductor DP83840: 0x07-0x11, 0x14, 0x1a, 0x1d-0x1f
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* reserved
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*/
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#define MII_DP83840_NAME "DP83840"
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#define MII_DP83840_COUNTER 0x12 /* Disconnect counter */
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#define MII_DP83840_FCSCOUNTER 0x13 /* False carrier sense counter */
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#define MII_DP83840_NWAYTEST 0x14 /* N-way auto-neg test reg */
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@ -80,6 +85,7 @@
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/* Am79c874: 0x08-0x0f, 0x14, 0x16, 0x19-0x1f reserved */
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#define MII_AM79C874_NAME "AM79C874"
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#define MII_AM79C874_NPADVERTISE 0x07 /* Auto-negotiation next page advertisement */
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#define MII_AM79C874_MISCFEATURES 0x10 /* Miscellaneous features reg */
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#define MII_AM79C874_INTCS 0x11 /* Interrupt control/status */
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@ -91,6 +97,7 @@
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/* Luminary LM3S6918 built-in PHY: 0x07-0x0f, 0x14-0x16, 0x19-0x1f reserved */
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#define MII_LM3S6918_NAME "LM3S6918"
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#define MII_LM_VSPECIFIC 0x10 /* Vendor-Specific */
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#define MII_LM_INTCS 0x11 /* Interrupt control/status */
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#define MII_LM_DIAGNOSTIC 0x12 /* Diagnostic */
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@ -100,12 +107,14 @@
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/* Micrel KS8721: 0x15, 0x1b, and 0x1f */
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#define MII_KS8721_NAME "KS8721"
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#define MII_KS8721_RXERCOUNTER 0x15 /* RXER counter */
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#define MII_KS8721_INTCS 0x1b /* Interrupt control/status register */
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#define MII_KS8721_10BTCR 0x1f /* 10BASE-TX PHY control register */
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/* Micrel KSZ8041: 0x15, 0x1b, 0x1e-0x1f */
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#define MII_KSZ8041_NAME "KSZ8041"
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#define MII_KSZ8041_RXERR 0x15 /* RXERR Counter */
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#define MII_KSZ8041_INT 0x1b /* Interrupt Control/Status */
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#define MII_KSZ8041_PHYCTRL1 0x1e /* PHY Control 1 */
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@ -113,6 +122,7 @@
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/* Micrel KSZ8051: 0x11, 0x15-0x18, 0x1b, 0x1d-0x1f */
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#define MII_KSZ8051_NAME "KSZ8051"
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#define MII_KSZ8051_AFEC1 0x11 /* AFE Control 1 */
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#define MII_KSZ8051_RXERR 0x15 /* RXERR Counter */
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#define MII_KSZ8051_OMSO 0x16 /* Operation Mode Strap Override */
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@ -124,6 +134,8 @@
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#define MII_KSZ8051_PHYCTRL2 0x1f /* PHY Control 2 */
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/* Micrel KSZ8061: 0x10-0x18, 0x1b, 0x1c-0x1f */
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#define MII_KSZ8061_NAME "KSZ8061"
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#define MII_KSZ8061_DIG_CTRL 0x10 /* Digital Control */
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#define MII_KSZ8061_AFE_CTRL_0 0x11 /* AFE Control 0 */
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#define MII_KSZ8061_AFE_CTRL_1 0x12 /* AFE Control 1 */
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@ -141,6 +153,7 @@
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/* Micrel KSZ8081: 0x10-0x11, 0x15-0x18, 0x1b, 0x1d-0x1f */
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#define MII_KSZ8081_NAME "KSZ8081"
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#define MII_KSZ8081_DRCTRL 0x10 /* Digital Reserve Control */
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#define MII_KSZ8081_AFEC1 0x11 /* AFE Control 1 */
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#define MII_KSZ8081_RXERR 0x15 /* RXERR Counter */
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@ -156,6 +169,7 @@
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* 0x8-0x15, 0x13, 0x1c reserved
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*/
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#define MII_DP83848C_NAME "DP83848C"
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#define MII_DP83848C_STS 0x10 /* RO PHY Status Register */
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#define MII_DP83848C_MICR 0x11 /* RW MII Interrupt Control Register */
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#define MII_DP83848C_MISR 0x12 /* RO MII Interrupt Status Register */
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@ -171,6 +185,7 @@
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/* Texas Instruments DP83825I PHY Extended Registers. */
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#define MII_DP83825I_NAME "DP83825I"
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#define MII_DP83825I_PHYSTS 0x10 /* RO PHY Status Register */
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#define MII_DP83825I_PHYSCR 0x11 /* RW PHY Specific Control Register */
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#define MII_DP83825I_MISR1 0x12 /* RO MII Interrupt Status Register 1 */
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@ -189,6 +204,7 @@
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/* SMSC LAN8720 PHY Extended Registers */
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#define MII_LAN8720_NAME "LAN8720"
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#define MII_LAN8720_REV 0x10 /* Silicon Revision Register */
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#define MII_LAN8720_MCSR 0x11 /* Mode Control/Status Register */
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#define MII_LAN8720_MODES 0x12 /* Special modes */
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@ -201,6 +217,8 @@
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/* SMSC LAN8740/LAN8742A PHY Extended Registers */
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#define MII_LAN8740_NAME "LAN8740"
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#define MII_LAN8742A_NAME "LAN8742A"
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#define MII_LAN8740_CONFIG 0x10 /* EDPD NDL/Crossover Timer/EEE Configuration */
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#define MII_LAN8740_MCSR 0x11 /* Mode Control/Status Register */
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#define MII_LAN8740_MODES 0x12 /* Special modes */
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@ -215,6 +233,7 @@
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/* Motorcomm YT8512C/YT8512H Extended Registers */
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#define MII_YT8512_NAME "YT8512"
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#define MII_YT8512_PHYSFC 0x10 /* PHY Function conrtol Register */
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#define MII_YT8512_PHYSTS 0x11 /* PHY Status Register */
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#define MII_YT8512_IMR 0x12 /* Interrupt Mask Register */
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@ -728,12 +747,15 @@
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/* TJA110X MII ID1/2 register bits */
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#define MII_TJA1100_NAME "TJA1100"
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#define MII_PHYID1_TJA1100 0x0180 /* ID1 value for NXP TJA1100 */
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#define MII_PHYID2_TJA1100 0xdc40 /* ID2 value for NXP TJA1100 */
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#define MII_TJA1101_NAME "TJA1101"
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#define MII_PHYID1_TJA1101 0x0180 /* ID1 value for NXP TJA1101 */
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#define MII_PHYID2_TJA1101 0xdd00 /* ID2 value for NXP TJA1101 */
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#define MII_TJA1103_NAME "TJA1103"
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#define MII_PHYID1_TJA1103 0x01b /* ID1 value for NXP TJA1103 */
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#define MII_PHYID2_TJA1103 0xB013 /* ID2 value for NXP TJA1103 */
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@ -915,6 +937,22 @@
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* Type Definitions
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****************************************************************************/
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struct phy_desc_s
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{
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char name[16]; /* The name of the PHY */
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uint16_t id1; /* The MII_PHYID1 registers value */
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uint16_t id2; /* The MII_PHYID2 registers value */
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uint16_t status; /* The Phys status register or 0xffff */
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uint16_t address_lo; /* The lowest address to check for the PHY */
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uint16_t address_high; /* The highest address to check for the PHY or
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* 0xffff uses only the address_lo (one address)
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*/
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uint16_t mbps10; /* The bit mask for 10MBP if status is not 0xffff */
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uint16_t mbps100; /* The bit mask for 100MBP if status is not 0xffff */
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uint16_t duplex; /* The bit mask for DUPLEX if status is not 0xffff */
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uint16_t clause; /* The PHY clause supported. 22 or 45 */
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};
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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@ -932,4 +970,5 @@ extern "C"
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __INCLUDE_NUTTX_NET_MII_H */
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