diff --git a/arch/arm/src/lm/chip/lm4f_syscontrol.h b/arch/arm/src/lm/chip/lm4f_syscontrol.h
index 9696962c9a..e0701c11e6 100644
--- a/arch/arm/src/lm/chip/lm4f_syscontrol.h
+++ b/arch/arm/src/lm/chip/lm4f_syscontrol.h
@@ -416,8 +416,8 @@
 #define SYSCON_RCC_OSCSRC_SHIFT       4         /* Bits 5-4: Oscillator Source */
 #define SYSCON_RCC_OSCSRC_MASK        (0x03 << SYSCON_RCC_OSCSRC_SHIFT)
 #  define SYSCON_RCC_OSCSRC_MOSC      (0 << SYSCON_RCC_OSCSRC_SHIFT) /* Main oscillator */
-#  define SYSCON_RCC_OSCSRC_IOSC      (1 << SYSCON_RCC_OSCSRC_SHIFT) /* Precision internal oscillator (reset) */
-#  define SYSCON_RCC_OSCSRC_IOSC4     (2 << SYSCON_RCC_OSCSRC_SHIFT) /* Precision internal oscillator / 4 */
+#  define SYSCON_RCC_OSCSRC_PIOSC     (1 << SYSCON_RCC_OSCSRC_SHIFT) /* Precision internal oscillator (reset) */
+#  define SYSCON_RCC_OSCSRC_PIOSC4    (2 << SYSCON_RCC_OSCSRC_SHIFT) /* Precision internal oscillator / 4 */
 #  define SYSCON_RCC_OSCSRC_LFIOSC    (3 << SYSCON_RCC_OSCSRC_SHIFT) /* Low-frequency internal oscillator */
 #define SYSCON_RCC_XTAL_SHIFT         6         /* Bits 10-6: Crystal Value */
 #define SYSCON_RCC_XTAL_MASK          (31 << SYSCON_RCC_XTAL_SHIFT)
@@ -425,23 +425,23 @@
 #  define SYSCON_RCC_XTAL4096KHZ      (7 << SYSCON_RCC_XTAL_SHIFT)  /* 4.096 MHz (NO PLL) */
 #  define SYSCON_RCC_XTAL4915p2KHZ    (8 << SYSCON_RCC_XTAL_SHIFT)  /* 4.9152 MHz (NO PLL) */
 #  define SYSCON_RCC_XTAL5000KHZ      (9 << SYSCON_RCC_XTAL_SHIFT)  /* 5 MHz (USB) */
-#  define SYSCON_RCC_XTAL5120KHZ      (10 << SYSCON_RCC_XTAL_SHIFT)  /* 5.12 MHz */
-#  define SYSCON_RCC_XTAL6000KHZ      (11 << SYSCON_RCC_XTAL_SHIFT)  /* 6 MHz (USB) */
-#  define SYSCON_RCC_XTAL6144KHZ      (12 << SYSCON_RCC_XTAL_SHIFT)  /* 6.144 MHz */
-#  define SYSCON_RCC_XTAL7372p8KHZ    (13 << SYSCON_RCC_XTAL_SHIFT)  /* 7.3728 MHz */
-#  define SYSCON_RCC_XTAL8000KHZ      (14 << SYSCON_RCC_XTAL_SHIFT)  /* 8 MHz (USB) */
-#  define SYSCON_RCC_XTAL8192KHZ      (15 << SYSCON_RCC_XTAL_SHIFT)  /* 8.192 MHz */
-#  define SYSCON_RCC_XTAL10000KHZ     (16 << SYSCON_RCC_XTAL_SHIFT)  /* 10.0 MHz (USB) */
-#  define SYSCON_RCC_XTAL12000KHZ     (17 << SYSCON_RCC_XTAL_SHIFT)  /* 12.0 MHz (USB) */
-#  define SYSCON_RCC_XTAL12288KHZ     (18 << SYSCON_RCC_XTAL_SHIFT)  /* 12.288 MHz */
-#  define SYSCON_RCC_XTAL13560KHZ     (19 << SYSCON_RCC_XTAL_SHIFT)  /* 13.56 MHz */
-#  define SYSCON_RCC_XTAL14318p18KHZ  (20 << SYSCON_RCC_XTAL_SHIFT)  /* 14.31818 MHz */
-#  define SYSCON_RCC_XTAL16000KHZ     (21 << SYSCON_RCC_XTAL_SHIFT)  /* 16.0 MHz (USB) */
-#  define SYSCON_RCC_XTAL16384KHZ     (22 << SYSCON_RCC_XTAL_SHIFT)  /* 16.384 MHz */
-#  define SYSCON_RCC_XTAL18000KHZ     (23 << SYSCON_RCC_XTAL_SHIFT)  /* 18.0 MHz (USB) */
-#  define SYSCON_RCC_XTAL20000KHZ     (24 << SYSCON_RCC_XTAL_SHIFT)  /* 20.0 MHz (USB) */
-#  define SYSCON_RCC_XTAL24000KHZ     (25 << SYSCON_RCC_XTAL_SHIFT)  /* 24.0 MHz (USB) */
-#  define SYSCON_RCC_XTAL25000KHZ     (26 << SYSCON_RCC_XTAL_SHIFT)  /* 25.0 MHz (USB) */
+#  define SYSCON_RCC_XTAL5120KHZ      (10 << SYSCON_RCC_XTAL_SHIFT) /* 5.12 MHz */
+#  define SYSCON_RCC_XTAL6000KHZ      (11 << SYSCON_RCC_XTAL_SHIFT) /* 6 MHz (USB) */
+#  define SYSCON_RCC_XTAL6144KHZ      (12 << SYSCON_RCC_XTAL_SHIFT) /* 6.144 MHz */
+#  define SYSCON_RCC_XTAL7372p8KHZ    (13 << SYSCON_RCC_XTAL_SHIFT) /* 7.3728 MHz */
+#  define SYSCON_RCC_XTAL8000KHZ      (14 << SYSCON_RCC_XTAL_SHIFT) /* 8 MHz (USB) */
+#  define SYSCON_RCC_XTAL8192KHZ      (15 << SYSCON_RCC_XTAL_SHIFT) /* 8.192 MHz */
+#  define SYSCON_RCC_XTAL10000KHZ     (16 << SYSCON_RCC_XTAL_SHIFT) /* 10.0 MHz (USB) */
+#  define SYSCON_RCC_XTAL12000KHZ     (17 << SYSCON_RCC_XTAL_SHIFT) /* 12.0 MHz (USB) */
+#  define SYSCON_RCC_XTAL12288KHZ     (18 << SYSCON_RCC_XTAL_SHIFT) /* 12.288 MHz */
+#  define SYSCON_RCC_XTAL13560KHZ     (19 << SYSCON_RCC_XTAL_SHIFT) /* 13.56 MHz */
+#  define SYSCON_RCC_XTAL14318p18KHZ  (20 << SYSCON_RCC_XTAL_SHIFT) /* 14.31818 MHz */
+#  define SYSCON_RCC_XTAL16000KHZ     (21 << SYSCON_RCC_XTAL_SHIFT) /* 16.0 MHz (USB) */
+#  define SYSCON_RCC_XTAL16384KHZ     (22 << SYSCON_RCC_XTAL_SHIFT) /* 16.384 MHz */
+#  define SYSCON_RCC_XTAL18000KHZ     (23 << SYSCON_RCC_XTAL_SHIFT) /* 18.0 MHz (USB) */
+#  define SYSCON_RCC_XTAL20000KHZ     (24 << SYSCON_RCC_XTAL_SHIFT) /* 20.0 MHz (USB) */
+#  define SYSCON_RCC_XTAL24000KHZ     (25 << SYSCON_RCC_XTAL_SHIFT) /* 24.0 MHz (USB) */
+#  define SYSCON_RCC_XTAL25000KHZ     (26 << SYSCON_RCC_XTAL_SHIFT) /* 25.0 MHz (USB) */
 #define SYSCON_RCC_BYPASS             (1 << 11) /* Bit 11: PLL Bypass */
 #define SYSCON_RCC_PWRDN              (1 << 13) /* Bit 13: PLL Power Down */
 #define SYSCON_RCC_USESYSDIV          (1 << 22) /* Bit 22: Enable System Clock Divider */