diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index 29ffa1ff4a..6bcea16b1a 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -2421,7 +2421,7 @@ config STM32_USBHOST_PKTDUMP endmenu -menu "USB Device Configuration" +comment "USB Device Configuration" config STM32_USB_ITRMP bool "Re-map USB interrupt" diff --git a/arch/arm/src/stm32/chip/stm32f10xxx_rtc.h b/arch/arm/src/stm32/chip/stm32_rtc.h similarity index 96% rename from arch/arm/src/stm32/chip/stm32f10xxx_rtc.h rename to arch/arm/src/stm32/chip/stm32_rtc.h index a0778f4e6a..f96f704b10 100644 --- a/arch/arm/src/stm32/chip/stm32f10xxx_rtc.h +++ b/arch/arm/src/stm32/chip/stm32_rtc.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32/chip/stm32f10xxx_rtc.h + * arch/arm/src/stm32/chip/stm32_rtc.h * * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_RTC_H -#define __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_RTC_H +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_RTC_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32_RTC_H /************************************************************************************ * Pre-processor Definitions @@ -93,4 +93,4 @@ #define RTC_DIVH_RTC_DIV_SHIFT (0) /* Bits 3-0: RTC Clock Divider High */ #define RTC_DIVH_RTC_DIV_MASK (0x0f << RTC_DIVH_RTC_DIV_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_RTC_H */ +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_RTC_H */ diff --git a/arch/arm/src/stm32/chip/stm32f20xxx_rtc.h b/arch/arm/src/stm32/chip/stm32_rtcc.h similarity index 81% rename from arch/arm/src/stm32/chip/stm32f20xxx_rtc.h rename to arch/arm/src/stm32/chip/stm32_rtcc.h index b0d7ec9135..e51caf69e3 100644 --- a/arch/arm/src/stm32/chip/stm32f20xxx_rtc.h +++ b/arch/arm/src/stm32/chip/stm32_rtcc.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/stm32/chip/stm32f20xxx_rtc.h + * arch/arm/src/stm32/chip/stm32_rtcc.h.h * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2011-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F20XXX_RTC_H -#define __ARCH_ARM_SRC_STM32_CHIP_STM32F20XXX_RTC_H +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_RTCC_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32_RTCC_H /************************************************************************************ * Pre-processor Definitions @@ -48,7 +48,9 @@ #define STM32_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */ #define STM32_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */ #define STM32_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */ -#define STM32_RTC_CALIBR_OFFSET 0x0018 /* RTC calibration register */ +#ifndef CONFIG_STM32_STM32F30XX +# define STM32_RTC_CALIBR_OFFSET 0x0018 /* RTC calibration register */ +#endif #define STM32_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */ #define STM32_RTC_ALRMBR_OFFSET 0x0020 /* RTC alarm B register */ #define STM32_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */ @@ -79,10 +81,12 @@ #define STM32_RTC_BK13R_OFFSET 0x0084 /* RTC backup register 13 */ #define STM32_RTC_BK14R_OFFSET 0x0088 /* RTC backup register 14 */ #define STM32_RTC_BK15R_OFFSET 0x008c /* RTC backup register 15 */ -#define STM32_RTC_BK16R_OFFSET 0x0090 /* RTC backup register 16 */ -#define STM32_RTC_BK17R_OFFSET 0x0094 /* RTC backup register 17 */ -#define STM32_RTC_BK18R_OFFSET 0x0098 /* RTC backup register 18 */ -#define STM32_RTC_BK19R_OFFSET 0x009c /* RTC backup register 19 */ +#ifndef CONFIG_STM32_STM32F30XX +# define STM32_RTC_BK16R_OFFSET 0x0090 /* RTC backup register 16 */ +# define STM32_RTC_BK17R_OFFSET 0x0094 /* RTC backup register 17 */ +# define STM32_RTC_BK18R_OFFSET 0x0098 /* RTC backup register 18 */ +# define STM32_RTC_BK19R_OFFSET 0x009c /* RTC backup register 19 */ +#endif /* Register Addresses ***************************************************************/ @@ -92,7 +96,9 @@ #define STM32_RTC_ISR (STM32_RTC_BASE+STM32_RTC_ISR_OFFSET) #define STM32_RTC_PRER (STM32_RTC_BASE+STM32_RTC_PRER_OFFSET) #define STM32_RTC_WUTR (STM32_RTC_BASE+STM32_RTC_WUTR_OFFSET) -#define STM32_RTC_CALIBR (STM32_RTC_BASE+STM32_RTC_CALIBR_OFFSET) +#ifndef CONFIG_STM32_STM32F30XX +# define STM32_RTC_CALIBR (STM32_RTC_BASE+STM32_RTC_CALIBR_OFFSET) +#endif #define STM32_RTC_ALRMAR (STM32_RTC_BASE+STM32_RTC_ALRMAR_OFFSET) #define STM32_RTC_ALRMBR (STM32_RTC_BASE+STM32_RTC_ALRMBR_OFFSET) #define STM32_RTC_WPR (STM32_RTC_BASE+STM32_RTC_WPR_OFFSET) @@ -123,10 +129,12 @@ #define STM32_RTC_BK13R (STM32_RTC_BASE+STM32_RTC_BK13R_OFFSET) #define STM32_RTC_BK14R (STM32_RTC_BASE+STM32_RTC_BK14R_OFFSET) #define STM32_RTC_BK15R (STM32_RTC_BASE+STM32_RTC_BK15R_OFFSET) -#define STM32_RTC_BK16R (STM32_RTC_BASE+STM32_RTC_BK16R_OFFSET) -#define STM32_RTC_BK17R (STM32_RTC_BASE+STM32_RTC_BK17R_OFFSET) -#define STM32_RTC_BK18R (STM32_RTC_BASE+STM32_RTC_BK18R_OFFSET) -#define STM32_RTC_BK19R (STM32_RTC_BASE+STM32_RTC_BK19R_OFFSET) +#ifndef CONFIG_STM32_STM32F30XX +# define STM32_RTC_BK16R (STM32_RTC_BASE+STM32_RTC_BK16R_OFFSET) +# define STM32_RTC_BK17R (STM32_RTC_BASE+STM32_RTC_BK17R_OFFSET) +# define STM32_RTC_BK18R (STM32_RTC_BASE+STM32_RTC_BK18R_OFFSET) +# define STM32_RTC_BK19R (STM32_RTC_BASE+STM32_RTC_BK19R_OFFSET) +#endif /* Register Bitfield Definitions ****************************************************/ @@ -240,10 +248,12 @@ /* RTC calibration register */ -#define RTC_CALIBR_DCS (1 << 7) /* Bit 7 Digital calibration sign */ -#define RTC_CALIBR_DC_SHIFT (0) /* Bits 4:0 0-4: Digital calibration */ -#define RTC_CALIBR_DC_MASK (31 << RTC_CALIBR_DC_SHIFT) -# define RTC_CALIBR_DC(n) (((n) >> 2) << RTC_CALIBR_DC_SHIFT) /* n= 0, 4, 8, ... 126 */ +#ifndef CONFIG_STM32_STM32F30XX +# define RTC_CALIBR_DCS (1 << 7) /* Bit 7 Digital calibration sign */ +# define RTC_CALIBR_DC_SHIFT (0) /* Bits 4:0 0-4: Digital calibration */ +# define RTC_CALIBR_DC_MASK (31 << RTC_CALIBR_DC_SHIFT) +# define RTC_CALIBR_DC(n) (((n) >> 2) << RTC_CALIBR_DC_SHIFT) /* n= 0, 4, 8, ... 126 */ +#endif /* RTC alarm A/B registers */ @@ -318,15 +328,45 @@ /* RTC calibration register */ -#define RTC_CALR_ +#define RTC_CALR_CALM_SHIFT (0) /* Bits 0-8: Calibration minus */ +#define RTC_CALR_CALM_MASK (0x1ff << RTC_CALR_CALM_SHIFT) +#define RTC_CALR_CALW16 (1 << 13) /* Bit 13: Use a 16-second calibration cycle period */ +#define RTC_CALR_CALW8 (1 << 14) /* Bit 14: Use an 8-second calibration cycle period */ +#define RTC_CALR_CALP (1 << 15) /* Bit 15: Increase frequency of RTC by 488.5 ppm */ /* RTC tamper and alternate function configuration register */ -#define RTC_TAFCR_CALM_SHIFT (0) /* Bits 0-8: Calibration minus */ -#define RTC_TAFCR_CALM_MASK (0x1ff << RTC_TAFCR_CALM_SHIFT) -#define RTC_TAFCR_CALW16 (1 << 13) /* Bit 13: Use a 16-second calibration cycle period */ -#define RTC_TAFCR_CALW8 (1 << 14) /* Bit 14: Use an 8-second calibration cycle period */ -#define RTC_TAFCR_CALP (1 << 15) /* Bit 15: Increase frequency of RTC by 488.5 ppm */ +#define RTC_TAFCR_TAMP1E (1 << 0) /* Bit 0: RTC_TAMP1 input detection enable */ +#define RTC_TAFCR_TAMP1TRG (1 << 1) /* Bit 1: Active level for RTC_TAMP1 input */ +#define RTC_TAFCR_TAMPIE (1 << 2) /* Bit 2: Tamper interrupt enable */ +#define RTC_TAFCR_TAMP3E (1 << 5) /* Bit 5: RTC_TAMP3 detection enable */ +#define RTC_TAFCR_TAMP3TRG (1 << 6) /* Bit 6: Active level for RTC_TAMP3 input */ +#define RTC_TAFCR_TAMPTS (1 << 7) /* Bit 7: Activate timestamp on tamper detection event */ +#define RTC_TAFCR_TAMPFREQ_SHIFT (8) /* Bits 8-10: Tamper sampling frequency */ +#define RTC_TAFCR_TAMPFREQ_MASK (7 << RTC_TAFCR_TAMPFREQ_SHIFT) +# define RTC_TAFCR_TAMPFREQ_DIV32768 (0 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 32768 (1 Hz) */ +# define RTC_TAFCR_TAMPFREQ_DIV16384 (1 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 16384 (2 Hz) */ +# define RTC_TAFCR_TAMPFREQ_DIV8192 (2 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 8192 (4 Hz) */ +# define RTC_TAFCR_TAMPFREQ_DIV4096 (3 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 4096 (8 Hz) */ +# define RTC_TAFCR_TAMPFREQ_DIV2048 (4 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 2048 (16 Hz) */ +# define RTC_TAFCR_TAMPFREQ_DIV1024 (5 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 1024 (32 Hz) */ +# define RTC_TAFCR_TAMPFREQ_DIV512 (6 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 512 (64 Hz) */ +# define RTC_TAFCR_TAMPFREQ_DIV256 (7 << RTC_TAFCR_TAMPFREQ_SHIFT) /* RTCCLK / 256 (128 Hz) */ +#define RTC_TAFCR_TAMPFLT_SHIFT (11) /* Bits 11-12: RTC_TAMPx filter count */ +#define RTC_TAFCR_TAMPFLT_MASK (3 << RTC_TAFCR_TAMPFLT_SHIFT) +#define RTC_TAFCR_TAMPPRCH_SHIFT (13) /* Bits 13-14: RTC_TAMPx precharge duration */ +#define RTC_TAFCR_TAMPPRCH_MASK (3 << RTC_TAFCR_TAMPPRCH_SHIFT) +# define RTC_TAFCR_TAMPPRCH_1CYCLE (0 << RTC_TAFCR_TAMPPRCH_SHIFT) /* 1 RTCCLK cycle */ +# define RTC_TAFCR_TAMPPRCH_2CYCLES (1 << RTC_TAFCR_TAMPPRCH_SHIFT) /* 2 RTCCLK cycles */ +# define RTC_TAFCR_TAMPPRCH_4CYCLES (2 << RTC_TAFCR_TAMPPRCH_SHIFT) /* 4 RTCCLK cycles */ +# define RTC_TAFCR_TAMPPRCH_5CYCLES (3 << RTC_TAFCR_TAMPPRCH_SHIFT) /* 8 RTCCLK cycles */ +#define RTC_TAFCR_TAMPPUDIS (1 << 15) /* Bit 15: RTC_TAMPx pull-up disable */ +#define RTC_TAFCR_PC13VALUE (1 << 18) /* Bit 18: RTC_ALARM output type/PC13 value */ +#define RTC_TAFCR_PC13MODE (1 << 19) /* Bit 19: PC13 mode */ +#define RTC_TAFCR_PC14VALUE (1 << 20) /* Bit 20: PC14 value */ +#define RTC_TAFCR_PC14MODE (1 << 21) /* Bit 21: PC14 mode */ +#define RTC_TAFCR_PC15VALUE (1 << 22) /* Bit 22: PC15 value */ +#define RTC_TAFCR_PC15MODE (1 << 23) /* Bit 23: PC15 mode */ /* RTC alarm A/B sub second register */ @@ -335,4 +375,4 @@ #define RTC_ALRMSSR_MASKSS_SHIFT (0) /* Bits 24-27: Mask the most-significant bits starting at this bit */ #define RTC_ALRMSSR_MASKSS_MASK (0xffff << RTC_ALRMSSR_SS_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F20XXX_RTC_H */ +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_RTCC_H */ diff --git a/arch/arm/src/stm32/chip/stm32_spi.h b/arch/arm/src/stm32/chip/stm32_spi.h index 7731d03b0d..d611cb1446 100644 --- a/arch/arm/src/stm32/chip/stm32_spi.h +++ b/arch/arm/src/stm32/chip/stm32_spi.h @@ -65,7 +65,8 @@ #define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ #define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F40XX) # define STM32_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */ # define STM32_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */ #endif @@ -90,7 +91,8 @@ # define STM32_SPI2_CRCPR (STM32_SPI2_BASE+STM32_SPI_CRCPR_OFFSET) # define STM32_SPI2_RXCRCR (STM32_SPI2_BASE+STM32_SPI_RXCRCR_OFFSET) # define STM32_SPI2_TXCRCR (STM32_SPI2_BASE+STM32_SPI_TXCRCR_OFFSET) -# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F40XX) # define STM32_SPI2_I2SCFGR (STM32_SPI2_BASE+STM32_SPI_I2SCFGR_OFFSET) # define STM32_SPI2_I2SPR (STM32_SPI2_BASE+STM32_SPI_I2SPR_OFFSET) # endif @@ -104,7 +106,8 @@ # define STM32_SPI3_CRCPR (STM32_SPI3_BASE+STM32_SPI_CRCPR_OFFSET) # define STM32_SPI3_RXCRCR (STM32_SPI3_BASE+STM32_SPI_RXCRCR_OFFSET) # define STM32_SPI3_TXCRCR (STM32_SPI3_BASE+STM32_SPI_TXCRCR_OFFSET) -# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F40XX) # define STM32_SPI3_I2SCFGR (STM32_SPI3_BASE+STM32_SPI_I2SCFGR_OFFSET) # define STM32_SPI3_I2SPR (STM32_SPI3_BASE+STM32_SPI_I2SPR_OFFSET) # endif @@ -144,7 +147,8 @@ #define SPI_CR2_TXDMAEN (1 << 1) /* Bit 1: Tx Buffer DMA Enable */ #define SPI_CR2_SSOE (1 << 2) /* Bit 2: SS Output Enable */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F40XX) # define STM32_SPI3_FRF (1 << 4) /* Bit 4: Frame format */ #endif @@ -152,12 +156,34 @@ #define SPI_CR2_RXNEIE (1 << 6) /* Bit 6: RX buffer not empty interrupt enable */ #define SPI_CR2_TXEIE (1 << 7) /* Bit 7: Tx buffer empty interrupt enable */ +#ifdef CONFIG_STM32_STM32F30XX +#define SPI_CR1_DS_SHIFT (8) /* Bits 8-11: Data size */ +#define SPI_CR1_DS_MASK (15 << SPI_CR1_DS_SHIFT) +# define SPI_CR1_DS_4BIT (3 << SPI_CR1_DS_SHIFT) +# define SPI_CR1_DS_5BIT (4 << SPI_CR1_DS_SHIFT) +# define SPI_CR1_DS_6BIT (5 << SPI_CR1_DS_SHIFT) +# define SPI_CR1_DS_7BIT (6 << SPI_CR1_DS_SHIFT) +# define SPI_CR1_DS_8BIT (7 << SPI_CR1_DS_SHIFT) +# define SPI_CR1_DS_9BIT (8 << SPI_CR1_DS_SHIFT) +# define SPI_CR1_DS_10BIT (9 << SPI_CR1_DS_SHIFT) +# define SPI_CR1_DS_11BIT (10 << SPI_CR1_DS_SHIFT) +# define SPI_CR1_DS_12BIT (11 << SPI_CR1_DS_SHIFT) +# define SPI_CR1_DS_13BIT (12 << SPI_CR1_DS_SHIFT) +# define SPI_CR1_DS_14BIT (13 << SPI_CR1_DS_SHIFT) +# define SPI_CR1_DS_15BIT (14 << SPI_CR1_DS_SHIFT) +# define SPI_CR1_DS_16BIT (15 << SPI_CR1_DS_SHIFT) +#define SPI_CR2_FRXTH (1 << 12) /* Bit 12: FIFO reception threshold */ +#define SPI_CR2_LDMARX (1 << 13) /* Bit 13: Last DMA transfer for receptione */ +#define SPI_CR2_LDMATX (1 << 14) /* Bit 14: Last DMA transfer for transmission */ +#endif + /* SPI status register */ #define SPI_SR_RXNE (1 << 0) /* Bit 0: Receive buffer not empty */ #define SPI_SR_TXE (1 << 1) /* Bit 1: Transmit buffer empty */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F40XX) # define SPI_SR_CHSIDE (1 << 2) /* Bit 2: Channel side */ # define SPI_SR_UDR (1 << 3) /* Bit 3: Underrun flag */ #endif @@ -167,13 +193,30 @@ #define SPI_SR_OVR (1 << 6) /* Bit 6: Overrun flag */ #define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F40XX) # define SPI_SR_TIFRFE (1 << 8) /* Bit 8: TI frame format error */ #endif +#ifdef CONFIG_STM32_STM32F30XX +#define SPI_CR1_FRLVL_SHIFT (9) /* Bits 9-10: FIFO reception level */ +#define SPI_CR1_FRLVL_MASK (3 << SPI_CR1_FRLVL_SHIFT) +# define SPI_CR1_FRLVL_EMPTY (0 << SPI_CR1_FRLVL_SHIFT) /* FIFO empty */ +# define SPI_CR1_FRLVL_QUARTER (1 << SPI_CR1_FRLVL_SHIFT) /* 1/4 FIFO */ +# define SPI_CR1_FRLVL_HALF (2 << SPI_CR1_FRLVL_SHIFT) /* 1/2 FIFO */ +# define SPI_CR1_FRLVL_FULL (3 << SPI_CR1_FRLVL_SHIFT) /* FIFO full */ +#define SPI_CR1_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */ +#define SPI_CR1_FTLVL_MASK (3 << SPI_CR1_FTLVL_SHIFT) +# define SPI_CR1_FTLVL_EMPTY (0 << SPI_CR1_FTLVL_SHIFT) /* FIFO empty */ +# define SPI_CR1_FTLVL_QUARTER (1 << SPI_CR1_FTLVL_SHIFT) /* 1/4 FIFO */ +# define SPI_CR1_FTLVL_HALF (2 << SPI_CR1_FTLVL_SHIFT) /* 1/2 FIFO */ +# define SPI_CR1_FTLVL_FULL (3 << SPI_CR1_FTLVL_SHIFT) /* FIFO full */ +#endif + /* I2S configuration register */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F40XX) # define SPI_I2SCFGR_CHLEN (1 << 0) /* Bit 0: Channel length (number of bits per audio channel) */ # define SPI_I2SCFGR_DATLEN_SHIFT (1) /* Bit 1-2: Data length to be transferred */ # define SPI_I2SCFGR_DATLEN_MASK (3 << SPI_I2SCFGR_DATLEN_SHIFT) @@ -200,7 +243,8 @@ /* I2S prescaler register */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F40XX) # define SPI_I2SPR_I2SDIV_SHIFT (0) /* Bit 0-7: I2S Linear prescaler */ # define SPI_I2SPR_I2SDIV_MASK (0xff << SPI_I2SPR_I2SDIV_SHIFT) # define SPI_I2SPR_ODD (1 << 8) /* Bit 8: Odd factor for the prescaler */ diff --git a/arch/arm/src/stm32/chip/stm32f40xxx_rtc.h b/arch/arm/src/stm32/chip/stm32f40xxx_rtc.h deleted file mode 100644 index a656cfda04..0000000000 --- a/arch/arm/src/stm32/chip/stm32f40xxx_rtc.h +++ /dev/null @@ -1,338 +0,0 @@ -/************************************************************************************ - * arch/arm/src/stm32/chip/stm32f40xxx_rtc.h - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_RTC_H -#define __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_RTC_H - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register Offsets *****************************************************************/ - -#define STM32_RTC_TR_OFFSET 0x0000 /* RTC time register */ -#define STM32_RTC_DR_OFFSET 0x0004 /* RTC date register */ -#define STM32_RTC_CR_OFFSET 0x0008 /* RTC control register */ -#define STM32_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */ -#define STM32_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */ -#define STM32_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */ -#define STM32_RTC_CALIBR_OFFSET 0x0018 /* RTC calibration register */ -#define STM32_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */ -#define STM32_RTC_ALRMBR_OFFSET 0x0020 /* RTC alarm B register */ -#define STM32_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */ -#define STM32_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */ -#define STM32_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */ -#define STM32_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */ -#define STM32_RTC_TSDR_OFFSET 0x0030 /* RTC time stamp date register */ -#define STM32_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */ -#define STM32_RTC_CALR_OFFSET 0x003c /* RTC calibration register */ -#define STM32_RTC_TAFCR_OFFSET 0x0040 /* RTC tamper and alternate function configuration register */ -#define STM32_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */ -#define STM32_RTC_ALRMBSSR_OFFSET 0x0048 /* RTC alarm B sub second register */ - -#define STM32_RTC_BKR_OFFSET(n) (0x0050+((n)<<2)) -#define STM32_RTC_BK0R_OFFSET 0x0050 /* RTC backup register 0 */ -#define STM32_RTC_BK1R_OFFSET 0x0054 /* RTC backup register 1 */ -#define STM32_RTC_BK2R_OFFSET 0x0058 /* RTC backup register 2 */ -#define STM32_RTC_BK3R_OFFSET 0x005c /* RTC backup register 3 */ -#define STM32_RTC_BK4R_OFFSET 0x0060 /* RTC backup register 4 */ -#define STM32_RTC_BK5R_OFFSET 0x0064 /* RTC backup register 5 */ -#define STM32_RTC_BK6R_OFFSET 0x0068 /* RTC backup register 6 */ -#define STM32_RTC_BK7R_OFFSET 0x006c /* RTC backup register 7 */ -#define STM32_RTC_BK8R_OFFSET 0x0070 /* RTC backup register 8 */ -#define STM32_RTC_BK9R_OFFSET 0x0074 /* RTC backup register 9 */ -#define STM32_RTC_BK10R_OFFSET 0x0078 /* RTC backup register 10 */ -#define STM32_RTC_BK11R_OFFSET 0x007c /* RTC backup register 11 */ -#define STM32_RTC_BK12R_OFFSET 0x0080 /* RTC backup register 12 */ -#define STM32_RTC_BK13R_OFFSET 0x0084 /* RTC backup register 13 */ -#define STM32_RTC_BK14R_OFFSET 0x0088 /* RTC backup register 14 */ -#define STM32_RTC_BK15R_OFFSET 0x008c /* RTC backup register 15 */ -#define STM32_RTC_BK16R_OFFSET 0x0090 /* RTC backup register 16 */ -#define STM32_RTC_BK17R_OFFSET 0x0094 /* RTC backup register 17 */ -#define STM32_RTC_BK18R_OFFSET 0x0098 /* RTC backup register 18 */ -#define STM32_RTC_BK19R_OFFSET 0x009c /* RTC backup register 19 */ - -/* Register Addresses ***************************************************************/ - -#define STM32_RTC_TR (STM32_RTC_BASE+STM32_RTC_TR_OFFSET) -#define STM32_RTC_DR (STM32_RTC_BASE+STM32_RTC_DR_OFFSET) -#define STM32_RTC_CR (STM32_RTC_BASE+STM32_RTC_CR_OFFSET) -#define STM32_RTC_ISR (STM32_RTC_BASE+STM32_RTC_ISR_OFFSET) -#define STM32_RTC_PRER (STM32_RTC_BASE+STM32_RTC_PRER_OFFSET) -#define STM32_RTC_WUTR (STM32_RTC_BASE+STM32_RTC_WUTR_OFFSET) -#define STM32_RTC_CALIBR (STM32_RTC_BASE+STM32_RTC_CALIBR_OFFSET) -#define STM32_RTC_ALRMAR (STM32_RTC_BASE+STM32_RTC_ALRMAR_OFFSET) -#define STM32_RTC_ALRMBR (STM32_RTC_BASE+STM32_RTC_ALRMBR_OFFSET) -#define STM32_RTC_WPR (STM32_RTC_BASE+STM32_RTC_WPR_OFFSET) -#define STM32_RTC_SSR (STM32_RTC_BASE+STM32_RTC_SSR_OFFSET) -#define STM32_RTC_SHIFTR (STM32_RTC_BASE+STM32_RTC_SHIFTR_OFFSET) -#define STM32_RTC_TSTR (STM32_RTC_BASE+STM32_RTC_TSTR_OFFSET) -#define STM32_RTC_TSDR (STM32_RTC_BASE+STM32_RTC_TSDR_OFFSET) -#define STM32_RTC_TSSSR (STM32_RTC_BASE+STM32_RTC_TSSSR_OFFSET) -#define STM32_RTC_CALR (STM32_RTC_BASE+STM32_RTC_CALR_OFFSET) -#define STM32_RTC_TAFCR (STM32_RTC_BASE+STM32_RTC_TAFCR_OFFSET) -#define STM32_RTC_ALRMASSR (STM32_RTC_BASE+STM32_RTC_ALRMASSR_OFFSET) -#define STM32_RTC_ALRMBSSR (STM32_RTC_BASE+STM32_RTC_ALRMBSSR_OFFSET) - -#define STM32_RTC_BKR(n) (STM32_RTC_BASE+STM32_RTC_BKR_OFFSET(n)) -#define STM32_RTC_BK0R (STM32_RTC_BASE+STM32_RTC_BK0R_OFFSET) -#define STM32_RTC_BK1R (STM32_RTC_BASE+STM32_RTC_BK1R_OFFSET) -#define STM32_RTC_BK2R (STM32_RTC_BASE+STM32_RTC_BK2R_OFFSET) -#define STM32_RTC_BK3R (STM32_RTC_BASE+STM32_RTC_BK3R_OFFSET) -#define STM32_RTC_BK4R (STM32_RTC_BASE+STM32_RTC_BK4R_OFFSET) -#define STM32_RTC_BK5R (STM32_RTC_BASE+STM32_RTC_BK5R_OFFSET) -#define STM32_RTC_BK6R (STM32_RTC_BASE+STM32_RTC_BK6R_OFFSET) -#define STM32_RTC_BK7R (STM32_RTC_BASE+STM32_RTC_BK7R_OFFSET) -#define STM32_RTC_BK8R (STM32_RTC_BASE+STM32_RTC_BK8R_OFFSET) -#define STM32_RTC_BK9R (STM32_RTC_BASE+STM32_RTC_BK9R_OFFSET) -#define STM32_RTC_BK10R (STM32_RTC_BASE+STM32_RTC_BK10R_OFFSET) -#define STM32_RTC_BK11R (STM32_RTC_BASE+STM32_RTC_BK11R_OFFSET) -#define STM32_RTC_BK12R (STM32_RTC_BASE+STM32_RTC_BK12R_OFFSET) -#define STM32_RTC_BK13R (STM32_RTC_BASE+STM32_RTC_BK13R_OFFSET) -#define STM32_RTC_BK14R (STM32_RTC_BASE+STM32_RTC_BK14R_OFFSET) -#define STM32_RTC_BK15R (STM32_RTC_BASE+STM32_RTC_BK15R_OFFSET) -#define STM32_RTC_BK16R (STM32_RTC_BASE+STM32_RTC_BK16R_OFFSET) -#define STM32_RTC_BK17R (STM32_RTC_BASE+STM32_RTC_BK17R_OFFSET) -#define STM32_RTC_BK18R (STM32_RTC_BASE+STM32_RTC_BK18R_OFFSET) -#define STM32_RTC_BK19R (STM32_RTC_BASE+STM32_RTC_BK19R_OFFSET) - -/* Register Bitfield Definitions ****************************************************/ - -/* RTC time register */ - -#define RTC_TR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format */ -#define RTC_TR_SU_MASK (15 << RTC_TR_SU_SHIFT) -#define RTC_TR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format */ -#define RTC_TR_ST_MASK (7 << RTC_TR_ST_SHIFT) -#define RTC_TR_MNU_SHIFT (8) /* Bit 8-11: Minute units in BCD format */ -#define RTC_TR_MNU_MASK (15 << RTC_TR_MNU_SHIFT) -#define RTC_TR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format */ -#define RTC_TR_MNT_MASK (7 << RTC_TR_MNT_SHIFT) -#define RTC_TR_HU_SHIFT (16) /* Bit 16-19: Hour units in BCD format */ -#define RTC_TR_HU_MASK (15 << RTC_TR_HU_SHIFT) -#define RTC_TR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format */ -#define RTC_TR_HT_MASK (3 << RTC_TR_HT_SHIFT) -#define RTC_TR_PM (1 << 22) /* Bit 22: AM/PM notation */ -#define RTC_TR_RESERVED_BITS (0xff808080) - -/* RTC date register */ - -#define RTC_DR_DU_SHIFT (0) /* Bits 0-3: Date units in BCD format */ -#define RTC_DR_DU_MASK (15 << RTC_DR_DU_SHIFT) -#define RTC_DR_DT_SHIFT (4) /* Bits 4-5: Date tens in BCD format */ -#define RTC_DR_DT_MASK (3 << RTC_DR_DT_SHIFT) -#define RTC_DR_MU_SHIFT (8) /* Bits 8-11: Month units in BCD format */ -#define RTC_DR_MU_MASK (15 << RTC_DR_MU_SHIFT) -#define RTC_DR_MT (1 << 12) /* Bit 12: Month tens in BCD format */ -#define RTC_DR_WDU_SHIFT (13) /* Bits 13-15: Week day units */ -#define RTC_DR_WDU_MASK (7 << RTC_DR_WDU_SHIFT) -# define RTC_DR_WDU_MONDAY (1 << RTC_DR_WDU_SHIFT) -# define RTC_DR_WDU_TUESDAY (2 << RTC_DR_WDU_SHIFT) -# define RTC_DR_WDU_WEDNESDAY (3 << RTC_DR_WDU_SHIFT) -# define RTC_DR_WDU_THURSDAY (4 << RTC_DR_WDU_SHIFT) -# define RTC_DR_WDU_FRIDAY (5 << RTC_DR_WDU_SHIFT) -# define RTC_DR_WDU_SATURDAY (6 << RTC_DR_WDU_SHIFT) -# define RTC_DR_WDU_SUNDAY (7 << RTC_DR_WDU_SHIFT) -#define RTC_DR_YU_SHIFT (16) /* Bits 16-19: Year units in BCD format */ -#define RTC_DR_YU_MASK (15 << RTC_DR_YU_SHIFT) -#define RTC_DR_YT_SHIFT (20) /* Bits 20-23: Year tens in BCD format */ -#define RTC_DR_YT_MASK (15 << RTC_DR_YT_SHIFT) -#define RTC_DR_RESERVED_BITS (0xff0000c0) - -/* RTC control register */ - -#define RTC_CR_WUCKSEL_SHIFT (0) /* Bits 0-2: Wakeup clock selection */ -#define RTC_CR_WUCKSEL_MASK (7 << RTC_CR_WUCKSEL_SHIFT) -# define RTC_CR_WUCKSEL_RTCDIV16 (0 << RTC_CR_WUCKSEL_SHIFT) /* 000: RTC/16 clock is selected */ -# define RTC_CR_WUCKSEL_RTCDIV8 (1 << RTC_CR_WUCKSEL_SHIFT) /* 001: RTC/8 clock is selected */ -# define RTC_CR_WUCKSEL_RTCDIV4 (2 << RTC_CR_WUCKSEL_SHIFT) /* 010: RTC/4 clock is selected */ -# define RTC_CR_WUCKSEL_RTCDIV2 (3 << RTC_CR_WUCKSEL_SHIFT) /* 011: RTC/2 clock is selected */ -# define RTC_CR_WUCKSEL_CKSPRE (4 << RTC_CR_WUCKSEL_SHIFT) /* 10x: ck_spre clock is selected */ -# define RTC_CR_WUCKSEL_CKSPREADD (6 << RTC_CR_WUCKSEL_SHIFT) /* 11x: ck_spr clock and 216 added WUT counter */ -#define RTC_CR_TSEDGE (1 << 3) /* Bit 3: Timestamp event active edge */ -#define RTC_CR_REFCKON (1 << 4) /* Bit 4: Reference clock detection enable (50 or 60 Hz) */ -#define RTC_CR_BYPSHAD (1 << 5) /* Bit 5: Bypass the shadow registers */ -#define RTC_CR_FMT (1 << 6) /* Bit 6: Hour format */ -#define RTC_CR_DCE (1 << 7) /* Bit 7: Coarse digital calibration enable */ -#define RTC_CR_ALRAE (1 << 8) /* Bit 8: Alarm A enable */ -#define RTC_CR_ALRBE (1 << 9) /* Bit 9: Alarm B enable */ -#define RTC_CR_WUTE (1 << 10) /* Bit 10: Wakeup timer enable */ -#define RTC_CR_TSE (1 << 11) /* Bit 11: Time stamp enable */ -#define RTC_CR_ALRAIE (1 << 12) /* Bit 12: Alarm A interrupt enable */ -#define RTC_CR_ALRBIE (1 << 13) /* Bit 13: Alarm B interrupt enable */ -#define RTC_CR_WUTIE (1 << 14) /* Bit 14: Wakeup timer interrupt enable */ -#define RTC_CR_TSIE (1 << 15) /* Bit 15: Timestamp interrupt enable */ -#define RTC_CR_ADD1H (1 << 16) /* Bit 16: Add 1 hour (summer time change) */ -#define RTC_CR_SUB1H (1 << 17) /* Bit 17: Subtract 1 hour (winter time change) */ -#define RTC_CR_BKP (1 << 18) /* Bit 18: Backup */ -#define RTC_CR_COSEL (1 << 19) /* Bit 19 : Calibration output selection */ -#define RTC_CR_POL (1 << 20) /* Bit 20: Output polarity */ -#define RTC_CR_OSEL_SHIFT (21) /* Bits 21-22: Output selection */ -#define RTC_CR_OSEL_MASK (3 << RTC_CR_OSEL_SHIFT) -# define RTC_CR_OSEL_DISABLED (0 << RTC_CR_OSEL_SHIFT) /* 00: Output disabled */ -# define RTC_CR_OSEL_ALRMA (1 << RTC_CR_OSEL_SHIFT) /* 01: Alarm A output enabled */ -# define RTC_CR_OSEL_ALRMB (2 << RTC_CR_OSEL_SHIFT) /* 10: Alarm B output enabled */ -# define RTC_CR_OSEL_WUT (3 << RTC_CR_OSEL_SHIFT) /* 11: Wakeup output enabled */ -#define RTC_CR_COE (1 << 23) /* Bit 23: Calibration output enable */ - -/* RTC initialization and status register */ - -#define RTC_ISR_ALRAWF (1 << 0) /* Bit 0: Alarm A write flag */ -#define RTC_ISR_ALRBWF (1 << 1) /* Bit 1: Alarm B write flag */ -#define RTC_ISR_WUTWF (1 << 2) /* Bit 2: Wakeup timer write flag */ -#define RTC_ISR_SHPF (1 << 3) /* Bit 3: Shift operation pending */ -#define RTC_ISR_INITS (1 << 4) /* Bit 4: Initialization status flag */ -#define RTC_ISR_RSF (1 << 5) /* Bit 5: Registers synchronization flag */ -#define RTC_ISR_INITF (1 << 6) /* Bit 6: Initialization flag */ -#define RTC_ISR_INIT (1 << 7) /* Bit 7: Initialization mode */ -#define RTC_ISR_ALRAF (1 << 8) /* Bit 8: Alarm A flag */ -#define RTC_ISR_ALRBF (1 << 9) /* Bit 9: Alarm B flag */ -#define RTC_ISR_WUTF (1 << 10) /* Bit 10: Wakeup timer flag */ -#define RTC_ISR_TSF (1 << 11) /* Bit 11: Timestamp flag */ -#define RTC_ISR_TSOVF (1 << 12) /* Bit 12: Timestamp overflow flag */ -#define RTC_ISR_TAMP1F (1 << 13) /* Bit 13: Tamper detection flag */ -#define RTC_ISR_TAMP2F (1 << 14) /* Bit 14: TAMPER2 detection flag */ -#define RTC_ISR_RECALPF (1 << 16) /* Bit 16: Recalibration pending Flag */ -#define RTC_ISR_ALLFLAGS (0x00017fff) - -/* RTC prescaler register */ - -#define RTC_PRER_PREDIV_S_SHIFT (0) /* Bits 0-14: Synchronous prescaler factor */ -#define RTC_PRER_PREDIV_S_MASK (0x7fff << RTC_PRER_PREDIV_S_SHIFT) -#define RTC_PRER_PREDIV_A_SHIFT (16) /* Bits 16-22: Asynchronous prescaler factor */ -#define RTC_PRER_PREDIV_A_MASK (0x7f << RTC_PRER_PREDIV_A_SHIFT) - -/* RTC wakeup timer register */ - -#define RTC_WUTR_MASK (0xffff) /* Bits 15:0 Wakeup auto-reload value bits */ - -/* RTC calibration register */ - -#define RTC_CALIBR_DCS (1 << 7) /* Bit 7 Digital calibration sign */ -#define RTC_CALIBR_DC_SHIFT (0) /* Bits 4:0 0-4: Digital calibration */ -#define RTC_CALIBR_DC_MASK (31 << RTC_CALIBR_DC_SHIFT) -# define RTC_CALIBR_DC(n) (((n) >> 2) << RTC_CALIBR_DC_SHIFT) /* n= 0, 4, 8, ... 126 */ - -/* RTC alarm A/B registers */ - -#define RTC_ALRMR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format. */ -#define RTC_ALRMR_SU_MASK (15 << RTC_ALRMR_SU_SHIFT) -#define RTC_ALRMR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format. */ -#define RTC_ALRMR_ST_MASK (7 << RTC_ALRMR_ST_SHIFT) -#define RTC_ALRMR_MSK1 (1 << 7) /* Bit 7 : Alarm A seconds mask */ -#define RTC_ALRMR_MNU_SHIFT (8) /* Bits 8-11: Minute units in BCD format. */ -#define RTC_ALRMR_MNU_MASK (15 << RTC_ALRMR_MNU_SHIFT) -#define RTC_ALRMR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format. */ -#define RTC_ALRMR_MNT_MASK (7 << RTC_ALRMR_MNT_SHIFT) -#define RTC_ALRMR_MSK2 (1 << 15) /* Bit 15 : Alarm A minutes mask */ -#define RTC_ALRMR_HU_SHIFT (16) /* Bits 16-19: Hour units in BCD format. */ -#define RTC_ALRMR_HU_MASK (15 << RTC_ALRMR_HU_SHIFT) -#define RTC_ALRMR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format. */ -#define RTC_ALRMR_HT_MASK (3 << RTC_ALRMR_HT_SHIFT) -#define RTC_ALRMR_PM (1 << 22) /* Bit 22 : AM/PM notation */ -#define RTC_ALRMR_MSK3 (1 << 23) /* Bit 23 : Alarm A hours mask */ -#define RTC_ALRMR_DU_SHIFT (24) /* Bits 24-27: Date units or day in BCD format. */ -#define RTC_ALRMR_DU_MASK (15 << RTC_ALRMR_DU_SHIFT) -#define RTC_ALRMR_DT_SHIFT (28) /* Bits 28-29: Date tens in BCD format. */ -#define RTC_ALRMR_DT_MASK (3 << RTC_ALRMR_DT_SHIFT) -#define RTC_ALRMR_WDSEL (1 << 30) /* Bit 30: Week day selection */ -#define RTC_ALRMR_MSK4 (1 << 31) /* Bit 31: Alarm A date mask */ - -/* RTC write protection register */ - -#define RTC_WPR_MASK (0xff) /* Bits 0-7: Write protection key */ - -/* RTC sub second register */ - -#define RTC_SSR_MASK (0xffff) /* Bits 0-15: Sub second value */ - -/* RTC shift control register */ - -#define RTC_SHIFTR_SUBFS_SHIFT (0) /* Bits 0-14: Subtract a fraction of a second */ -#define RTC_SHIFTR_SUBFS_MASK (0x7ffff << RTC_SHIFTR_SUBFS_SHIFT) -#define RTC_SHIFTR_ADD1S (1 << 31) /* Bit 31: Add one second */ - -/* RTC time stamp time register */ - -#define RTC_TSTR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format. */ -#define RTC_TSTR_SU_MASK (15 << RTC_TSTR_SU_SHIFT) -#define RTC_TSTR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format. */ -#define RTC_TSTR_ST_MASK (7 << RTC_TSTR_ST_SHIFT) -#define RTC_TSTR_MNU_SHIFT (8) /* Bits 8-11: Minute units in BCD format. */ -#define RTC_TSTR_MNU_MASK (15 << RTC_TSTR_MNU_SHIFT) -#define RTC_TSTR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format. */ -#define RTC_TSTR_MNT_MASK (7 << RTC_TSTR_MNT_SHIFT) -#define RTC_TSTR_HU_SHIFT (16) /* Bits 16-19: Hour units in BCD format. */ -#define RTC_TSTR_HU_MASK (15 << RTC_TSTR_HU_SHIFT) -#define RTC_TSTR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format. */ -#define RTC_TSTR_HT_MASK (3 << RTC_TSTR_HT_SHIFT) -#define RTC_TSTR_PM (1 << 22) /* Bit 22: AM/PM notation */ - -/* RTC time stamp date register */ - -#define RTC_TSDR_DU_SHIFT (0) /* Bit 0-3: Date units in BCD format */ -#define RTC_TSDR_DU_MASK (15 << RTC_TSDR_DU_SHIFT) */ -#define RTC_TSDR_DT_SHIFT (4) /* Bits 4-5: Date tens in BCD format */ -#define RTC_TSDR_DT_MASK (3 << RTC_TSDR_DT_SHIFT) -#define RTC_TSDR_MU_SHIFT (8) /* Bits 8-11: Month units in BCD format */ -#define RTC_TSDR_MU_MASK (xx << RTC_TSDR_MU_SHIFT) -#define RTC_TSDR_MT (1 << 12) /* Bit 12: Month tens in BCD format */ -#define RTC_TSDR_WDU_SHIFT (13) /* Bits 13-15: Week day units */ -#define RTC_TSDR_WDU_MASK (7 << RTC_TSDR_WDU_SHIFT) - -/* RTC timestamp sub second register */ - -#define RTC_TSSSR_MASK (0xffff) /* Bits 0-15: Sub second value */ - -/* RTC calibration register */ - -#define RTC_CALR_ - -/* RTC tamper and alternate function configuration register */ - -#define RTC_TAFCR_CALM_SHIFT (0) /* Bits 0-8: Calibration minus */ -#define RTC_TAFCR_CALM_MASK (0x1ff << RTC_TAFCR_CALM_SHIFT) -#define RTC_TAFCR_CALW16 (1 << 13) /* Bit 13: Use a 16-second calibration cycle period */ -#define RTC_TAFCR_CALW8 (1 << 14) /* Bit 14: Use an 8-second calibration cycle period */ -#define RTC_TAFCR_CALP (1 << 15) /* Bit 15: Increase frequency of RTC by 488.5 ppm */ - -/* RTC alarm A/B sub second register */ - -#define RTC_ALRMSSR_SS_SHIFT (0) /* Bits 0-15: Sub second value */ -#define RTC_ALRMSSR_SS_MASK (0xffff << RTC_ALRMSSR_SS_SHIFT) -#define RTC_ALRMSSR_MASKSS_SHIFT (0) /* Bits 24-27: Mask the most-significant bits starting at this bit */ -#define RTC_ALRMSSR_MASKSS_MASK (0xffff << RTC_ALRMSSR_SS_SHIFT) - -#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_RTC_H */ diff --git a/arch/arm/src/stm32/stm32_rtc.c b/arch/arm/src/stm32/stm32_rtc.c index b79a74dcb5..5d4e0896e6 100644 --- a/arch/arm/src/stm32/stm32_rtc.c +++ b/arch/arm/src/stm32/stm32_rtc.c @@ -65,16 +65,22 @@ * for the selected STM32 family. The correct file cannot be selected by * the make system because it needs the intelligence that only exists in * chip.h that can associate an STM32 part number with an STM32 family. - * - * The STM32 F4 RTC differs dramatically the F1 RTC. The F1 RTC is a simple - * battery-backed counter; the F4 RTC is provides broken-out data/time in BCD - * format. + */ + +/* The STM32 F1 has a simple battery-backed counter for its RTC and has a separate + * block for the BKP registers. */ #if defined(CONFIG_STM32_STM32F10XX) -# include "stm32f10xxx_rtc.c" -#elif defined(CONFIG_STM32_STM32F20XX) -# include "stm32f20xxx_rtc.c" -#elif defined(CONFIG_STM32_STM32F40XX) -# include "stm32f40xxx_rtc.c" +# include "stm32_rtcounter.c" + +/* The other families use a more traditional Realtime Clock/Calendar (RTCC) with + * broken-out data/time in BCD format. The backup registers are integrated into + * the RTCC in these families. + */ + +#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) ||\ + defined(CONFIG_STM32_STM32F40XX) +# include "stm32_rtcc.c" #endif + diff --git a/arch/arm/src/stm32/stm32_rtc.h b/arch/arm/src/stm32/stm32_rtc.h index 11822f76c8..8e529cb619 100644 --- a/arch/arm/src/stm32/stm32_rtc.h +++ b/arch/arm/src/stm32/stm32_rtc.h @@ -2,7 +2,9 @@ * arch/arm/src/stm32/stm32_rtc.h * * Copyright (C) 2011 Uros Platise. All rights reserved. - * Author: Uros Platise + * Copyright (C) 2011-2013 Gregory Nutt. All rights reserved. + * Author: Uros Platise (Original for the F1) + * Gregory Nutt (On-going support and development) * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -43,13 +45,23 @@ #include #include "chip.h" + +/* The STM32 F1 has a simple battery-backed counter for its RTC and has a separate + * block for the BKP registers. + */ + #if defined(CONFIG_STM32_STM32F10XX) -# include "chip/stm32f10xxx_rtc.h" +# include "chip/stm32_rtc.h" # include "chip/stm32_bkp.h" -#elif defined(CONFIG_STM32_STM32F20XX) -# include "chip/stm32f20xxx_rtc.h" -#elif defined(CONFIG_STM32_STM32F40XX) -# include "chip/stm32f40xxx_rtc.h" + +/* The other families use a more traditional Realtime Clock/Calendar (RTCC) with + * broken-out data/time in BCD format. The backup registers are integrated into + * the RTCC in these families. + */ + +#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) ||\ + defined(CONFIG_STM32_STM32F40XX) +# include "chip/stm32_rtcc.h" #endif /************************************************************************************ diff --git a/arch/arm/src/stm32/stm32f40xxx_rtc.c b/arch/arm/src/stm32/stm32_rtcc.c similarity index 99% rename from arch/arm/src/stm32/stm32f40xxx_rtc.c rename to arch/arm/src/stm32/stm32_rtcc.c index c11748ae57..e9e71a007c 100644 --- a/arch/arm/src/stm32/stm32f40xxx_rtc.c +++ b/arch/arm/src/stm32/stm32_rtcc.c @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/stm32/stm32f40xxx_rtc.c + * arch/arm/src/stm32/stm32_rtcc.c * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -148,7 +148,9 @@ static void rtc_dumpregs(FAR const char *msg) rtclldbg(" ISR: %08x\n", getreg32(STM32_RTC_ISR)); rtclldbg(" PRER: %08x\n", getreg32(STM32_RTC_PRER)); rtclldbg(" WUTR: %08x\n", getreg32(STM32_RTC_WUTR)); +#ifndef CONFIG_STM32_STM32F30XX rtclldbg(" CALIBR: %08x\n", getreg32(STM32_RTC_CALIBR)); +#endif rtclldbg(" ALRMAR: %08x\n", getreg32(STM32_RTC_ALRMAR)); rtclldbg(" ALRMBR: %08x\n", getreg32(STM32_RTC_ALRMBR)); rtclldbg(" SHIFTR: %08x\n", getreg32(STM32_RTC_SHIFTR)); @@ -270,7 +272,7 @@ static int rtc_synchwait(void) rtc_wprunlock(); /* Clear Registers synchronization flag (RSF) */ - + regval = getreg32(STM32_RTC_ISR); regval &= ~RTC_ISR_RSF; putreg32(regval, STM32_RTC_ISR); @@ -315,7 +317,7 @@ static int rtc_enterinit(void) volatile uint32_t timeout; uint32_t regval; int ret; - + /* Check if the Initialization mode is already set */ regval = getreg32(STM32_RTC_ISR); @@ -326,9 +328,9 @@ static int rtc_enterinit(void) /* Set the Initialization mode */ putreg32(RTC_ISR_INIT, STM32_RTC_ISR); - + /* Wait until the RTC is in the INIT state (or a timeout occurs) */ - + ret = -ETIMEDOUT; for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) { @@ -341,7 +343,7 @@ static int rtc_enterinit(void) } } - return ret; + return ret; } /************************************************************************************ @@ -359,7 +361,7 @@ static int rtc_enterinit(void) ************************************************************************************/ static void rtc_exitinit(void) -{ +{ uint32_t regval; regval = getreg32(STM32_RTC_ISR); @@ -384,13 +386,13 @@ static void rtc_exitinit(void) static uint32_t rtc_bin2bcd(int value) { uint32_t msbcd = 0; - + while (value >= 10) { msbcd++; value -= 10; } - + return (msbcd << 4) | value; } @@ -631,7 +633,7 @@ int up_rtcinitialize(void) #endif g_rtc_enabled = true; - rtc_dumpregs("After Initialization"); + rtc_dumpregs("After Initialization"); return OK; } diff --git a/arch/arm/src/stm32/stm32f10xxx_rtc.c b/arch/arm/src/stm32/stm32_rtcounter.c similarity index 99% rename from arch/arm/src/stm32/stm32f10xxx_rtc.c rename to arch/arm/src/stm32/stm32_rtcounter.c index e1d52ac099..251398c80a 100644 --- a/arch/arm/src/stm32/stm32f10xxx_rtc.c +++ b/arch/arm/src/stm32/stm32_rtcounter.c @@ -1,12 +1,12 @@ /************************************************************************************ - * arch/arm/src/stm32/stm32f10xxx_rtc.c + * arch/arm/src/stm32/stm32_rtcounter.c * * Copyright (C) 2011 Uros Platise. All rights reserved. * Author: Uros Platise * * With extensions, modifications by: * - * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2011-2013 Gregory Nutt. All rights reserved. * Author: Gregroy Nutt * * Redistribution and use in source and binary forms, with or without diff --git a/arch/arm/src/stm32/stm32f20xxx_rtc.c b/arch/arm/src/stm32/stm32f20xxx_rtc.c deleted file mode 100644 index b98276498c..0000000000 --- a/arch/arm/src/stm32/stm32f20xxx_rtc.c +++ /dev/null @@ -1,842 +0,0 @@ -/************************************************************************************ - * arch/arm/src/stm32/stm32f20xxx_rtc.c - * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include - -#include "up_arch.h" - -#include "stm32_rtc.h" - -#ifdef CONFIG_RTC - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ -/* Configuration ********************************************************************/ -/* This RTC implementation supports only date/time RTC hardware */ - -#ifndef CONFIG_RTC_DATETIME -# error "CONFIG_RTC_DATETIME must be set to use this driver" -#endif - -#ifdef CONFIG_RTC_HIRES -# error "CONFIG_RTC_HIRES must NOT be set with this driver" -#endif - -#ifndef CONFIG_STM32_PWR -# error "CONFIG_STM32_PWR must selected to use this driver" -#endif - -#ifndef CONFIG_DEBUG -# undef CONFIG_DEBUG_RTC -#endif - -/* Constants ************************************************************************/ - -#define SYNCHRO_TIMEOUT (0x00020000) -#define INITMODE_TIMEOUT (0x00010000) -#define RTC_MAGIC (0xfacefeed) -#define RTC_PREDIV_S (0xff) -#define RTC_PREDIV_A (0x7f) - -/* Debug ****************************************************************************/ - -#ifdef CONFIG_DEBUG_RTC -# define rtcdbg dbg -# define rtcvdbg vdbg -# define rtclldbg lldbg -# define rtcllvdbg llvdbg -#else -# define rtcdbg(x...) -# define rtcvdbg(x...) -# define rtclldbg(x...) -# define rtcllvdbg(x...) -#endif - -/************************************************************************************ - * Private Types - ************************************************************************************/ - -/************************************************************************************ - * Private Data - ************************************************************************************/ - -/* Callback to use when the alarm expires */ - -#ifdef CONFIG_RTC_ALARM -static alarmcb_t g_alarmcb; -#endif - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/* g_rtc_enabled is set true after the RTC has successfully initialized */ - -volatile bool g_rtc_enabled = false; - -/************************************************************************************ - * Private Functions - ************************************************************************************/ -/************************************************************************************ - * Name: rtc_dumpregs - * - * Description: - * Disable RTC write protection - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ************************************************************************************/ - -#ifdef CONFIG_DEBUG_RTC -static void rtc_dumpregs(FAR const char *msg) -{ - rtclldbg("%s:\n", msg); - rtclldbg(" TR: %08x\n", getreg32(STM32_RTC_TR)); - rtclldbg(" DR: %08x\n", getreg32(STM32_RTC_DR)); - rtclldbg(" CR: %08x\n", getreg32(STM32_RTC_CR)); - rtclldbg(" ISR: %08x\n", getreg32(STM32_RTC_ISR)); - rtclldbg(" PRER: %08x\n", getreg32(STM32_RTC_PRER)); - rtclldbg(" WUTR: %08x\n", getreg32(STM32_RTC_WUTR)); - rtclldbg(" CALIBR: %08x\n", getreg32(STM32_RTC_CALIBR)); - rtclldbg(" ALRMAR: %08x\n", getreg32(STM32_RTC_ALRMAR)); - rtclldbg(" ALRMBR: %08x\n", getreg32(STM32_RTC_ALRMBR)); - rtclldbg(" SHIFTR: %08x\n", getreg32(STM32_RTC_SHIFTR)); - rtclldbg(" TSTR: %08x\n", getreg32(STM32_RTC_TSTR)); - rtclldbg(" TSDR: %08x\n", getreg32(STM32_RTC_TSDR)); - rtclldbg(" TSSSR: %08x\n", getreg32(STM32_RTC_TSSSR)); - rtclldbg(" CALR: %08x\n", getreg32(STM32_RTC_CALR)); - rtclldbg(" TAFCR: %08x\n", getreg32(STM32_RTC_TAFCR)); - rtclldbg("ALRMASSR: %08x\n", getreg32(STM32_RTC_ALRMASSR)); - rtclldbg("ALRMBSSR: %08x\n", getreg32(STM32_RTC_ALRMBSSR)); - rtclldbg(" BK0: %08x\n", getreg32(STM32_RTC_BK0R)); -} -#else -# define rtc_dumpregs(msg) -#endif - -/************************************************************************************ - * Name: rtc_dumptime - * - * Description: - * Disable RTC write protection - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ************************************************************************************/ - -#ifdef CONFIG_DEBUG_RTC -static void rtc_dumptime(FAR struct tm *tp, FAR const char *msg) -{ - rtclldbg("%s:\n", msg); - rtclldbg(" tm_sec: %08x\n", tp->tm_sec); - rtclldbg(" tm_min: %08x\n", tp->tm_min); - rtclldbg(" tm_hour: %08x\n", tp->tm_hour); - rtclldbg(" tm_mday: %08x\n", tp->tm_mday); - rtclldbg(" tm_mon: %08x\n", tp->tm_mon); - rtclldbg(" tm_year: %08x\n", tp->tm_year); -} -#else -# define rtc_dumptime(tp, msg) -#endif - -/************************************************************************************ - * Name: rtc_wprunlock - * - * Description: - * Disable RTC write protection - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ************************************************************************************/ - -static void rtc_wprunlock(void) -{ - /* The following steps are required to unlock the write protection on all the - * RTC registers (except for RTC_ISR[13:8], RTC_TAFCR, and RTC_BKPxR). - * - * 1. Write 0xCA into the RTC_WPR register. - * 2. Write 0x53 into the RTC_WPR register. - * - * Writing a wrong key reactivates the write protection. - */ - - putreg32(0xca, STM32_RTC_WPR); - putreg32(0x53, STM32_RTC_WPR); -} - -/************************************************************************************ - * Name: rtc_wprunlock - * - * Description: - * Enable RTC write protection - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ************************************************************************************/ - -static inline void rtc_wprlock(void) -{ - /* Writing any wrong key reactivates the write protection. */ - - putreg32(0xff, STM32_RTC_WPR); -} - -/************************************************************************************ - * Name: rtc_synchwait - * - * Description: - * Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are - * synchronized with RTC APB clock. - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ************************************************************************************/ - -static int rtc_synchwait(void) -{ - volatile uint32_t timeout; - uint32_t regval; - int ret; - - /* Disable the write protection for RTC registers */ - - rtc_wprunlock(); - - /* Clear Registers synchronization flag (RSF) */ - - regval = getreg32(STM32_RTC_ISR); - regval &= ~RTC_ISR_RSF; - putreg32(regval, STM32_RTC_ISR); - - /* Now wait the registers to become synchronised */ - - ret = -ETIMEDOUT; - for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) - { - regval = getreg32(STM32_RTC_ISR); - if ((regval & RTC_ISR_RSF) != 0) - { - /* Synchronized */ - - ret = OK; - break; - } - } - - /* Re-enable the write protection for RTC registers */ - - rtc_wprlock(); - return ret; -} - -/************************************************************************************ - * Name: rtc_enterinit - * - * Description: - * Enter RTC initialization mode. - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ************************************************************************************/ - -static int rtc_enterinit(void) -{ - volatile uint32_t timeout; - uint32_t regval; - int ret; - - /* Check if the Initialization mode is already set */ - - regval = getreg32(STM32_RTC_ISR); - - ret = OK; - if ((regval & RTC_ISR_INITF) == 0) - { - /* Set the Initialization mode */ - - putreg32(RTC_ISR_INIT, STM32_RTC_ISR); - - /* Wait until the RTC is in the INIT state (or a timeout occurs) */ - - ret = -ETIMEDOUT; - for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) - { - regval = getreg32(STM32_RTC_ISR); - if ((regval & RTC_ISR_INITF) != 0) - { - ret = OK; - break; - } - } - } - - return ret; -} - -/************************************************************************************ - * Name: rtc_exitinit - * - * Description: - * Exit RTC initialization mode. - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ************************************************************************************/ - -static void rtc_exitinit(void) -{ - uint32_t regval; - - regval = getreg32(STM32_RTC_ISR); - regval &= ~(RTC_ISR_INIT); - putreg32(regval, STM32_RTC_ISR); -} - -/************************************************************************************ - * Name: rtc_bin2bcd - * - * Description: - * Converts a 2 digit binary to BCD format - * - * Input Parameters: - * value - The byte to be converted. - * - * Returned Value: - * The value in BCD representation - * - ************************************************************************************/ - -static uint32_t rtc_bin2bcd(int value) -{ - uint32_t msbcd = 0; - - while (value >= 10) - { - msbcd++; - value -= 10; - } - - return (msbcd << 4) | value; -} - -/************************************************************************************ - * Name: rtc_bin2bcd - * - * Description: - * Convert from 2 digit BCD to binary. - * - * Input Parameters: - * value - The BCD value to be converted. - * - * Returned Value: - * The value in binary representation - * - ************************************************************************************/ - -static int rtc_bcd2bin(uint32_t value) -{ - uint32_t tens = (value >> 4) * 10; - return (int)(tens + (value & 0x0f)); -} - -/************************************************************************************ - * Name: rtc_setup - * - * Description: - * Performs first time configuration of the RTC. A special value written into - * back-up register 0 will prevent this function from being called on sub-sequent - * resets or power up. - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ************************************************************************************/ - -static int rtc_setup(void) -{ - uint32_t regval; - int ret; - - /* Enable the External Low-Speed (LSE) Oscillator setup the LSE as the RTC clock\ - * source, and enable the RTC. - */ - - stm32_rcc_enablelse(); - - /* Wait for the RTC Time and Date registers to be synchronized with RTC APB - * clock. - */ - - ret = rtc_synchwait(); - if (ret == OK) - { - /* Disable the write protection for RTC registers */ - - rtc_wprunlock(); - - /* Set Initialization mode */ - - ret = rtc_enterinit(); - if (ret == OK) - { - /* Set the 24 hour format by clearing the FMT bit in the RTC - * control register - */ - - regval = getreg32(STM32_RTC_CR); - regval &= ~RTC_CR_FMT; - putreg32(regval, STM32_RTC_CR); - - /* Configure RTC pre-scaler to the required, default values for - * use with the 32.768 KHz LSE clock: - */ - - putreg32(((uint32_t)0xff << RTC_PRER_PREDIV_S_SHIFT) | - ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), - STM32_RTC_PRER); - - /* Exit RTC initialization mode */ - - rtc_exitinit(); - } - - /* Re-enable the write protection for RTC registers */ - - rtc_wprlock(); - } - return ret; -} - -/************************************************************************************ - * Name: rtc_resume - * - * Description: - * Called when the RTC was already initialized on a previous power cycle. This - * just brings the RTC back into full operation. - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ************************************************************************************/ - -static int rtc_resume(void) -{ -#ifdef CONFIG_RTC_ALARM - uint32_t regval; -#endif - int ret; - - /* Wait for the RTC Time and Date registers to be syncrhonized with RTC APB - * clock. - */ - - ret = rtc_synchwait(); - - /* Clear the RTC alarm flags */ - -#ifdef CONFIG_RTC_ALARM - regval = getreg32(STM32_RTC_ISR); - regval &= ~(RTC_ISR_ALRAF|RTC_ISR_ALRBF); - putreg32(regval, STM32_RTC_ISR); - - /* Clear the EXTI Line 17 Pending bit (Connected internally to RTC Alarm) */ - - putreg32((1 << 17), STM32_EXTI_PR); -#endif - return ret; -} - -/************************************************************************************ - * Name: rtc_interrupt - * - * Description: - * RTC interrupt service routine - * - * Input Parameters: - * irq - The IRQ number that generated the interrupt - * context - Architecture specific register save information. - * - * Returned Value: - * Zero (OK) on success; A negated errno value on failure. - * - ************************************************************************************/ - -#if CONFIG_RTC_ALARM -static int rtc_interrupt(int irq, void *context) -{ -#warning "Missing logic" - return OK; -} -#endif - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/************************************************************************************ - * Name: up_rtcinitialize - * - * Description: - * Initialize the hardware RTC per the selected configuration. This function is - * called once during the OS initialization sequence - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ************************************************************************************/ - -int up_rtcinitialize(void) -{ - uint32_t regval; - int ret; - - rtc_dumpregs("On reset"); - - /* Clocking for the PWR block must be provided. However, this is done - * unconditionally in stm32f40xxx_rcc.c on power up. This done unconditionally - * because the PWR block is also needed to set the internal voltage regulator for - * maximum performance. - */ - - /* Enable access to the backup domain (RTC registers, RTC backup data registers - * and backup SRAM). - */ - - stm32_pwr_enablebkp(); - - /* Check if the one-time initialization of the RTC has already been performed. - * We can determine this by checking if the magic number has been writing to - * to back-up date register DR0. - */ - - regval = getreg32(STM32_RTC_BK0R); - if (regval != RTC_MAGIC) - { - /* Perform the one-time setup of the LSE clocking to the RTC */ - - ret = rtc_setup(); - - /* Remember that the RTC is initialized */ - - putreg32(RTC_MAGIC, STM32_RTC_BK0R); - } - else - { - /* RTC already set-up, just resume normal operation */ - - ret = rtc_resume(); - } - - /* Configure RTC interrupt to catch alarm interrupts. All RTC interrupts are - * connected to the EXTI controller. To enable the RTC Alarm interrupt, the - * following sequence is required: - * - * 1. Configure and enable the EXTI Line 17 in interrupt mode and select the - * rising edge sensitivity. - * 2. Configure and enable the RTC_Alarm IRQ channel in the NVIC. - * 3. Configure the RTC to generate RTC alarms (Alarm A or Alarm B). - */ - -#ifdef CONFIG_RTC_ALARM -# warning "Missing EXTI setup logic" - - /* Then attach the ALARM interrupt handler */ - - irq_attach(STM32_IRQ_RTC, rtc_interrupt); - up_enable_irq(STM32_IRQ_RTC); -#endif - - g_rtc_enabled = true; - rtc_dumpregs("After Initialzation"); - return OK; -} - -/************************************************************************************ - * Name: up_rtc_getdatetime - * - * Description: - * Get the current date and time from the date/time RTC. This interface - * is only supported by the date/time RTC hardware implementation. - * It is used to replace the system timer. It is only used by the RTOS during - * intialization to set up the system time when CONFIG_RTC and CONFIG_RTC_DATETIME - * are selected (and CONFIG_RTC_HIRES is not). - * - * NOTE: Some date/time RTC hardware is capability of sub-second accuracy. That - * sub-second accuracy is lost in this interface. However, since the system time - * is reinitialized on each power-up/reset, there will be no timing inaccuracy in - * the long run. - * - * Input Parameters: - * tp - The location to return the high resolution time value. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ************************************************************************************/ - -int up_rtc_getdatetime(FAR struct tm *tp) -{ - uint32_t dr; - uint32_t tr; - uint32_t tmp; - - /* Sample the data time registers. There is a race condition here... If we sample - * the time just before midnight on December 31, the date could be wrong because - * the day rolled over while were sampling. - */ - - do - { - dr = getreg32(STM32_RTC_DR); - tr = getreg32(STM32_RTC_TR); - tmp = getreg32(STM32_RTC_DR); - } - while (tmp != dr); - - rtc_dumpregs("Reading Time"); - - /* Convert the RTC time to fields in struct tm format. All of the STM32 - * All of the ranges of values correspond between struct tm and the time - * register. - */ - - tmp = (tr & (RTC_TR_SU_MASK|RTC_TR_ST_MASK)) >> RTC_TR_SU_SHIFT; - tp->tm_sec = rtc_bcd2bin(tmp); - - tmp = (tr & (RTC_TR_MNU_MASK|RTC_TR_MNT_MASK)) >> RTC_TR_MNU_SHIFT; - tp->tm_min = rtc_bcd2bin(tmp); - - tmp = (tr & (RTC_TR_HU_MASK|RTC_TR_HT_MASK)) >> RTC_TR_HU_SHIFT; - tp->tm_hour = rtc_bcd2bin(tmp); - - /* Now convert the RTC date to fields in struct tm format: - * Days: 1-31 match in both cases. - * Month: STM32 is 1-12, struct tm is 0-11. - * Years: STM32 is 00-99, struct tm is years since 1900. - * - * Issue: I am not sure what the STM32 years mean. Are these the - * years 2000-2099? I'll assume so. - */ - - tmp = (dr & (RTC_DR_DU_MASK|RTC_DR_DT_MASK)) >> RTC_DR_DU_SHIFT; - tp->tm_mday = rtc_bcd2bin(tmp); - - tmp = (dr & (RTC_DR_MU_MASK|RTC_DR_MT)) >> RTC_DR_MU_SHIFT; - tp->tm_mon = rtc_bcd2bin(tmp) - 1; - - tmp = (dr & (RTC_DR_YU_MASK|RTC_DR_YT_MASK)) >> RTC_DR_YU_SHIFT; - tp->tm_year = rtc_bcd2bin(tmp) + 100; - - rtc_dumptime(tp, "Returning"); - return OK; -} - -/************************************************************************************ - * Name: up_rtc_settime - * - * Description: - * Set the RTC to the provided time. All RTC implementations must be able to - * set their time based on a standard timespec. - * - * Input Parameters: - * tp - the time to use - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ************************************************************************************/ - -int up_rtc_settime(FAR const struct timespec *tp) -{ - FAR struct tm newtime; - uint32_t tr; - uint32_t dr; - int ret; - - /* Break out the time values (not that the time is set only to units of seconds) */ - - (void)gmtime_r(&tp->tv_sec, &newtime); - rtc_dumptime(&newtime, "Setting time"); - - /* Then write the broken out values to the RTC */ - - /* Convert the struct tm format to RTC time register fields. All of the STM32 - * All of the ranges of values correspond between struct tm and the time - * register. - */ - - tr = (rtc_bin2bcd(newtime.tm_sec) << RTC_TR_SU_SHIFT) | - (rtc_bin2bcd(newtime.tm_min) << RTC_TR_MNU_SHIFT) | - (rtc_bin2bcd(newtime.tm_hour) << RTC_TR_HU_SHIFT); - tr &= ~RTC_TR_RESERVED_BITS; - - /* Now convert the fields in struct tm format to the RTC date register fields: - * Days: 1-31 match in both cases. - * Month: STM32 is 1-12, struct tm is 0-11. - * Years: STM32 is 00-99, struct tm is years since 1900. - * - * Issue: I am not sure what the STM32 years mean. Are these the - * years 2000-2099? I'll assume so. - */ - - dr = (rtc_bin2bcd(newtime.tm_mday) << RTC_DR_DU_SHIFT) | - ((rtc_bin2bcd(newtime.tm_mon + 1)) << RTC_DR_MU_SHIFT) | - ((rtc_bin2bcd(newtime.tm_year - 100)) << RTC_DR_YU_SHIFT); - dr &= ~RTC_DR_RESERVED_BITS; - - /* Disable the write protection for RTC registers */ - - rtc_wprunlock(); - - /* Set Initialization mode */ - - ret = rtc_enterinit(); - if (ret == OK) - { - /* Set the RTC TR and DR registers */ - - putreg32(tr, STM32_RTC_TR); - putreg32(dr, STM32_RTC_DR); - - /* Exit Initialization mode and wait for the RTC Time and Date - * registers to be synchronized with RTC APB clock. - */ - - rtc_exitinit(); - ret = rtc_synchwait(); - } - - /* Re-enable the write protection for RTC registers */ - - rtc_wprlock(); - rtc_dumpregs("New time setting"); - return ret; -} - -/************************************************************************************ - * Name: up_rtc_setalarm - * - * Description: - * Set up an alarm. Up to two alarms can be supported (ALARM A and ALARM B). - * - * Input Parameters: - * tp - the time to set the alarm - * callback - the function to call when the alarm expires. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ************************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -int up_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback); -{ - irqstate_t flags; - int ret = -EBUSY; - - /* Is there already something waiting on the ALARM? */ - - if (g_alarmcb == NULL) - { - /* No.. Save the callback function pointer */ - - g_alarmcb = callback; - - /* Break out the time values */ -#warning "Missing logic" - - /* The set the alarm */ -#warning "Missing logic" - - ret = OK; - } - return ret; -} -#endif - -#endif /* CONFIG_RTC */ -