SAML21: Add some parameter checking for FDPLL96M
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@ -226,6 +226,14 @@
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#define BOARD_DFLL48M_FREQUENCY (48000000)
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#define BOARD_DFLL48M_FREQUENCY (48000000)
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/* Fractional Digital Phase Locked Loop configuration.
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*
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* BOARD_FDPLL96M_REFCLK - See OSCCTRL_DPLLCTRLB_REFLCK_* definitions
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*/
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#undef BOARD_FDPLL96M_ENABLE
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#define BOARD_FDPLL96M_REFCLK OSCCTRL_DPLLCTRLB_REFLCK_XOSC
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/* GCLK Configuration
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/* GCLK Configuration
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*
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*
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* Global enable/disable.
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* Global enable/disable.
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